1 set(LLVM_TARGET_DEFINITIONS AMDGPU.td)
3 tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)
4 tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
5 tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
6 tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
7 tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
8 tablegen(LLVM AMDGPUGenIntrinsics.inc -gen-tgt-intrinsic)
9 tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
10 tablegen(LLVM AMDGPUGenDFAPacketizer.inc -gen-dfa-packetizer)
11 tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
12 tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
13 add_public_tablegen_target(AMDGPUCommonTableGen)
15 add_llvm_target(R600CodeGen
16 AMDILCFGStructurizer.cpp
17 AMDGPUAlwaysInlinePass.cpp
19 AMDGPUFrameLowering.cpp
20 AMDGPUIntrinsicInfo.cpp
21 AMDGPUISelDAGToDAG.cpp
23 AMDGPUMachineFunction.cpp
25 AMDGPUTargetMachine.cpp
26 AMDGPUTargetTransformInfo.cpp
27 AMDGPUISelLowering.cpp
29 AMDGPUPromoteAlloca.cpp
30 AMDGPURegisterInfo.cpp
31 R600ClauseMergePass.cpp
32 R600ControlFlowFinalizer.cpp
33 R600EmitClauseMarkers.cpp
34 R600ExpandSpecialInstrs.cpp
37 R600MachineFunctionInfo.cpp
38 R600MachineScheduler.cpp
39 R600OptimizeVectorRegisters.cpp
42 R600TextureIntrinsicsReplacer.cpp
43 SIAnnotateControlFlow.cpp
45 SIFixSGPRLiveRanges.cpp
50 SILoadStoreOptimizer.cpp
51 SILowerControlFlow.cpp
53 SIMachineFunctionInfo.cpp
54 SIPrepareScratchRegs.cpp
56 SIShrinkInstructions.cpp
60 add_subdirectory(AsmParser)
61 add_subdirectory(InstPrinter)
62 add_subdirectory(TargetInfo)
63 add_subdirectory(MCTargetDesc)