1 //===-- CaymanInstructions.td - CM Instruction defs -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // TableGen definitions for instructions which are available only on Cayman
13 //===----------------------------------------------------------------------===//
15 def isCayman : Predicate<"Subtarget.hasCaymanISA()">;
17 //===----------------------------------------------------------------------===//
18 // Cayman Instructions
19 //===----------------------------------------------------------------------===//
21 let Predicates = [isCayman] in {
23 def MULADD_INT24_cm : R600_3OP <0x08, "MULADD_INT24",
24 [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))], VecALU
26 def MUL_INT24_cm : R600_2OP <0x5B, "MUL_INT24",
27 [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))], VecALU
30 def : IMad24Pat<MULADD_INT24_cm>;
34 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
36 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
37 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
38 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
39 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
40 def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>;
41 def EXP_IEEE_cm : EXP_IEEE_Common<0x81>;
42 def LOG_IEEE_cm : LOG_IEEE_Common<0x83>;
43 def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>;
44 def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>;
45 def SIN_cm : SIN_Common<0x8D>;
46 def COS_cm : COS_Common<0x8E>;
49 def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL>;
51 defm DIV_cm : DIV_Common<RECIP_IEEE_cm>;
52 defm : Expand24UBitOps<MULLO_UINT_cm, ADD_INT>;
54 // RECIP_UINT emulation for Cayman
55 // The multiplication scales from [0,1] to the unsigned integer range
57 (AMDGPUurecip i32:$src0),
58 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)),
59 (MOV_IMM_I32 CONST.FP_UINT_MAX_PLUS_1)))
62 def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> {
69 def : Pat<(fsqrt f32:$src), (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm $src))>;
71 class RAT_STORE_DWORD <RegisterClass rc, ValueType vt, bits<4> mask> :
72 CF_MEM_RAT_CACHELESS <0x14, 0, mask,
73 (ins rc:$rw_gpr, R600_TReg32_X:$index_gpr),
74 "STORE_DWORD $rw_gpr, $index_gpr",
75 [(global_store vt:$rw_gpr, i32:$index_gpr)]> {
76 let eop = 0; // This bit is not used on Cayman.
79 def RAT_STORE_DWORD32 : RAT_STORE_DWORD <R600_TReg32_X, i32, 0x1>;
80 def RAT_STORE_DWORD64 : RAT_STORE_DWORD <R600_Reg64, v2i32, 0x3>;
81 def RAT_STORE_DWORD128 : RAT_STORE_DWORD <R600_Reg128, v4i32, 0xf>;
83 class VTX_READ_cm <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
84 : VTX_WORD0_cm, VTX_READ<name, buffer_id, outs, pattern> {
89 let FETCH_WHOLE_QUAD = 0;
90 let BUFFER_ID = buffer_id;
92 // XXX: We can infer this field based on the SRC_GPR. This would allow us
93 // to store vertex addresses in any channel, not just X.
96 let STRUCTURED_READ = 0;
98 let COALESCED_READ = 0;
100 let Inst{31-0} = Word0;
103 class VTX_READ_8_cm <bits<8> buffer_id, list<dag> pattern>
104 : VTX_READ_cm <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id,
105 (outs R600_TReg32_X:$dst_gpr), pattern> {
108 let DST_SEL_Y = 7; // Masked
109 let DST_SEL_Z = 7; // Masked
110 let DST_SEL_W = 7; // Masked
111 let DATA_FORMAT = 1; // FMT_8
114 class VTX_READ_16_cm <bits<8> buffer_id, list<dag> pattern>
115 : VTX_READ_cm <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id,
116 (outs R600_TReg32_X:$dst_gpr), pattern> {
118 let DST_SEL_Y = 7; // Masked
119 let DST_SEL_Z = 7; // Masked
120 let DST_SEL_W = 7; // Masked
121 let DATA_FORMAT = 5; // FMT_16
125 class VTX_READ_32_cm <bits<8> buffer_id, list<dag> pattern>
126 : VTX_READ_cm <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id,
127 (outs R600_TReg32_X:$dst_gpr), pattern> {
130 let DST_SEL_Y = 7; // Masked
131 let DST_SEL_Z = 7; // Masked
132 let DST_SEL_W = 7; // Masked
133 let DATA_FORMAT = 0xD; // COLOR_32
135 // This is not really necessary, but there were some GPU hangs that appeared
136 // to be caused by ALU instructions in the next instruction group that wrote
137 // to the $src_gpr registers of the VTX_READ.
139 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
140 // %T2_X<def> = MOV %ZERO
141 //Adding this constraint prevents this from happening.
142 let Constraints = "$src_gpr.ptr = $dst_gpr";
145 class VTX_READ_64_cm <bits<8> buffer_id, list<dag> pattern>
146 : VTX_READ_cm <"VTX_READ_64 $dst_gpr, $src_gpr", buffer_id,
147 (outs R600_Reg64:$dst_gpr), pattern> {
153 let DATA_FORMAT = 0x1D; // COLOR_32_32
156 class VTX_READ_128_cm <bits<8> buffer_id, list<dag> pattern>
157 : VTX_READ_cm <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id,
158 (outs R600_Reg128:$dst_gpr), pattern> {
164 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
166 // XXX: Need to force VTX_READ_128 instructions to write to the same register
167 // that holds its buffer address to avoid potential hangs. We can't use
168 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst
169 // registers are different sizes.
172 //===----------------------------------------------------------------------===//
173 // VTX Read from parameter memory space
174 //===----------------------------------------------------------------------===//
175 def VTX_READ_PARAM_8_cm : VTX_READ_8_cm <0,
176 [(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))]
179 def VTX_READ_PARAM_16_cm : VTX_READ_16_cm <0,
180 [(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))]
183 def VTX_READ_PARAM_32_cm : VTX_READ_32_cm <0,
184 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
187 def VTX_READ_PARAM_64_cm : VTX_READ_64_cm <0,
188 [(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
191 def VTX_READ_PARAM_128_cm : VTX_READ_128_cm <0,
192 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
195 //===----------------------------------------------------------------------===//
196 // VTX Read from global memory space
197 //===----------------------------------------------------------------------===//
200 def VTX_READ_GLOBAL_8_cm : VTX_READ_8_cm <1,
201 [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))]
204 def VTX_READ_GLOBAL_16_cm : VTX_READ_16_cm <1,
205 [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))]
209 def VTX_READ_GLOBAL_32_cm : VTX_READ_32_cm <1,
210 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
214 def VTX_READ_GLOBAL_64_cm : VTX_READ_64_cm <1,
215 [(set v2i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
219 def VTX_READ_GLOBAL_128_cm : VTX_READ_128_cm <1,
220 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]