1 //===-- CaymanInstructions.td - CM Instruction defs -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // TableGen definitions for instructions which are available only on Cayman
13 //===----------------------------------------------------------------------===//
15 def isCayman : Predicate<"Subtarget.hasCaymanISA()">;
17 //===----------------------------------------------------------------------===//
18 // Cayman Instructions
19 //===----------------------------------------------------------------------===//
21 let Predicates = [isCayman] in {
23 def MULADD_INT24_cm : R600_3OP <0x08, "MULADD_INT24",
24 [(set i32:$dst, (add (AMDGPUmul_i24 i32:$src0, i32:$src1), i32:$src2))], VecALU
26 def MUL_INT24_cm : R600_2OP <0x5B, "MUL_INT24",
27 [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))], VecALU
32 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
34 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
35 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
36 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
37 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
38 def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>;
39 def EXP_IEEE_cm : EXP_IEEE_Common<0x81>;
40 def LOG_IEEE_cm : LOG_IEEE_Common<0x83>;
41 def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>;
42 def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>;
43 def SIN_cm : SIN_Common<0x8D>;
44 def COS_cm : COS_Common<0x8E>;
47 def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL>;
49 defm DIV_cm : DIV_Common<RECIP_IEEE_cm>;
51 // RECIP_UINT emulation for Cayman
52 // The multiplication scales from [0,1] to the unsigned integer range
54 (AMDGPUurecip i32:$src0),
55 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)),
56 (MOV_IMM_I32 CONST.FP_UINT_MAX_PLUS_1)))
59 def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> {
66 def : Pat<(fsqrt f32:$src), (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm $src))>;
68 class RAT_STORE_DWORD <RegisterClass rc, ValueType vt, bits<4> mask> :
69 CF_MEM_RAT_CACHELESS <0x14, 0, mask,
70 (ins rc:$rw_gpr, R600_TReg32_X:$index_gpr),
71 "STORE_DWORD $rw_gpr, $index_gpr",
72 [(global_store vt:$rw_gpr, i32:$index_gpr)]> {
73 let eop = 0; // This bit is not used on Cayman.
76 def RAT_STORE_DWORD32 : RAT_STORE_DWORD <R600_TReg32_X, i32, 0x1>;
77 def RAT_STORE_DWORD64 : RAT_STORE_DWORD <R600_Reg64, v2i32, 0x3>;
78 def RAT_STORE_DWORD128 : RAT_STORE_DWORD <R600_Reg128, v4i32, 0xf>;
80 class VTX_READ_cm <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
81 : VTX_WORD0_cm, VTX_READ<name, buffer_id, outs, pattern> {
86 let FETCH_WHOLE_QUAD = 0;
87 let BUFFER_ID = buffer_id;
89 // XXX: We can infer this field based on the SRC_GPR. This would allow us
90 // to store vertex addresses in any channel, not just X.
93 let STRUCTURED_READ = 0;
95 let COALESCED_READ = 0;
97 let Inst{31-0} = Word0;
100 class VTX_READ_8_cm <bits<8> buffer_id, list<dag> pattern>
101 : VTX_READ_cm <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id,
102 (outs R600_TReg32_X:$dst_gpr), pattern> {
105 let DST_SEL_Y = 7; // Masked
106 let DST_SEL_Z = 7; // Masked
107 let DST_SEL_W = 7; // Masked
108 let DATA_FORMAT = 1; // FMT_8
111 class VTX_READ_16_cm <bits<8> buffer_id, list<dag> pattern>
112 : VTX_READ_cm <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id,
113 (outs R600_TReg32_X:$dst_gpr), pattern> {
115 let DST_SEL_Y = 7; // Masked
116 let DST_SEL_Z = 7; // Masked
117 let DST_SEL_W = 7; // Masked
118 let DATA_FORMAT = 5; // FMT_16
122 class VTX_READ_32_cm <bits<8> buffer_id, list<dag> pattern>
123 : VTX_READ_cm <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id,
124 (outs R600_TReg32_X:$dst_gpr), pattern> {
127 let DST_SEL_Y = 7; // Masked
128 let DST_SEL_Z = 7; // Masked
129 let DST_SEL_W = 7; // Masked
130 let DATA_FORMAT = 0xD; // COLOR_32
132 // This is not really necessary, but there were some GPU hangs that appeared
133 // to be caused by ALU instructions in the next instruction group that wrote
134 // to the $src_gpr registers of the VTX_READ.
136 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
137 // %T2_X<def> = MOV %ZERO
138 //Adding this constraint prevents this from happening.
139 let Constraints = "$src_gpr.ptr = $dst_gpr";
142 class VTX_READ_64_cm <bits<8> buffer_id, list<dag> pattern>
143 : VTX_READ_cm <"VTX_READ_64 $dst_gpr, $src_gpr", buffer_id,
144 (outs R600_Reg64:$dst_gpr), pattern> {
150 let DATA_FORMAT = 0x1D; // COLOR_32_32
153 class VTX_READ_128_cm <bits<8> buffer_id, list<dag> pattern>
154 : VTX_READ_cm <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id,
155 (outs R600_Reg128:$dst_gpr), pattern> {
161 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
163 // XXX: Need to force VTX_READ_128 instructions to write to the same register
164 // that holds its buffer address to avoid potential hangs. We can't use
165 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst
166 // registers are different sizes.
169 //===----------------------------------------------------------------------===//
170 // VTX Read from parameter memory space
171 //===----------------------------------------------------------------------===//
172 def VTX_READ_PARAM_8_cm : VTX_READ_8_cm <0,
173 [(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))]
176 def VTX_READ_PARAM_16_cm : VTX_READ_16_cm <0,
177 [(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))]
180 def VTX_READ_PARAM_32_cm : VTX_READ_32_cm <0,
181 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
184 def VTX_READ_PARAM_64_cm : VTX_READ_64_cm <0,
185 [(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
188 def VTX_READ_PARAM_128_cm : VTX_READ_128_cm <0,
189 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
192 //===----------------------------------------------------------------------===//
193 // VTX Read from global memory space
194 //===----------------------------------------------------------------------===//
197 def VTX_READ_GLOBAL_8_cm : VTX_READ_8_cm <1,
198 [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))]
201 def VTX_READ_GLOBAL_16_cm : VTX_READ_16_cm <1,
202 [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))]
206 def VTX_READ_GLOBAL_32_cm : VTX_READ_32_cm <1,
207 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
211 def VTX_READ_GLOBAL_64_cm : VTX_READ_64_cm <1,
212 [(set v2i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
216 def VTX_READ_GLOBAL_128_cm : VTX_READ_128_cm <1,
217 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]