1 //===-- EvergreenInstructions.td - EG Instruction defs ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // TableGen definitions for instructions which are:
11 // - Available to Evergreen and newer VLIW4/VLIW5 GPUs
12 // - Available only on Evergreen family GPUs.
14 //===----------------------------------------------------------------------===//
17 "Subtarget.getGeneration() >= AMDGPUSubtarget::EVERGREEN && "
18 "Subtarget.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && "
19 "!Subtarget.hasCaymanISA()"
22 def isEGorCayman : Predicate<
23 "Subtarget.getGeneration() == AMDGPUSubtarget::EVERGREEN ||"
24 "Subtarget.getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS"
27 //===----------------------------------------------------------------------===//
28 // Evergreen / Cayman store instructions
29 //===----------------------------------------------------------------------===//
31 let Predicates = [isEGorCayman] in {
33 class CF_MEM_RAT_CACHELESS <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins,
34 string name, list<dag> pattern>
35 : EG_CF_RAT <0x57, rat_inst, rat_id, mask, (outs), ins,
36 "MEM_RAT_CACHELESS "#name, pattern>;
38 class CF_MEM_RAT <bits<6> rat_inst, bits<4> rat_id, dag ins, string name,
40 : EG_CF_RAT <0x56, rat_inst, rat_id, 0xf /* mask */, (outs), ins,
41 "MEM_RAT "#name, pattern>;
43 def RAT_MSKOR : CF_MEM_RAT <0x11, 0,
44 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr),
45 "MSKOR $rw_gpr.XW, $index_gpr",
46 [(mskor_global v4i32:$rw_gpr, i32:$index_gpr)]
51 } // End let Predicates = [isEGorCayman]
53 //===----------------------------------------------------------------------===//
54 // Evergreen Only instructions
55 //===----------------------------------------------------------------------===//
57 let Predicates = [isEG] in {
59 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
60 defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
62 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
63 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
64 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
65 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
66 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
67 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
68 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
69 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
70 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
71 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
72 def SIN_eg : SIN_Common<0x8D>;
73 def COS_eg : COS_Common<0x8E>;
75 def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>;
76 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>;
78 defm : Expand24IBitOps<MULLO_INT_eg, ADD_INT>;
80 //===----------------------------------------------------------------------===//
81 // Memory read/write instructions
82 //===----------------------------------------------------------------------===//
84 let usesCustomInserter = 1 in {
87 def RAT_WRITE_CACHELESS_32_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x1,
88 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
89 "STORE_RAW $rw_gpr, $index_gpr, $eop",
90 [(global_store i32:$rw_gpr, i32:$index_gpr)]
94 def RAT_WRITE_CACHELESS_64_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x3,
95 (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
96 "STORE_RAW $rw_gpr.XY, $index_gpr, $eop",
97 [(global_store v2i32:$rw_gpr, i32:$index_gpr)]
101 def RAT_WRITE_CACHELESS_128_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0xf,
102 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
103 "STORE_RAW $rw_gpr.XYZW, $index_gpr, $eop",
104 [(global_store v4i32:$rw_gpr, i32:$index_gpr)]
107 } // End usesCustomInserter = 1
109 class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
110 : VTX_WORD0_eg, VTX_READ<name, buffer_id, outs, pattern> {
115 let FETCH_WHOLE_QUAD = 0;
116 let BUFFER_ID = buffer_id;
118 // XXX: We can infer this field based on the SRC_GPR. This would allow us
119 // to store vertex addresses in any channel, not just X.
122 let Inst{31-0} = Word0;
125 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
126 : VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id,
127 (outs R600_TReg32_X:$dst_gpr), pattern> {
129 let MEGA_FETCH_COUNT = 1;
131 let DST_SEL_Y = 7; // Masked
132 let DST_SEL_Z = 7; // Masked
133 let DST_SEL_W = 7; // Masked
134 let DATA_FORMAT = 1; // FMT_8
137 class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
138 : VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id,
139 (outs R600_TReg32_X:$dst_gpr), pattern> {
140 let MEGA_FETCH_COUNT = 2;
142 let DST_SEL_Y = 7; // Masked
143 let DST_SEL_Z = 7; // Masked
144 let DST_SEL_W = 7; // Masked
145 let DATA_FORMAT = 5; // FMT_16
149 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
150 : VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id,
151 (outs R600_TReg32_X:$dst_gpr), pattern> {
153 let MEGA_FETCH_COUNT = 4;
155 let DST_SEL_Y = 7; // Masked
156 let DST_SEL_Z = 7; // Masked
157 let DST_SEL_W = 7; // Masked
158 let DATA_FORMAT = 0xD; // COLOR_32
160 // This is not really necessary, but there were some GPU hangs that appeared
161 // to be caused by ALU instructions in the next instruction group that wrote
162 // to the $src_gpr registers of the VTX_READ.
164 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
165 // %T2_X<def> = MOV %ZERO
166 //Adding this constraint prevents this from happening.
167 let Constraints = "$src_gpr.ptr = $dst_gpr";
170 class VTX_READ_64_eg <bits<8> buffer_id, list<dag> pattern>
171 : VTX_READ_eg <"VTX_READ_64 $dst_gpr.XY, $src_gpr", buffer_id,
172 (outs R600_Reg64:$dst_gpr), pattern> {
174 let MEGA_FETCH_COUNT = 8;
179 let DATA_FORMAT = 0x1D; // COLOR_32_32
182 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
183 : VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id,
184 (outs R600_Reg128:$dst_gpr), pattern> {
186 let MEGA_FETCH_COUNT = 16;
191 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
193 // XXX: Need to force VTX_READ_128 instructions to write to the same register
194 // that holds its buffer address to avoid potential hangs. We can't use
195 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst
196 // registers are different sizes.
199 //===----------------------------------------------------------------------===//
200 // VTX Read from parameter memory space
201 //===----------------------------------------------------------------------===//
203 def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <0,
204 [(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))]
207 def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <0,
208 [(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))]
211 def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0,
212 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
215 def VTX_READ_PARAM_64_eg : VTX_READ_64_eg <0,
216 [(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
219 def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <0,
220 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
223 //===----------------------------------------------------------------------===//
224 // VTX Read from global memory space
225 //===----------------------------------------------------------------------===//
228 def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1,
229 [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))]
232 def VTX_READ_GLOBAL_16_eg : VTX_READ_16_eg <1,
233 [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))]
237 def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1,
238 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
242 def VTX_READ_GLOBAL_64_eg : VTX_READ_64_eg <1,
243 [(set v2i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
247 def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
248 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
251 } // End Predicates = [isEG]
253 //===----------------------------------------------------------------------===//
254 // Evergreen / Cayman Instructions
255 //===----------------------------------------------------------------------===//
257 let Predicates = [isEGorCayman] in {
259 // BFE_UINT - bit_extract, an optimization for mask and shift
264 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
269 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0
270 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
271 // (16, 8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
272 // (24, 8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
273 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
274 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))],
278 def BFE_INT_eg : R600_3OP <0x5, "BFE_INT",
279 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))],
283 // XXX: This pattern is broken, disabling for now. See comment in
284 // AMDGPUInstructions.td for more info.
285 // def : BFEPattern <BFE_UINT_eg>;
286 def BFI_INT_eg : R600_3OP <0x06, "BFI_INT",
287 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))],
291 def : Pat<(i32 (sext_inreg i32:$src, i1)),
292 (BFE_INT_eg i32:$src, (i32 ZERO), (i32 ONE_INT))>;
293 def : Pat<(i32 (sext_inreg i32:$src, i8)),
294 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 8))>;
295 def : Pat<(i32 (sext_inreg i32:$src, i16)),
296 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 16))>;
298 defm : BFIPatterns <BFI_INT_eg>;
300 def BFM_INT_eg : R600_2OP <0xA0, "BFM_INT",
301 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))],
305 def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24",
306 [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))], VecALU
309 def : UMad24Pat<MULADD_UINT24_eg>;
311 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>;
312 def : ROTRPattern <BIT_ALIGN_INT_eg>;
313 def MULADD_eg : MULADD_Common<0x14>;
314 def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>;
315 def ASHR_eg : ASHR_Common<0x15>;
316 def LSHR_eg : LSHR_Common<0x16>;
317 def LSHL_eg : LSHL_Common<0x17>;
318 def CNDE_eg : CNDE_Common<0x19>;
319 def CNDGT_eg : CNDGT_Common<0x1A>;
320 def CNDGE_eg : CNDGE_Common<0x1B>;
321 def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
322 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
323 def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24",
324 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))], VecALU
326 def DOT4_eg : DOT4_Common<0xBE>;
327 defm CUBE_eg : CUBE_Common<0xC0>;
329 let hasSideEffects = 1 in {
330 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", [], VecALU>;
333 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
335 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
337 let Itinerary = AnyALU;
340 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
342 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
346 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
348 def GROUP_BARRIER : InstR600 <
349 (outs), (ins), " GROUP_BARRIER", [(int_AMDGPU_barrier_local)], AnyALU>,
351 R600ALU_Word1_OP2 <0x54> {
367 let bank_swizzle = 0;
369 let update_exec_mask = 0;
372 let Inst{31-0} = Word0;
373 let Inst{63-32} = Word1;
378 //===----------------------------------------------------------------------===//
380 //===----------------------------------------------------------------------===//
381 class R600_LDS <bits<6> op, dag outs, dag ins, string asm,
382 list<dag> pattern = []> :
384 InstR600 <outs, ins, asm, pattern, XALU>,
391 let Word1{27} = offset{0};
392 let Word1{12} = offset{1};
393 let Word1{28} = offset{2};
394 let Word1{31} = offset{3};
395 let Word0{12} = offset{4};
396 let Word0{25} = offset{5};
399 let Inst{31-0} = Word0;
400 let Inst{63-32} = Word1;
403 let HasNativeOperands = 1;
404 let UseNamedOperandTable = 1;
407 class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS <
409 (outs R600_Reg32:$dst),
410 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
411 LAST:$last, R600_Pred:$pred_sel,
412 BANK_SWIZZLE:$bank_swizzle),
413 " "#name#" $last OQAP, $src0$src0_rel $pred_sel",
422 let usesCustomInserter = 1;
424 let DisableEncoding = "$dst";
427 class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern,
431 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
432 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
433 LAST:$last, R600_Pred:$pred_sel,
434 BANK_SWIZZLE:$bank_swizzle),
435 " "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel",
446 class R600_LDS_1A1D_NORET <bits<6> lds_op, string name, list<dag> pattern> :
447 R600_LDS_1A1D <lds_op, (outs), name, pattern> {
451 class R600_LDS_1A1D_RET <bits<6> lds_op, string name, list<dag> pattern> :
452 R600_LDS_1A1D <lds_op, (outs R600_Reg32:$dst), name##"_RET", pattern, "OQAP, "> {
455 let usesCustomInserter = 1;
456 let DisableEncoding = "$dst";
459 class R600_LDS_1A2D <bits<6> lds_op, string name, list<dag> pattern> :
463 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
464 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
465 R600_Reg32:$src2, REL:$src2_rel, SEL:$src2_sel,
466 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle),
467 " "#name# "$last $src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel",
472 def LDS_ADD : R600_LDS_1A1D_NORET <0x0, "LDS_ADD", [] >;
473 def LDS_SUB : R600_LDS_1A1D_NORET <0x1, "LDS_SUB", [] >;
474 def LDS_WRITE : R600_LDS_1A1D_NORET <0xD, "LDS_WRITE",
475 [(local_store (i32 R600_Reg32:$src1), R600_Reg32:$src0)]
477 def LDS_BYTE_WRITE : R600_LDS_1A1D_NORET<0x12, "LDS_BYTE_WRITE",
478 [(truncstorei8_local i32:$src1, i32:$src0)]
480 def LDS_SHORT_WRITE : R600_LDS_1A1D_NORET<0x13, "LDS_SHORT_WRITE",
481 [(truncstorei16_local i32:$src1, i32:$src0)]
483 def LDS_ADD_RET : R600_LDS_1A1D_RET <0x20, "LDS_ADD",
484 [(set i32:$dst, (atomic_load_add_local i32:$src0, i32:$src1))]
486 def LDS_SUB_RET : R600_LDS_1A1D_RET <0x21, "LDS_SUB",
487 [(set i32:$dst, (atomic_load_sub_local i32:$src0, i32:$src1))]
489 def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET",
490 [(set (i32 R600_Reg32:$dst), (local_load R600_Reg32:$src0))]
492 def LDS_BYTE_READ_RET : R600_LDS_1A <0x36, "LDS_BYTE_READ_RET",
493 [(set i32:$dst, (sextloadi8_local i32:$src0))]
495 def LDS_UBYTE_READ_RET : R600_LDS_1A <0x37, "LDS_UBYTE_READ_RET",
496 [(set i32:$dst, (az_extloadi8_local i32:$src0))]
498 def LDS_SHORT_READ_RET : R600_LDS_1A <0x38, "LDS_SHORT_READ_RET",
499 [(set i32:$dst, (sextloadi16_local i32:$src0))]
501 def LDS_USHORT_READ_RET : R600_LDS_1A <0x39, "LDS_USHORT_READ_RET",
502 [(set i32:$dst, (az_extloadi16_local i32:$src0))]
505 // TRUNC is used for the FLT_TO_INT instructions to work around a
506 // perceived problem where the rounding modes are applied differently
507 // depending on the instruction and the slot they are in.
509 // https://bugs.freedesktop.org/show_bug.cgi?id=50232
510 // Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c
512 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
513 // which do not need to be truncated since the fp values are 0.0f or 1.0f.
514 // We should look into handling these cases separately.
515 def : Pat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>;
517 def : Pat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>;
520 def : SHA256MaPattern <BFI_INT_eg, XOR_INT>;
522 def : FROUNDPat <CNDGE_eg>;
524 def EG_ExportSwz : ExportSwzInst {
525 let Word1{19-16} = 0; // BURST_COUNT
526 let Word1{20} = 0; // VALID_PIXEL_MODE
528 let Word1{29-22} = inst;
529 let Word1{30} = 0; // MARK
530 let Word1{31} = 1; // BARRIER
532 defm : ExportPattern<EG_ExportSwz, 83>;
534 def EG_ExportBuf : ExportBufInst {
535 let Word1{19-16} = 0; // BURST_COUNT
536 let Word1{20} = 0; // VALID_PIXEL_MODE
538 let Word1{29-22} = inst;
539 let Word1{30} = 0; // MARK
540 let Word1{31} = 1; // BARRIER
542 defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>;
544 def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT),
545 "TEX $COUNT @$ADDR"> {
548 def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT),
549 "VTX $COUNT @$ADDR"> {
552 def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR),
553 "LOOP_START_DX10 @$ADDR"> {
557 def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
561 def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR),
562 "LOOP_BREAK @$ADDR"> {
566 def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR),
571 def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
572 "JUMP @$ADDR POP:$POP_COUNT"> {
575 def CF_PUSH_EG : CF_CLAUSE_EG<11, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
576 "PUSH @$ADDR POP:$POP_COUNT"> {
579 def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
580 "ELSE @$ADDR POP:$POP_COUNT"> {
583 def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> {
588 def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
589 "POP @$ADDR POP:$POP_COUNT"> {
592 def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> {
596 let END_OF_PROGRAM = 1;
599 } // End Predicates = [isEGorCayman]