1 //===-- EvergreenInstructions.td - EG Instruction defs ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // TableGen definitions for instructions which are:
11 // - Available to Evergreen and newer VLIW4/VLIW5 GPUs
12 // - Available only on Evergreen family GPUs.
14 //===----------------------------------------------------------------------===//
17 "Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && "
18 "Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && "
19 "!Subtarget->hasCaymanISA()"
22 def isEGorCayman : Predicate<
23 "Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||"
24 "Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS"
27 //===----------------------------------------------------------------------===//
28 // Evergreen / Cayman store instructions
29 //===----------------------------------------------------------------------===//
31 let Predicates = [isEGorCayman] in {
33 class CF_MEM_RAT_CACHELESS <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins,
34 string name, list<dag> pattern>
35 : EG_CF_RAT <0x57, rat_inst, rat_id, mask, (outs), ins,
36 "MEM_RAT_CACHELESS "#name, pattern>;
38 class CF_MEM_RAT <bits<6> rat_inst, bits<4> rat_id, dag ins, string name,
40 : EG_CF_RAT <0x56, rat_inst, rat_id, 0xf /* mask */, (outs), ins,
41 "MEM_RAT "#name, pattern>;
43 def RAT_MSKOR : CF_MEM_RAT <0x11, 0,
44 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr),
45 "MSKOR $rw_gpr.XW, $index_gpr",
46 [(mskor_global v4i32:$rw_gpr, i32:$index_gpr)]
51 } // End let Predicates = [isEGorCayman]
53 //===----------------------------------------------------------------------===//
54 // Evergreen Only instructions
55 //===----------------------------------------------------------------------===//
57 let Predicates = [isEG] in {
59 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
60 defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
62 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
63 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
64 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
65 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
66 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
67 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
68 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
69 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
70 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
71 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
72 def : RsqPat<RECIPSQRT_IEEE_eg, f32>;
73 def SIN_eg : SIN_Common<0x8D>;
74 def COS_eg : COS_Common<0x8E>;
76 def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>;
77 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>;
79 defm : Expand24IBitOps<MULLO_INT_eg, ADD_INT>;
81 //===----------------------------------------------------------------------===//
82 // Memory read/write instructions
83 //===----------------------------------------------------------------------===//
85 let usesCustomInserter = 1 in {
88 def RAT_WRITE_CACHELESS_32_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x1,
89 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
90 "STORE_RAW $rw_gpr, $index_gpr, $eop",
91 [(global_store i32:$rw_gpr, i32:$index_gpr)]
95 def RAT_WRITE_CACHELESS_64_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x3,
96 (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
97 "STORE_RAW $rw_gpr.XY, $index_gpr, $eop",
98 [(global_store v2i32:$rw_gpr, i32:$index_gpr)]
102 def RAT_WRITE_CACHELESS_128_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0xf,
103 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
104 "STORE_RAW $rw_gpr.XYZW, $index_gpr, $eop",
105 [(global_store v4i32:$rw_gpr, i32:$index_gpr)]
108 } // End usesCustomInserter = 1
110 class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
111 : VTX_WORD0_eg, VTX_READ<name, buffer_id, outs, pattern> {
116 let FETCH_WHOLE_QUAD = 0;
117 let BUFFER_ID = buffer_id;
119 // XXX: We can infer this field based on the SRC_GPR. This would allow us
120 // to store vertex addresses in any channel, not just X.
123 let Inst{31-0} = Word0;
126 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
127 : VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id,
128 (outs R600_TReg32_X:$dst_gpr), pattern> {
130 let MEGA_FETCH_COUNT = 1;
132 let DST_SEL_Y = 7; // Masked
133 let DST_SEL_Z = 7; // Masked
134 let DST_SEL_W = 7; // Masked
135 let DATA_FORMAT = 1; // FMT_8
138 class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
139 : VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id,
140 (outs R600_TReg32_X:$dst_gpr), pattern> {
141 let MEGA_FETCH_COUNT = 2;
143 let DST_SEL_Y = 7; // Masked
144 let DST_SEL_Z = 7; // Masked
145 let DST_SEL_W = 7; // Masked
146 let DATA_FORMAT = 5; // FMT_16
150 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
151 : VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id,
152 (outs R600_TReg32_X:$dst_gpr), pattern> {
154 let MEGA_FETCH_COUNT = 4;
156 let DST_SEL_Y = 7; // Masked
157 let DST_SEL_Z = 7; // Masked
158 let DST_SEL_W = 7; // Masked
159 let DATA_FORMAT = 0xD; // COLOR_32
161 // This is not really necessary, but there were some GPU hangs that appeared
162 // to be caused by ALU instructions in the next instruction group that wrote
163 // to the $src_gpr registers of the VTX_READ.
165 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
166 // %T2_X<def> = MOV %ZERO
167 //Adding this constraint prevents this from happening.
168 let Constraints = "$src_gpr.ptr = $dst_gpr";
171 class VTX_READ_64_eg <bits<8> buffer_id, list<dag> pattern>
172 : VTX_READ_eg <"VTX_READ_64 $dst_gpr.XY, $src_gpr", buffer_id,
173 (outs R600_Reg64:$dst_gpr), pattern> {
175 let MEGA_FETCH_COUNT = 8;
180 let DATA_FORMAT = 0x1D; // COLOR_32_32
183 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
184 : VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id,
185 (outs R600_Reg128:$dst_gpr), pattern> {
187 let MEGA_FETCH_COUNT = 16;
192 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
194 // XXX: Need to force VTX_READ_128 instructions to write to the same register
195 // that holds its buffer address to avoid potential hangs. We can't use
196 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst
197 // registers are different sizes.
200 //===----------------------------------------------------------------------===//
201 // VTX Read from parameter memory space
202 //===----------------------------------------------------------------------===//
204 def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <0,
205 [(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))]
208 def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <0,
209 [(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))]
212 def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0,
213 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
216 def VTX_READ_PARAM_64_eg : VTX_READ_64_eg <0,
217 [(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
220 def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <0,
221 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
224 //===----------------------------------------------------------------------===//
225 // VTX Read from global memory space
226 //===----------------------------------------------------------------------===//
229 def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1,
230 [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))]
233 def VTX_READ_GLOBAL_16_eg : VTX_READ_16_eg <1,
234 [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))]
238 def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1,
239 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
243 def VTX_READ_GLOBAL_64_eg : VTX_READ_64_eg <1,
244 [(set v2i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
248 def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
249 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
252 } // End Predicates = [isEG]
254 //===----------------------------------------------------------------------===//
255 // Evergreen / Cayman Instructions
256 //===----------------------------------------------------------------------===//
258 let Predicates = [isEGorCayman] in {
260 // Should be predicated on FeatureFP64
261 // def FMA_64 : R600_3OP <
263 // [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
266 // BFE_UINT - bit_extract, an optimization for mask and shift
271 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
276 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0
277 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
278 // (16, 8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
279 // (24, 8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
280 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
281 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))],
285 def BFE_INT_eg : R600_3OP <0x5, "BFE_INT",
286 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))],
290 // XXX: This pattern is broken, disabling for now. See comment in
291 // AMDGPUInstructions.td for more info.
292 // def : BFEPattern <BFE_UINT_eg>;
293 def BFI_INT_eg : R600_3OP <0x06, "BFI_INT",
294 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))],
298 def : Pat<(i32 (sext_inreg i32:$src, i1)),
299 (BFE_INT_eg i32:$src, (i32 ZERO), (i32 ONE_INT))>;
300 def : Pat<(i32 (sext_inreg i32:$src, i8)),
301 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 8))>;
302 def : Pat<(i32 (sext_inreg i32:$src, i16)),
303 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 16))>;
305 defm : BFIPatterns <BFI_INT_eg, MOV_IMM_I32, R600_Reg64>;
307 def BFM_INT_eg : R600_2OP <0xA0, "BFM_INT",
308 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))],
312 def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24",
313 [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))], VecALU
316 def : UMad24Pat<MULADD_UINT24_eg>;
318 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>;
319 def : ROTRPattern <BIT_ALIGN_INT_eg>;
320 def MULADD_eg : MULADD_Common<0x14>;
321 def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>;
322 def FMA_eg : FMA_Common<0x7>;
323 def ASHR_eg : ASHR_Common<0x15>;
324 def LSHR_eg : LSHR_Common<0x16>;
325 def LSHL_eg : LSHL_Common<0x17>;
326 def CNDE_eg : CNDE_Common<0x19>;
327 def CNDGT_eg : CNDGT_Common<0x1A>;
328 def CNDGE_eg : CNDGE_Common<0x1B>;
329 def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
330 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
331 def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24",
332 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))], VecALU
334 def DOT4_eg : DOT4_Common<0xBE>;
335 defm CUBE_eg : CUBE_Common<0xC0>;
337 def BCNT_INT : R600_1OP_Helper <0xAA, "BCNT_INT", ctpop, VecALU>;
339 def FFBH_UINT : R600_1OP_Helper <0xAB, "FFBH_UINT", ctlz_zero_undef, VecALU>;
340 def FFBL_INT : R600_1OP_Helper <0xAC, "FFBL_INT", cttz_zero_undef, VecALU>;
342 let hasSideEffects = 1 in {
343 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", [], VecALU>;
346 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
348 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
350 let Itinerary = AnyALU;
353 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
355 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
359 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
361 def GROUP_BARRIER : InstR600 <
362 (outs), (ins), " GROUP_BARRIER", [(int_AMDGPU_barrier_local), (int_AMDGPU_barrier_global)], AnyALU>,
364 R600ALU_Word1_OP2 <0x54> {
380 let bank_swizzle = 0;
382 let update_exec_mask = 0;
385 let Inst{31-0} = Word0;
386 let Inst{63-32} = Word1;
392 (int_AMDGPU_barrier_global),
396 //===----------------------------------------------------------------------===//
398 //===----------------------------------------------------------------------===//
399 class R600_LDS <bits<6> op, dag outs, dag ins, string asm,
400 list<dag> pattern = []> :
402 InstR600 <outs, ins, asm, pattern, XALU>,
409 let Word1{27} = offset{0};
410 let Word1{12} = offset{1};
411 let Word1{28} = offset{2};
412 let Word1{31} = offset{3};
413 let Word0{12} = offset{4};
414 let Word0{25} = offset{5};
417 let Inst{31-0} = Word0;
418 let Inst{63-32} = Word1;
421 let HasNativeOperands = 1;
422 let UseNamedOperandTable = 1;
425 class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS <
427 (outs R600_Reg32:$dst),
428 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
429 LAST:$last, R600_Pred:$pred_sel,
430 BANK_SWIZZLE:$bank_swizzle),
431 " "#name#" $last OQAP, $src0$src0_rel $pred_sel",
440 let usesCustomInserter = 1;
442 let DisableEncoding = "$dst";
445 class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern,
449 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
450 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
451 LAST:$last, R600_Pred:$pred_sel,
452 BANK_SWIZZLE:$bank_swizzle),
453 " "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel",
464 class R600_LDS_1A1D_NORET <bits<6> lds_op, string name, list<dag> pattern> :
465 R600_LDS_1A1D <lds_op, (outs), name, pattern> {
469 class R600_LDS_1A1D_RET <bits<6> lds_op, string name, list<dag> pattern> :
470 R600_LDS_1A1D <lds_op, (outs R600_Reg32:$dst), name##"_RET", pattern, "OQAP, "> {
473 let usesCustomInserter = 1;
474 let DisableEncoding = "$dst";
477 class R600_LDS_1A2D <bits<6> lds_op, dag outs, string name, list<dag> pattern,
481 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
482 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
483 R600_Reg32:$src2, REL:$src2_rel, SEL:$src2_sel,
484 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle),
485 " "#name# "$last "#dst#"$src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel",
494 class R600_LDS_1A2D_NORET <bits<6> lds_op, string name, list<dag> pattern> :
495 R600_LDS_1A2D <lds_op, (outs), name, pattern> {
499 class R600_LDS_1A2D_RET <bits<6> lds_op, string name, list<dag> pattern> :
500 R600_LDS_1A2D <lds_op, (outs R600_Reg32:$dst), name, pattern> {
503 let usesCustomInserter = 1;
504 let DisableEncoding = "$dst";
507 def LDS_ADD : R600_LDS_1A1D_NORET <0x0, "LDS_ADD", [] >;
508 def LDS_SUB : R600_LDS_1A1D_NORET <0x1, "LDS_SUB", [] >;
509 def LDS_AND : R600_LDS_1A1D_NORET <0x9, "LDS_AND", [] >;
510 def LDS_OR : R600_LDS_1A1D_NORET <0xa, "LDS_OR", [] >;
511 def LDS_XOR : R600_LDS_1A1D_NORET <0xb, "LDS_XOR", [] >;
512 def LDS_WRXCHG: R600_LDS_1A1D_NORET <0xd, "LDS_WRXCHG", [] >;
513 def LDS_CMPST: R600_LDS_1A2D_NORET <0x10, "LDS_CMPST", [] >;
514 def LDS_MIN_INT : R600_LDS_1A1D_NORET <0x5, "LDS_MIN_INT", [] >;
515 def LDS_MAX_INT : R600_LDS_1A1D_NORET <0x6, "LDS_MAX_INT", [] >;
516 def LDS_MIN_UINT : R600_LDS_1A1D_NORET <0x7, "LDS_MIN_UINT", [] >;
517 def LDS_MAX_UINT : R600_LDS_1A1D_NORET <0x8, "LDS_MAX_UINT", [] >;
518 def LDS_WRITE : R600_LDS_1A1D_NORET <0xD, "LDS_WRITE",
519 [(local_store (i32 R600_Reg32:$src1), R600_Reg32:$src0)]
521 def LDS_BYTE_WRITE : R600_LDS_1A1D_NORET<0x12, "LDS_BYTE_WRITE",
522 [(truncstorei8_local i32:$src1, i32:$src0)]
524 def LDS_SHORT_WRITE : R600_LDS_1A1D_NORET<0x13, "LDS_SHORT_WRITE",
525 [(truncstorei16_local i32:$src1, i32:$src0)]
527 def LDS_ADD_RET : R600_LDS_1A1D_RET <0x20, "LDS_ADD",
528 [(set i32:$dst, (atomic_load_add_local i32:$src0, i32:$src1))]
530 def LDS_SUB_RET : R600_LDS_1A1D_RET <0x21, "LDS_SUB",
531 [(set i32:$dst, (atomic_load_sub_local i32:$src0, i32:$src1))]
533 def LDS_AND_RET : R600_LDS_1A1D_RET <0x29, "LDS_AND",
534 [(set i32:$dst, (atomic_load_and_local i32:$src0, i32:$src1))]
536 def LDS_OR_RET : R600_LDS_1A1D_RET <0x2a, "LDS_OR",
537 [(set i32:$dst, (atomic_load_or_local i32:$src0, i32:$src1))]
539 def LDS_XOR_RET : R600_LDS_1A1D_RET <0x2b, "LDS_XOR",
540 [(set i32:$dst, (atomic_load_xor_local i32:$src0, i32:$src1))]
542 def LDS_MIN_INT_RET : R600_LDS_1A1D_RET <0x25, "LDS_MIN_INT",
543 [(set i32:$dst, (atomic_load_min_local i32:$src0, i32:$src1))]
545 def LDS_MAX_INT_RET : R600_LDS_1A1D_RET <0x26, "LDS_MAX_INT",
546 [(set i32:$dst, (atomic_load_max_local i32:$src0, i32:$src1))]
548 def LDS_MIN_UINT_RET : R600_LDS_1A1D_RET <0x27, "LDS_MIN_UINT",
549 [(set i32:$dst, (atomic_load_umin_local i32:$src0, i32:$src1))]
551 def LDS_MAX_UINT_RET : R600_LDS_1A1D_RET <0x28, "LDS_MAX_UINT",
552 [(set i32:$dst, (atomic_load_umax_local i32:$src0, i32:$src1))]
554 def LDS_WRXCHG_RET : R600_LDS_1A1D_RET <0x2d, "LDS_WRXCHG",
555 [(set i32:$dst, (atomic_swap_local i32:$src0, i32:$src1))]
557 def LDS_CMPST_RET : R600_LDS_1A2D_RET <0x30, "LDS_CMPST",
558 [(set i32:$dst, (atomic_cmp_swap_32_local i32:$src0, i32:$src1, i32:$src2))]
560 def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET",
561 [(set (i32 R600_Reg32:$dst), (local_load R600_Reg32:$src0))]
563 def LDS_BYTE_READ_RET : R600_LDS_1A <0x36, "LDS_BYTE_READ_RET",
564 [(set i32:$dst, (sextloadi8_local i32:$src0))]
566 def LDS_UBYTE_READ_RET : R600_LDS_1A <0x37, "LDS_UBYTE_READ_RET",
567 [(set i32:$dst, (az_extloadi8_local i32:$src0))]
569 def LDS_SHORT_READ_RET : R600_LDS_1A <0x38, "LDS_SHORT_READ_RET",
570 [(set i32:$dst, (sextloadi16_local i32:$src0))]
572 def LDS_USHORT_READ_RET : R600_LDS_1A <0x39, "LDS_USHORT_READ_RET",
573 [(set i32:$dst, (az_extloadi16_local i32:$src0))]
576 // TRUNC is used for the FLT_TO_INT instructions to work around a
577 // perceived problem where the rounding modes are applied differently
578 // depending on the instruction and the slot they are in.
580 // https://bugs.freedesktop.org/show_bug.cgi?id=50232
581 // Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c
583 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
584 // which do not need to be truncated since the fp values are 0.0f or 1.0f.
585 // We should look into handling these cases separately.
586 def : Pat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>;
588 def : Pat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>;
591 def : SHA256MaPattern <BFI_INT_eg, XOR_INT>;
593 def EG_ExportSwz : ExportSwzInst {
594 let Word1{19-16} = 0; // BURST_COUNT
595 let Word1{20} = 0; // VALID_PIXEL_MODE
597 let Word1{29-22} = inst;
598 let Word1{30} = 0; // MARK
599 let Word1{31} = 1; // BARRIER
601 defm : ExportPattern<EG_ExportSwz, 83>;
603 def EG_ExportBuf : ExportBufInst {
604 let Word1{19-16} = 0; // BURST_COUNT
605 let Word1{20} = 0; // VALID_PIXEL_MODE
607 let Word1{29-22} = inst;
608 let Word1{30} = 0; // MARK
609 let Word1{31} = 1; // BARRIER
611 defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>;
613 def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT),
614 "TEX $COUNT @$ADDR"> {
617 def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT),
618 "VTX $COUNT @$ADDR"> {
621 def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR),
622 "LOOP_START_DX10 @$ADDR"> {
626 def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
630 def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR),
631 "LOOP_BREAK @$ADDR"> {
635 def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR),
640 def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
641 "JUMP @$ADDR POP:$POP_COUNT"> {
644 def CF_PUSH_EG : CF_CLAUSE_EG<11, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
645 "PUSH @$ADDR POP:$POP_COUNT"> {
648 def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
649 "ELSE @$ADDR POP:$POP_COUNT"> {
652 def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> {
657 def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
658 "POP @$ADDR POP:$POP_COUNT"> {
661 def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> {
665 let END_OF_PROGRAM = 1;
668 } // End Predicates = [isEGorCayman]