1 //===-- EvergreenInstructions.td - EG Instruction defs ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // TableGen definitions for instructions which are:
11 // - Available to Evergreen and newer VLIW4/VLIW5 GPUs
12 // - Available only on Evergreen family GPUs.
14 //===----------------------------------------------------------------------===//
17 "Subtarget.getGeneration() >= AMDGPUSubtarget::EVERGREEN && "
18 "Subtarget.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && "
19 "!Subtarget.hasCaymanISA()"
22 def isEGorCayman : Predicate<
23 "Subtarget.getGeneration() == AMDGPUSubtarget::EVERGREEN ||"
24 "Subtarget.getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS"
27 //===----------------------------------------------------------------------===//
28 // Evergreen / Cayman store instructions
29 //===----------------------------------------------------------------------===//
31 let Predicates = [isEGorCayman] in {
33 class CF_MEM_RAT_CACHELESS <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins,
34 string name, list<dag> pattern>
35 : EG_CF_RAT <0x57, rat_inst, rat_id, mask, (outs), ins,
36 "MEM_RAT_CACHELESS "#name, pattern>;
38 class CF_MEM_RAT <bits<6> rat_inst, bits<4> rat_id, dag ins, string name,
40 : EG_CF_RAT <0x56, rat_inst, rat_id, 0xf /* mask */, (outs), ins,
41 "MEM_RAT "#name, pattern>;
43 def RAT_MSKOR : CF_MEM_RAT <0x11, 0,
44 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr),
45 "MSKOR $rw_gpr.XW, $index_gpr",
46 [(mskor_global v4i32:$rw_gpr, i32:$index_gpr)]
51 } // End let Predicates = [isEGorCayman]
53 //===----------------------------------------------------------------------===//
54 // Evergreen Only instructions
55 //===----------------------------------------------------------------------===//
57 let Predicates = [isEG] in {
59 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
60 defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
62 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
63 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
64 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
65 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
66 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
67 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
68 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
69 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
70 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
71 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
72 def SIN_eg : SIN_Common<0x8D>;
73 def COS_eg : COS_Common<0x8E>;
75 def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>;
76 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>;
78 //===----------------------------------------------------------------------===//
79 // Memory read/write instructions
80 //===----------------------------------------------------------------------===//
82 let usesCustomInserter = 1 in {
85 def RAT_WRITE_CACHELESS_32_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x1,
86 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
87 "STORE_RAW $rw_gpr, $index_gpr, $eop",
88 [(global_store i32:$rw_gpr, i32:$index_gpr)]
92 def RAT_WRITE_CACHELESS_64_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x3,
93 (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
94 "STORE_RAW $rw_gpr.XY, $index_gpr, $eop",
95 [(global_store v2i32:$rw_gpr, i32:$index_gpr)]
99 def RAT_WRITE_CACHELESS_128_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0xf,
100 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
101 "STORE_RAW $rw_gpr.XYZW, $index_gpr, $eop",
102 [(global_store v4i32:$rw_gpr, i32:$index_gpr)]
105 } // End usesCustomInserter = 1
107 class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
108 : VTX_WORD0_eg, VTX_READ<name, buffer_id, outs, pattern> {
113 let FETCH_WHOLE_QUAD = 0;
114 let BUFFER_ID = buffer_id;
116 // XXX: We can infer this field based on the SRC_GPR. This would allow us
117 // to store vertex addresses in any channel, not just X.
120 let Inst{31-0} = Word0;
123 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
124 : VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id,
125 (outs R600_TReg32_X:$dst_gpr), pattern> {
127 let MEGA_FETCH_COUNT = 1;
129 let DST_SEL_Y = 7; // Masked
130 let DST_SEL_Z = 7; // Masked
131 let DST_SEL_W = 7; // Masked
132 let DATA_FORMAT = 1; // FMT_8
135 class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
136 : VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id,
137 (outs R600_TReg32_X:$dst_gpr), pattern> {
138 let MEGA_FETCH_COUNT = 2;
140 let DST_SEL_Y = 7; // Masked
141 let DST_SEL_Z = 7; // Masked
142 let DST_SEL_W = 7; // Masked
143 let DATA_FORMAT = 5; // FMT_16
147 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
148 : VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id,
149 (outs R600_TReg32_X:$dst_gpr), pattern> {
151 let MEGA_FETCH_COUNT = 4;
153 let DST_SEL_Y = 7; // Masked
154 let DST_SEL_Z = 7; // Masked
155 let DST_SEL_W = 7; // Masked
156 let DATA_FORMAT = 0xD; // COLOR_32
158 // This is not really necessary, but there were some GPU hangs that appeared
159 // to be caused by ALU instructions in the next instruction group that wrote
160 // to the $src_gpr registers of the VTX_READ.
162 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
163 // %T2_X<def> = MOV %ZERO
164 //Adding this constraint prevents this from happening.
165 let Constraints = "$src_gpr.ptr = $dst_gpr";
168 class VTX_READ_64_eg <bits<8> buffer_id, list<dag> pattern>
169 : VTX_READ_eg <"VTX_READ_64 $dst_gpr.XY, $src_gpr", buffer_id,
170 (outs R600_Reg64:$dst_gpr), pattern> {
172 let MEGA_FETCH_COUNT = 8;
177 let DATA_FORMAT = 0x1D; // COLOR_32_32
180 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
181 : VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id,
182 (outs R600_Reg128:$dst_gpr), pattern> {
184 let MEGA_FETCH_COUNT = 16;
189 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
191 // XXX: Need to force VTX_READ_128 instructions to write to the same register
192 // that holds its buffer address to avoid potential hangs. We can't use
193 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst
194 // registers are different sizes.
197 //===----------------------------------------------------------------------===//
198 // VTX Read from parameter memory space
199 //===----------------------------------------------------------------------===//
201 def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <0,
202 [(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))]
205 def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <0,
206 [(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))]
209 def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0,
210 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
213 def VTX_READ_PARAM_64_eg : VTX_READ_64_eg <0,
214 [(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
217 def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <0,
218 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
221 //===----------------------------------------------------------------------===//
222 // VTX Read from global memory space
223 //===----------------------------------------------------------------------===//
226 def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1,
227 [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))]
230 def VTX_READ_GLOBAL_16_eg : VTX_READ_16_eg <1,
231 [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))]
235 def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1,
236 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
240 def VTX_READ_GLOBAL_64_eg : VTX_READ_64_eg <1,
241 [(set v2i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
245 def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
246 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
249 } // End Predicates = [isEG]
251 //===----------------------------------------------------------------------===//
252 // Evergreen / Cayman Instructions
253 //===----------------------------------------------------------------------===//
255 let Predicates = [isEGorCayman] in {
257 // BFE_UINT - bit_extract, an optimization for mask and shift
262 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
267 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0
268 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
269 // (16, 8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
270 // (24, 8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
271 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
272 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))],
276 def BFE_INT_eg : R600_3OP <0x5, "BFE_INT",
277 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))],
281 // XXX: This pattern is broken, disabling for now. See comment in
282 // AMDGPUInstructions.td for more info.
283 // def : BFEPattern <BFE_UINT_eg>;
284 def BFI_INT_eg : R600_3OP <0x06, "BFI_INT",
285 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))],
289 def : Pat<(i32 (sext_inreg i32:$src, i1)),
290 (BFE_INT_eg i32:$src, (i32 ZERO), (i32 ONE_INT))>;
291 def : Pat<(i32 (sext_inreg i32:$src, i8)),
292 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 8))>;
293 def : Pat<(i32 (sext_inreg i32:$src, i16)),
294 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 16))>;
296 defm : BFIPatterns <BFI_INT_eg>;
298 def BFM_INT_eg : R600_2OP <0xA0, "BFM_INT",
299 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))],
303 def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24",
304 [(set i32:$dst, (add (AMDGPUmul_u24 i32:$src0, i32:$src1), i32:$src2))], VecALU
306 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>;
307 def : ROTRPattern <BIT_ALIGN_INT_eg>;
308 def MULADD_eg : MULADD_Common<0x14>;
309 def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>;
310 def ASHR_eg : ASHR_Common<0x15>;
311 def LSHR_eg : LSHR_Common<0x16>;
312 def LSHL_eg : LSHL_Common<0x17>;
313 def CNDE_eg : CNDE_Common<0x19>;
314 def CNDGT_eg : CNDGT_Common<0x1A>;
315 def CNDGE_eg : CNDGE_Common<0x1B>;
316 def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
317 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
318 def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24",
319 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))], VecALU
321 def DOT4_eg : DOT4_Common<0xBE>;
322 defm CUBE_eg : CUBE_Common<0xC0>;
324 let hasSideEffects = 1 in {
325 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", [], VecALU>;
328 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
330 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
332 let Itinerary = AnyALU;
335 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
337 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
341 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
343 def GROUP_BARRIER : InstR600 <
344 (outs), (ins), " GROUP_BARRIER", [(int_AMDGPU_barrier_local)], AnyALU>,
346 R600ALU_Word1_OP2 <0x54> {
362 let bank_swizzle = 0;
364 let update_exec_mask = 0;
367 let Inst{31-0} = Word0;
368 let Inst{63-32} = Word1;
373 //===----------------------------------------------------------------------===//
375 //===----------------------------------------------------------------------===//
376 class R600_LDS <bits<6> op, dag outs, dag ins, string asm,
377 list<dag> pattern = []> :
379 InstR600 <outs, ins, asm, pattern, XALU>,
386 let Word1{27} = offset{0};
387 let Word1{12} = offset{1};
388 let Word1{28} = offset{2};
389 let Word1{31} = offset{3};
390 let Word0{12} = offset{4};
391 let Word0{25} = offset{5};
394 let Inst{31-0} = Word0;
395 let Inst{63-32} = Word1;
398 let HasNativeOperands = 1;
399 let UseNamedOperandTable = 1;
402 class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS <
404 (outs R600_Reg32:$dst),
405 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
406 LAST:$last, R600_Pred:$pred_sel,
407 BANK_SWIZZLE:$bank_swizzle),
408 " "#name#" $last OQAP, $src0$src0_rel $pred_sel",
417 let usesCustomInserter = 1;
419 let DisableEncoding = "$dst";
422 class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern,
426 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
427 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
428 LAST:$last, R600_Pred:$pred_sel,
429 BANK_SWIZZLE:$bank_swizzle),
430 " "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel",
441 class R600_LDS_1A1D_NORET <bits<6> lds_op, string name, list<dag> pattern> :
442 R600_LDS_1A1D <lds_op, (outs), name, pattern> {
446 class R600_LDS_1A1D_RET <bits<6> lds_op, string name, list<dag> pattern> :
447 R600_LDS_1A1D <lds_op, (outs R600_Reg32:$dst), name##"_RET", pattern, "OQAP, "> {
450 let usesCustomInserter = 1;
451 let DisableEncoding = "$dst";
454 class R600_LDS_1A2D <bits<6> lds_op, string name, list<dag> pattern> :
458 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
459 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
460 R600_Reg32:$src2, REL:$src2_rel, SEL:$src2_sel,
461 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle),
462 " "#name# "$last $src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel",
467 def LDS_ADD : R600_LDS_1A1D_NORET <0x0, "LDS_ADD", [] >;
468 def LDS_SUB : R600_LDS_1A1D_NORET <0x1, "LDS_SUB", [] >;
469 def LDS_WRITE : R600_LDS_1A1D_NORET <0xD, "LDS_WRITE",
470 [(local_store (i32 R600_Reg32:$src1), R600_Reg32:$src0)]
472 def LDS_BYTE_WRITE : R600_LDS_1A1D_NORET<0x12, "LDS_BYTE_WRITE",
473 [(truncstorei8_local i32:$src1, i32:$src0)]
475 def LDS_SHORT_WRITE : R600_LDS_1A1D_NORET<0x13, "LDS_SHORT_WRITE",
476 [(truncstorei16_local i32:$src1, i32:$src0)]
478 def LDS_ADD_RET : R600_LDS_1A1D_RET <0x20, "LDS_ADD",
479 [(set i32:$dst, (atomic_load_add_local i32:$src0, i32:$src1))]
481 def LDS_SUB_RET : R600_LDS_1A1D_RET <0x21, "LDS_SUB",
482 [(set i32:$dst, (atomic_load_sub_local i32:$src0, i32:$src1))]
484 def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET",
485 [(set (i32 R600_Reg32:$dst), (local_load R600_Reg32:$src0))]
487 def LDS_BYTE_READ_RET : R600_LDS_1A <0x36, "LDS_BYTE_READ_RET",
488 [(set i32:$dst, (sextloadi8_local i32:$src0))]
490 def LDS_UBYTE_READ_RET : R600_LDS_1A <0x37, "LDS_UBYTE_READ_RET",
491 [(set i32:$dst, (az_extloadi8_local i32:$src0))]
493 def LDS_SHORT_READ_RET : R600_LDS_1A <0x38, "LDS_SHORT_READ_RET",
494 [(set i32:$dst, (sextloadi16_local i32:$src0))]
496 def LDS_USHORT_READ_RET : R600_LDS_1A <0x39, "LDS_USHORT_READ_RET",
497 [(set i32:$dst, (az_extloadi16_local i32:$src0))]
500 // TRUNC is used for the FLT_TO_INT instructions to work around a
501 // perceived problem where the rounding modes are applied differently
502 // depending on the instruction and the slot they are in.
504 // https://bugs.freedesktop.org/show_bug.cgi?id=50232
505 // Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c
507 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
508 // which do not need to be truncated since the fp values are 0.0f or 1.0f.
509 // We should look into handling these cases separately.
510 def : Pat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>;
512 def : Pat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>;
515 def : SHA256MaPattern <BFI_INT_eg, XOR_INT>;
517 def : FROUNDPat <CNDGE_eg>;
519 def EG_ExportSwz : ExportSwzInst {
520 let Word1{19-16} = 0; // BURST_COUNT
521 let Word1{20} = 0; // VALID_PIXEL_MODE
523 let Word1{29-22} = inst;
524 let Word1{30} = 0; // MARK
525 let Word1{31} = 1; // BARRIER
527 defm : ExportPattern<EG_ExportSwz, 83>;
529 def EG_ExportBuf : ExportBufInst {
530 let Word1{19-16} = 0; // BURST_COUNT
531 let Word1{20} = 0; // VALID_PIXEL_MODE
533 let Word1{29-22} = inst;
534 let Word1{30} = 0; // MARK
535 let Word1{31} = 1; // BARRIER
537 defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>;
539 def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT),
540 "TEX $COUNT @$ADDR"> {
543 def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT),
544 "VTX $COUNT @$ADDR"> {
547 def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR),
548 "LOOP_START_DX10 @$ADDR"> {
552 def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
556 def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR),
557 "LOOP_BREAK @$ADDR"> {
561 def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR),
566 def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
567 "JUMP @$ADDR POP:$POP_COUNT"> {
570 def CF_PUSH_EG : CF_CLAUSE_EG<11, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
571 "PUSH @$ADDR POP:$POP_COUNT"> {
574 def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
575 "ELSE @$ADDR POP:$POP_COUNT"> {
578 def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> {
583 def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
584 "POP @$ADDR POP:$POP_COUNT"> {
587 def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> {
591 let END_OF_PROGRAM = 1;
594 } // End Predicates = [isEGorCayman]