1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "AMDGPUInstPrinter.h"
12 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCRegisterInfo.h"
16 #include "llvm/Support/MathExtras.h"
20 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
23 printInstruction(MI, OS);
25 printAnnotation(OS, Annot);
28 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
30 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
33 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
35 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff);
38 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
40 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
43 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
45 if (MI->getOperand(OpNo).getImm())
49 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
51 if (MI->getOperand(OpNo).getImm())
55 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
57 if (MI->getOperand(OpNo).getImm())
61 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
63 if (MI->getOperand(OpNo).getImm()) {
65 printU16ImmOperand(MI, OpNo, O);
69 void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo,
71 if (MI->getOperand(OpNo).getImm())
75 void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo,
77 if (MI->getOperand(OpNo).getImm())
81 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
83 if (MI->getOperand(OpNo).getImm())
87 void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O) {
108 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) {
111 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) {
114 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) {
117 } else if (MRI.getRegClass(AMDGPU::SReg_64RegClassID).contains(reg)) {
120 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) {
123 } else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) {
126 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) {
129 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) {
132 } else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) {
135 } else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(reg)) {
138 } else if (MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(reg)) {
142 O << getRegisterName(reg);
146 // The low 8 bits of the encoding value is the register index, for both VGPRs
148 unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1);
154 O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
157 void AMDGPUInstPrinter::printImmediate(uint32_t Imm, raw_ostream &O) {
158 int32_t SImm = static_cast<int32_t>(Imm);
159 if (SImm >= -16 && SImm <= 64) {
164 if (Imm == FloatToBits(1.0f) ||
165 Imm == FloatToBits(-1.0f) ||
166 Imm == FloatToBits(0.5f) ||
167 Imm == FloatToBits(-0.5f) ||
168 Imm == FloatToBits(2.0f) ||
169 Imm == FloatToBits(-2.0f) ||
170 Imm == FloatToBits(4.0f) ||
171 Imm == FloatToBits(-4.0f)) {
172 O << BitsToFloat(Imm);
176 O << formatHex(static_cast<uint64_t>(Imm));
179 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
182 const MCOperand &Op = MI->getOperand(OpNo);
184 switch (Op.getReg()) {
185 // This is the default predicate state, so we don't need to print it.
186 case AMDGPU::PRED_SEL_OFF:
190 printRegOperand(Op.getReg(), O);
193 } else if (Op.isImm()) {
194 printImmediate(Op.getImm(), O);
195 } else if (Op.isFPImm()) {
197 } else if (Op.isExpr()) {
198 const MCExpr *Exp = Op.getExpr();
201 assert(!"unknown operand type in printOperand");
205 void AMDGPUInstPrinter::printOperandAndMods(const MCInst *MI, unsigned OpNo,
207 unsigned InputModifiers = MI->getOperand(OpNo).getImm();
208 if (InputModifiers & 0x1)
210 if (InputModifiers & 0x2)
212 printOperand(MI, OpNo + 1, O);
213 if (InputModifiers & 0x2)
217 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
219 unsigned Imm = MI->getOperand(OpNum).getImm();
223 } else if (Imm == 1) {
225 } else if (Imm == 0) {
228 assert(!"Invalid interpolation parameter slot");
232 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
234 printOperand(MI, OpNo, O);
236 printOperand(MI, OpNo + 1, O);
239 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
240 raw_ostream &O, StringRef Asm,
242 const MCOperand &Op = MI->getOperand(OpNo);
244 if (Op.getImm() == 1) {
251 void AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
253 printIfSet(MI, OpNo, O, "|");
256 void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
258 printIfSet(MI, OpNo, O, "_SAT");
261 void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
263 int32_t Imm = MI->getOperand(OpNo).getImm();
264 O << Imm << '(' << BitsToFloat(Imm) << ')';
267 void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo,
269 printIfSet(MI, OpNo, O.indent(25 - O.GetNumBytesInBuffer()), "*", " ");
272 void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
274 printIfSet(MI, OpNo, O, "-");
277 void AMDGPUInstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
279 switch (MI->getOperand(OpNo).getImm()) {
293 void AMDGPUInstPrinter::printRel(const MCInst *MI, unsigned OpNo,
295 printIfSet(MI, OpNo, O, "+");
298 void AMDGPUInstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
300 printIfSet(MI, OpNo, O, "ExecMask,");
303 void AMDGPUInstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
305 printIfSet(MI, OpNo, O, "Pred,");
308 void AMDGPUInstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
310 const MCOperand &Op = MI->getOperand(OpNo);
311 if (Op.getImm() == 0) {
316 void AMDGPUInstPrinter::printSel(const MCInst *MI, unsigned OpNo,
318 const char * chans = "XYZW";
319 int sel = MI->getOperand(OpNo).getImm();
328 O << cb << "[" << sel << "]";
329 } else if (sel >= 448) {
332 } else if (sel >= 0){
337 O << "." << chans[chan];
340 void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
342 int BankSwizzle = MI->getOperand(OpNo).getImm();
343 switch (BankSwizzle) {
345 O << "BS:VEC_021/SCL_122";
348 O << "BS:VEC_120/SCL_212";
351 O << "BS:VEC_102/SCL_221";
365 void AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
367 unsigned Sel = MI->getOperand(OpNo).getImm();
395 void AMDGPUInstPrinter::printCT(const MCInst *MI, unsigned OpNo,
397 unsigned CT = MI->getOperand(OpNo).getImm();
410 void AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
412 int KCacheMode = MI->getOperand(OpNo).getImm();
413 if (KCacheMode > 0) {
414 int KCacheBank = MI->getOperand(OpNo - 2).getImm();
415 O << "CB" << KCacheBank <<":";
416 int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
417 int LineSize = (KCacheMode == 1)?16:32;
418 O << KCacheAddr * 16 << "-" << KCacheAddr * 16 + LineSize;
422 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
424 unsigned SImm16 = MI->getOperand(OpNo).getImm();
425 unsigned Msg = SImm16 & 0xF;
426 if (Msg == 2 || Msg == 3) {
427 unsigned Op = (SImm16 >> 4) & 0xF;
435 unsigned Stream = (SImm16 >> 8) & 0x3;
442 O << " stream " << Stream;
450 O << "unknown(" << Msg << ") ";
453 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
455 // Note: Mask values are taken from SIInsertWaits.cpp and not from ISA docs
456 // SIInsertWaits.cpp bits usage does not match ISA docs description but it
457 // works so it might be a misprint in docs.
458 unsigned SImm16 = MI->getOperand(OpNo).getImm();
459 unsigned Vmcnt = SImm16 & 0xF;
460 unsigned Expcnt = (SImm16 >> 4) & 0xF;
461 unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
463 O << "vmcnt(" << Vmcnt << ") ";
465 O << "expcnt(" << Expcnt << ") ";
467 O << "lgkmcnt(" << Lgkmcnt << ")";
470 #include "AMDGPUGenAsmWriter.inc"