1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "AMDGPUInstPrinter.h"
12 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInst.h"
18 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
21 printInstruction(MI, OS);
23 printAnnotation(OS, Annot);
26 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
29 const MCOperand &Op = MI->getOperand(OpNo);
31 switch (Op.getReg()) {
32 // This is the default predicate state, so we don't need to print it.
33 case AMDGPU::PRED_SEL_OFF: break;
34 default: O << getRegisterName(Op.getReg()); break;
36 } else if (Op.isImm()) {
38 } else if (Op.isFPImm()) {
40 } else if (Op.isExpr()) {
41 const MCExpr *Exp = Op.getExpr();
44 assert(!"unknown operand type in printOperand");
48 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
50 unsigned Imm = MI->getOperand(OpNum).getImm();
54 } else if (Imm == 1) {
56 } else if (Imm == 0) {
59 assert(!"Invalid interpolation parameter slot");
63 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
65 printOperand(MI, OpNo, O);
67 printOperand(MI, OpNo + 1, O);
70 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
71 raw_ostream &O, StringRef Asm,
73 const MCOperand &Op = MI->getOperand(OpNo);
75 if (Op.getImm() == 1) {
82 void AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
84 printIfSet(MI, OpNo, O, "|");
87 void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
89 printIfSet(MI, OpNo, O, "_SAT");
92 void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
99 L.i = MI->getOperand(OpNo).getImm();
100 O << L.i << "(" << L.f << ")";
103 void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo,
105 printIfSet(MI, OpNo, O.indent(25 - O.GetNumBytesInBuffer()), "*", " ");
108 void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
110 printIfSet(MI, OpNo, O, "-");
113 void AMDGPUInstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
115 switch (MI->getOperand(OpNo).getImm()) {
129 void AMDGPUInstPrinter::printRel(const MCInst *MI, unsigned OpNo,
131 printIfSet(MI, OpNo, O, "+");
134 void AMDGPUInstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
136 printIfSet(MI, OpNo, O, "ExecMask,");
139 void AMDGPUInstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
141 printIfSet(MI, OpNo, O, "Pred,");
144 void AMDGPUInstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
146 const MCOperand &Op = MI->getOperand(OpNo);
147 if (Op.getImm() == 0) {
152 void AMDGPUInstPrinter::printSel(const MCInst *MI, unsigned OpNo,
154 const char * chans = "XYZW";
155 int sel = MI->getOperand(OpNo).getImm();
164 O << cb << "[" << sel << "]";
165 } else if (sel >= 448) {
168 } else if (sel >= 0){
173 O << "." << chans[chan];
176 void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
178 int BankSwizzle = MI->getOperand(OpNo).getImm();
179 switch (BankSwizzle) {
181 O << "BS:VEC_021/SCL_122";
184 O << "BS:VEC_120/SCL_212";
187 O << "BS:VEC_102/SCL_221";
201 void AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
203 unsigned Sel = MI->getOperand(OpNo).getImm();
231 void AMDGPUInstPrinter::printCT(const MCInst *MI, unsigned OpNo,
233 unsigned CT = MI->getOperand(OpNo).getImm();
246 void AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
248 int KCacheMode = MI->getOperand(OpNo).getImm();
249 if (KCacheMode > 0) {
250 int KCacheBank = MI->getOperand(OpNo - 2).getImm();
251 O << "CB" << KCacheBank <<":";
252 int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
253 int LineSize = (KCacheMode == 1)?16:32;
254 O << KCacheAddr * 16 << "-" << KCacheAddr * 16 + LineSize;
258 #include "AMDGPUGenAsmWriter.inc"