1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "AMDGPUInstPrinter.h"
12 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInst.h"
18 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
21 printInstruction(MI, OS);
23 printAnnotation(OS, Annot);
26 void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O) {
44 // It's seems there's no way to use SIRegisterInfo here, and dealing with the
45 // giant enum of all the different shifted sets of registers is pretty
46 // unmanagable, so parse the name and reformat it to be prettier.
47 StringRef Name(getRegisterName(reg));
49 std::pair<StringRef, StringRef> Split = Name.split('_');
50 StringRef SubRegName = Split.first;
51 StringRef Rest = Split.second;
53 if (SubRegName.size() <= 4) { // Must at least be as long as "SGPR"/"VGPR".
59 StringRef RegIndexStr = SubRegName.drop_front(4);
61 if (RegIndexStr.getAsInteger(10, RegIndex)) {
66 if (SubRegName.front() == 'V')
68 else if (SubRegName.front() == 'S')
75 if (Rest.empty()) // Only 1 32-bit register
78 unsigned NumReg = Rest.count('_') + 2;
79 O << '[' << RegIndex << ':' << (RegIndex + NumReg - 1) << ']';
83 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
86 const MCOperand &Op = MI->getOperand(OpNo);
88 switch (Op.getReg()) {
89 // This is the default predicate state, so we don't need to print it.
90 case AMDGPU::PRED_SEL_OFF:
94 printRegOperand(Op.getReg(), O);
97 } else if (Op.isImm()) {
99 } else if (Op.isFPImm()) {
101 } else if (Op.isExpr()) {
102 const MCExpr *Exp = Op.getExpr();
105 assert(!"unknown operand type in printOperand");
109 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
111 unsigned Imm = MI->getOperand(OpNum).getImm();
115 } else if (Imm == 1) {
117 } else if (Imm == 0) {
120 assert(!"Invalid interpolation parameter slot");
124 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
126 printOperand(MI, OpNo, O);
128 printOperand(MI, OpNo + 1, O);
131 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
132 raw_ostream &O, StringRef Asm,
134 const MCOperand &Op = MI->getOperand(OpNo);
136 if (Op.getImm() == 1) {
143 void AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
145 printIfSet(MI, OpNo, O, "|");
148 void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
150 printIfSet(MI, OpNo, O, "_SAT");
153 void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
160 L.i = MI->getOperand(OpNo).getImm();
161 O << L.i << "(" << L.f << ")";
164 void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo,
166 printIfSet(MI, OpNo, O.indent(25 - O.GetNumBytesInBuffer()), "*", " ");
169 void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
171 printIfSet(MI, OpNo, O, "-");
174 void AMDGPUInstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
176 switch (MI->getOperand(OpNo).getImm()) {
190 void AMDGPUInstPrinter::printRel(const MCInst *MI, unsigned OpNo,
192 printIfSet(MI, OpNo, O, "+");
195 void AMDGPUInstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
197 printIfSet(MI, OpNo, O, "ExecMask,");
200 void AMDGPUInstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
202 printIfSet(MI, OpNo, O, "Pred,");
205 void AMDGPUInstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
207 const MCOperand &Op = MI->getOperand(OpNo);
208 if (Op.getImm() == 0) {
213 void AMDGPUInstPrinter::printSel(const MCInst *MI, unsigned OpNo,
215 const char * chans = "XYZW";
216 int sel = MI->getOperand(OpNo).getImm();
225 O << cb << "[" << sel << "]";
226 } else if (sel >= 448) {
229 } else if (sel >= 0){
234 O << "." << chans[chan];
237 void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
239 int BankSwizzle = MI->getOperand(OpNo).getImm();
240 switch (BankSwizzle) {
242 O << "BS:VEC_021/SCL_122";
245 O << "BS:VEC_120/SCL_212";
248 O << "BS:VEC_102/SCL_221";
262 void AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
264 unsigned Sel = MI->getOperand(OpNo).getImm();
292 void AMDGPUInstPrinter::printCT(const MCInst *MI, unsigned OpNo,
294 unsigned CT = MI->getOperand(OpNo).getImm();
307 void AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
309 int KCacheMode = MI->getOperand(OpNo).getImm();
310 if (KCacheMode > 0) {
311 int KCacheBank = MI->getOperand(OpNo - 2).getImm();
312 O << "CB" << KCacheBank <<":";
313 int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
314 int LineSize = (KCacheMode == 1)?16:32;
315 O << KCacheAddr * 16 << "-" << KCacheAddr * 16 + LineSize;
319 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
321 unsigned SImm16 = MI->getOperand(OpNo).getImm();
322 unsigned Msg = SImm16 & 0xF;
323 if (Msg == 2 || Msg == 3) {
324 unsigned Op = (SImm16 >> 4) & 0xF;
332 unsigned Stream = (SImm16 >> 8) & 0x3;
339 O << " stream " << Stream;
347 O << "unknown(" << Msg << ") ";
350 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
352 // Note: Mask values are taken from SIInsertWaits.cpp and not from ISA docs
353 // SIInsertWaits.cpp bits usage does not match ISA docs description but it
354 // works so it might be a misprint in docs.
355 unsigned SImm16 = MI->getOperand(OpNo).getImm();
356 unsigned Vmcnt = SImm16 & 0xF;
357 unsigned Expcnt = (SImm16 >> 4) & 0xF;
358 unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
360 O << "vmcnt(" << Vmcnt << ") ";
362 O << "expcnt(" << Expcnt << ") ";
364 O << "lgkmcnt(" << Lgkmcnt << ")";
367 #include "AMDGPUGenAsmWriter.inc"