1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "AMDGPUInstPrinter.h"
12 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCRegisterInfo.h"
16 #include "llvm/Support/MathExtras.h"
20 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
23 printInstruction(MI, OS);
25 printAnnotation(OS, Annot);
28 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
30 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
33 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
35 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff);
38 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
40 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
43 void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O) {
64 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) {
67 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) {
70 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) {
73 } else if (MRI.getRegClass(AMDGPU::SReg_64RegClassID).contains(reg)) {
76 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) {
79 } else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) {
82 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) {
85 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) {
88 } else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) {
91 } else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(reg)) {
94 } else if (MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(reg)) {
98 O << getRegisterName(reg);
102 // The low 8 bits encoding value is the register index, for both VGPRs and
104 unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1);
110 O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
113 void AMDGPUInstPrinter::printImmediate(uint32_t Imm, raw_ostream &O) {
114 int32_t SImm = static_cast<int32_t>(Imm);
115 if (SImm >= -16 && SImm <= 64) {
120 if (Imm == FloatToBits(1.0f) ||
121 Imm == FloatToBits(-1.0f) ||
122 Imm == FloatToBits(0.5f) ||
123 Imm == FloatToBits(-0.5f) ||
124 Imm == FloatToBits(2.0f) ||
125 Imm == FloatToBits(-2.0f) ||
126 Imm == FloatToBits(4.0f) ||
127 Imm == FloatToBits(-4.0f)) {
128 O << BitsToFloat(Imm);
132 O << formatHex(static_cast<uint64_t>(Imm));
135 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
138 const MCOperand &Op = MI->getOperand(OpNo);
140 switch (Op.getReg()) {
141 // This is the default predicate state, so we don't need to print it.
142 case AMDGPU::PRED_SEL_OFF:
146 printRegOperand(Op.getReg(), O);
149 } else if (Op.isImm()) {
150 printImmediate(Op.getImm(), O);
151 } else if (Op.isFPImm()) {
153 } else if (Op.isExpr()) {
154 const MCExpr *Exp = Op.getExpr();
157 assert(!"unknown operand type in printOperand");
161 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
163 unsigned Imm = MI->getOperand(OpNum).getImm();
167 } else if (Imm == 1) {
169 } else if (Imm == 0) {
172 assert(!"Invalid interpolation parameter slot");
176 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
178 printOperand(MI, OpNo, O);
180 printOperand(MI, OpNo + 1, O);
183 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
184 raw_ostream &O, StringRef Asm,
186 const MCOperand &Op = MI->getOperand(OpNo);
188 if (Op.getImm() == 1) {
195 void AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
197 printIfSet(MI, OpNo, O, "|");
200 void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
202 printIfSet(MI, OpNo, O, "_SAT");
205 void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
212 L.i = MI->getOperand(OpNo).getImm();
213 O << L.i << "(" << L.f << ")";
216 void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo,
218 printIfSet(MI, OpNo, O.indent(25 - O.GetNumBytesInBuffer()), "*", " ");
221 void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
223 printIfSet(MI, OpNo, O, "-");
226 void AMDGPUInstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
228 switch (MI->getOperand(OpNo).getImm()) {
242 void AMDGPUInstPrinter::printRel(const MCInst *MI, unsigned OpNo,
244 printIfSet(MI, OpNo, O, "+");
247 void AMDGPUInstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
249 printIfSet(MI, OpNo, O, "ExecMask,");
252 void AMDGPUInstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
254 printIfSet(MI, OpNo, O, "Pred,");
257 void AMDGPUInstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
259 const MCOperand &Op = MI->getOperand(OpNo);
260 if (Op.getImm() == 0) {
265 void AMDGPUInstPrinter::printSel(const MCInst *MI, unsigned OpNo,
267 const char * chans = "XYZW";
268 int sel = MI->getOperand(OpNo).getImm();
277 O << cb << "[" << sel << "]";
278 } else if (sel >= 448) {
281 } else if (sel >= 0){
286 O << "." << chans[chan];
289 void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
291 int BankSwizzle = MI->getOperand(OpNo).getImm();
292 switch (BankSwizzle) {
294 O << "BS:VEC_021/SCL_122";
297 O << "BS:VEC_120/SCL_212";
300 O << "BS:VEC_102/SCL_221";
314 void AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
316 unsigned Sel = MI->getOperand(OpNo).getImm();
344 void AMDGPUInstPrinter::printCT(const MCInst *MI, unsigned OpNo,
346 unsigned CT = MI->getOperand(OpNo).getImm();
359 void AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
361 int KCacheMode = MI->getOperand(OpNo).getImm();
362 if (KCacheMode > 0) {
363 int KCacheBank = MI->getOperand(OpNo - 2).getImm();
364 O << "CB" << KCacheBank <<":";
365 int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
366 int LineSize = (KCacheMode == 1)?16:32;
367 O << KCacheAddr * 16 << "-" << KCacheAddr * 16 + LineSize;
371 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
373 unsigned SImm16 = MI->getOperand(OpNo).getImm();
374 unsigned Msg = SImm16 & 0xF;
375 if (Msg == 2 || Msg == 3) {
376 unsigned Op = (SImm16 >> 4) & 0xF;
384 unsigned Stream = (SImm16 >> 8) & 0x3;
391 O << " stream " << Stream;
399 O << "unknown(" << Msg << ") ";
402 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
404 // Note: Mask values are taken from SIInsertWaits.cpp and not from ISA docs
405 // SIInsertWaits.cpp bits usage does not match ISA docs description but it
406 // works so it might be a misprint in docs.
407 unsigned SImm16 = MI->getOperand(OpNo).getImm();
408 unsigned Vmcnt = SImm16 & 0xF;
409 unsigned Expcnt = (SImm16 >> 4) & 0xF;
410 unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
412 O << "vmcnt(" << Vmcnt << ") ";
414 O << "expcnt(" << Expcnt << ") ";
416 O << "lgkmcnt(" << Lgkmcnt << ")";
419 #include "AMDGPUGenAsmWriter.inc"