1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file provides AMDGPU specific target descriptions.
13 //===----------------------------------------------------------------------===//
15 #include "AMDGPUMCTargetDesc.h"
16 #include "AMDGPUMCAsmInfo.h"
17 #include "InstPrinter/AMDGPUInstPrinter.h"
18 #include "llvm/MC/MCCodeGenInfo.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCRegisterInfo.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MachineLocation.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/TargetRegistry.h"
27 #define GET_INSTRINFO_MC_DESC
28 #include "AMDGPUGenInstrInfo.inc"
30 #define GET_SUBTARGETINFO_MC_DESC
31 #include "AMDGPUGenSubtargetInfo.inc"
33 #define GET_REGINFO_MC_DESC
34 #include "AMDGPUGenRegisterInfo.inc"
38 static MCInstrInfo *createAMDGPUMCInstrInfo() {
39 MCInstrInfo *X = new MCInstrInfo();
40 InitAMDGPUMCInstrInfo(X);
44 static MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) {
45 MCRegisterInfo *X = new MCRegisterInfo();
46 InitAMDGPUMCRegisterInfo(X, 0);
50 static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU,
52 MCSubtargetInfo * X = new MCSubtargetInfo();
53 InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
57 static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM,
59 CodeGenOpt::Level OL) {
60 MCCodeGenInfo *X = new MCCodeGenInfo();
61 X->InitMCCodeGenInfo(RM, CM, OL);
65 static MCInstPrinter *createAMDGPUMCInstPrinter(const Target &T,
66 unsigned SyntaxVariant,
68 const MCInstrInfo &MII,
69 const MCRegisterInfo &MRI,
70 const MCSubtargetInfo &STI) {
71 return new AMDGPUInstPrinter(MAI, MII, MRI);
74 static MCCodeEmitter *createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII,
75 const MCRegisterInfo &MRI,
76 const MCSubtargetInfo &STI,
78 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
79 return createSIMCCodeEmitter(MCII, MRI, STI, Ctx);
81 return createR600MCCodeEmitter(MCII, MRI, STI, Ctx);
85 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
86 MCContext &Ctx, MCAsmBackend &MAB,
88 MCCodeEmitter *_Emitter,
91 return createELFStreamer(Ctx, MAB, _OS, _Emitter, false, false);
94 extern "C" void LLVMInitializeR600TargetMC() {
96 RegisterMCAsmInfo<AMDGPUMCAsmInfo> Y(TheAMDGPUTarget);
98 TargetRegistry::RegisterMCCodeGenInfo(TheAMDGPUTarget, createAMDGPUMCCodeGenInfo);
100 TargetRegistry::RegisterMCInstrInfo(TheAMDGPUTarget, createAMDGPUMCInstrInfo);
102 TargetRegistry::RegisterMCRegInfo(TheAMDGPUTarget, createAMDGPUMCRegisterInfo);
104 TargetRegistry::RegisterMCSubtargetInfo(TheAMDGPUTarget, createAMDGPUMCSubtargetInfo);
106 TargetRegistry::RegisterMCInstPrinter(TheAMDGPUTarget, createAMDGPUMCInstPrinter);
108 TargetRegistry::RegisterMCCodeEmitter(TheAMDGPUTarget, createAMDGPUMCCodeEmitter);
110 TargetRegistry::RegisterMCAsmBackend(TheAMDGPUTarget, createAMDGPUAsmBackend);
112 TargetRegistry::RegisterMCObjectStreamer(TheAMDGPUTarget, createMCStreamer);