1 //===-- SIMCCodeEmitter.cpp - SI Code Emitter -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief The SI code emitter produces machine code that can be executed
12 /// directly on the GPU device.
14 //===----------------------------------------------------------------------===//
17 #include "MCTargetDesc/AMDGPUFixupKinds.h"
18 #include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
19 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
20 #include "SIDefines.h"
21 #include "llvm/MC/MCCodeEmitter.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCFixup.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/Support/raw_ostream.h"
34 class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
35 SIMCCodeEmitter(const SIMCCodeEmitter &) LLVM_DELETED_FUNCTION;
36 void operator=(const SIMCCodeEmitter &) LLVM_DELETED_FUNCTION;
37 const MCInstrInfo &MCII;
38 const MCRegisterInfo &MRI;
41 /// \brief Can this operand also contain immediate values?
42 bool isSrcOperand(const MCInstrDesc &Desc, unsigned OpNo) const;
44 /// \brief Encode an fp or int literal
45 uint32_t getLitEncoding(const MCOperand &MO, unsigned OpSize) const;
48 SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
50 : MCII(mcii), MRI(mri), Ctx(ctx) { }
52 ~SIMCCodeEmitter() { }
54 /// \brief Encode the instruction and write it to the OS.
55 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
56 SmallVectorImpl<MCFixup> &Fixups,
57 const MCSubtargetInfo &STI) const override;
59 /// \returns the encoding for an MCOperand.
60 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
61 SmallVectorImpl<MCFixup> &Fixups,
62 const MCSubtargetInfo &STI) const override;
64 /// \brief Use a fixup to encode the simm16 field for SOPP branch
66 unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
67 SmallVectorImpl<MCFixup> &Fixups,
68 const MCSubtargetInfo &STI) const override;
71 } // End anonymous namespace
73 MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII,
74 const MCRegisterInfo &MRI,
75 const MCSubtargetInfo &STI,
77 return new SIMCCodeEmitter(MCII, MRI, Ctx);
80 bool SIMCCodeEmitter::isSrcOperand(const MCInstrDesc &Desc,
81 unsigned OpNo) const {
82 unsigned OpType = Desc.OpInfo[OpNo].OperandType;
84 return OpType == AMDGPU::OPERAND_REG_IMM32 ||
85 OpType == AMDGPU::OPERAND_REG_INLINE_C;
88 // Returns the encoding value to use if the given integer is an integer inline
89 // immediate value, or 0 if it is not.
90 template <typename IntTy>
91 static uint32_t getIntInlineImmEncoding(IntTy Imm) {
92 if (Imm >= 0 && Imm <= 64)
95 if (Imm >= -16 && Imm <= -1)
96 return 192 + std::abs(Imm);
101 static uint32_t getLit32Encoding(uint32_t Val) {
102 uint32_t IntImm = getIntInlineImmEncoding(static_cast<int32_t>(Val));
106 if (Val == FloatToBits(0.5f))
109 if (Val == FloatToBits(-0.5f))
112 if (Val == FloatToBits(1.0f))
115 if (Val == FloatToBits(-1.0f))
118 if (Val == FloatToBits(2.0f))
121 if (Val == FloatToBits(-2.0f))
124 if (Val == FloatToBits(4.0f))
127 if (Val == FloatToBits(-4.0f))
133 static uint32_t getLit64Encoding(uint64_t Val) {
134 uint32_t IntImm = getIntInlineImmEncoding(static_cast<int64_t>(Val));
138 if (Val == DoubleToBits(0.5))
141 if (Val == DoubleToBits(-0.5))
144 if (Val == DoubleToBits(1.0))
147 if (Val == DoubleToBits(-1.0))
150 if (Val == DoubleToBits(2.0))
153 if (Val == DoubleToBits(-2.0))
156 if (Val == DoubleToBits(4.0))
159 if (Val == DoubleToBits(-4.0))
165 uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
166 unsigned OpSize) const {
170 assert(!MO.isFPImm());
176 return getLit32Encoding(static_cast<uint32_t>(MO.getImm()));
180 return getLit64Encoding(static_cast<uint64_t>(MO.getImm()));
183 void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
184 SmallVectorImpl<MCFixup> &Fixups,
185 const MCSubtargetInfo &STI) const {
187 uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
188 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
189 unsigned bytes = Desc.getSize();
191 for (unsigned i = 0; i < bytes; i++) {
192 OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
198 // Check for additional literals in SRC0/1/2 (Op 1/2/3)
199 for (unsigned i = 0, e = MI.getNumOperands(); i < e; ++i) {
201 // Check if this operand should be encoded as [SV]Src
202 if (!isSrcOperand(Desc, i))
205 int RCID = Desc.OpInfo[i].RegClass;
206 const MCRegisterClass &RC = MRI.getRegClass(RCID);
208 // Is this operand a literal immediate?
209 const MCOperand &Op = MI.getOperand(i);
210 if (getLitEncoding(Op, RC.getSize()) != 255)
218 else if (!Op.isExpr()) // Exprs will be replaced with a fixup value.
219 llvm_unreachable("Must be immediate or expr");
221 for (unsigned j = 0; j < 4; j++) {
222 OS.write((uint8_t) ((Imm >> (8 * j)) & 0xff));
225 // Only one literal value allowed
230 unsigned SIMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
231 SmallVectorImpl<MCFixup> &Fixups,
232 const MCSubtargetInfo &STI) const {
233 const MCOperand &MO = MI.getOperand(OpNo);
236 const MCExpr *Expr = MO.getExpr();
237 MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br;
238 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
242 return getMachineOpValue(MI, MO, Fixups, STI);
245 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
247 SmallVectorImpl<MCFixup> &Fixups,
248 const MCSubtargetInfo &STI) const {
250 return MRI.getEncodingValue(MO.getReg());
253 const MCSymbolRefExpr *Expr = cast<MCSymbolRefExpr>(MO.getExpr());
255 const MCSymbol *Sym =
256 Ctx.GetOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
258 if (&Expr->getSymbol() == Sym) {
259 // Add the offset to the beginning of the constant values.
260 Kind = (MCFixupKind)AMDGPU::fixup_si_end_of_text;
262 // This is used for constant data stored in .rodata.
263 Kind = (MCFixupKind)AMDGPU::fixup_si_rodata;
265 Fixups.push_back(MCFixup::Create(4, Expr, Kind, MI.getLoc()));
268 // Figure out the operand number, needed for isSrcOperand check
270 for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) {
271 if (&MO == &MI.getOperand(OpNo))
275 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
276 if (isSrcOperand(Desc, OpNo)) {
277 int RCID = Desc.OpInfo[OpNo].RegClass;
278 const MCRegisterClass &RC = MRI.getRegClass(RCID);
280 uint32_t Enc = getLitEncoding(MO, RC.getSize());
281 if (Enc != ~0U && (Enc != 255 || Desc.getSize() == 4))
284 } else if (MO.isImm())
287 llvm_unreachable("Encoding of this operand type is not supported yet.");