1 //===-- R600ControlFlowFinalizer.cpp - Finalize Control Flow Inst----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This pass compute turns all control flow pseudo instructions into native one
12 /// computing their address on the fly ; it also sets STACK_SIZE info.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/Support/Debug.h"
17 #include "AMDGPUSubtarget.h"
18 #include "R600Defines.h"
19 #include "R600InstrInfo.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "r600cf"
38 FIRST_NON_WQM_PUSH = 2,
39 FIRST_NON_WQM_PUSH_W_FULL_ENTRY = 3
42 const AMDGPUSubtarget &ST;
43 std::vector<StackItem> BranchStack;
44 std::vector<StackItem> LoopStack;
45 unsigned MaxStackSize;
46 unsigned CurrentEntries;
47 unsigned CurrentSubEntries;
49 CFStack(const AMDGPUSubtarget &st, unsigned ShaderType) : ST(st),
50 // We need to reserve a stack entry for CALL_FS in vertex shaders.
51 MaxStackSize(ShaderType == ShaderType::VERTEX ? 1 : 0),
52 CurrentEntries(0), CurrentSubEntries(0) { }
54 unsigned getLoopDepth();
55 bool branchStackContains(CFStack::StackItem);
56 bool requiresWorkAroundForInst(unsigned Opcode);
57 unsigned getSubEntrySize(CFStack::StackItem Item);
58 void updateMaxStackSize();
59 void pushBranch(unsigned Opcode, bool isWQM = false);
65 unsigned CFStack::getLoopDepth() {
66 return LoopStack.size();
69 bool CFStack::branchStackContains(CFStack::StackItem Item) {
70 for (std::vector<CFStack::StackItem>::const_iterator I = BranchStack.begin(),
71 E = BranchStack.end(); I != E; ++I) {
78 bool CFStack::requiresWorkAroundForInst(unsigned Opcode) {
79 if (Opcode == AMDGPU::CF_ALU_PUSH_BEFORE && ST.hasCaymanISA() &&
83 if (!ST.hasCFAluBug())
87 default: return false;
88 case AMDGPU::CF_ALU_PUSH_BEFORE:
89 case AMDGPU::CF_ALU_ELSE_AFTER:
90 case AMDGPU::CF_ALU_BREAK:
91 case AMDGPU::CF_ALU_CONTINUE:
92 if (CurrentSubEntries == 0)
94 if (ST.getWavefrontSize() == 64) {
95 // We are being conservative here. We only require this work-around if
96 // CurrentSubEntries > 3 &&
97 // (CurrentSubEntries % 4 == 3 || CurrentSubEntries % 4 == 0)
99 // We have to be conservative, because we don't know for certain that
100 // our stack allocation algorithm for Evergreen/NI is correct. Applying this
101 // work-around when CurrentSubEntries > 3 allows us to over-allocate stack
102 // resources without any problems.
103 return CurrentSubEntries > 3;
105 assert(ST.getWavefrontSize() == 32);
106 // We are being conservative here. We only require the work-around if
107 // CurrentSubEntries > 7 &&
108 // (CurrentSubEntries % 8 == 7 || CurrentSubEntries % 8 == 0)
109 // See the comment on the wavefront size == 64 case for why we are
110 // being conservative.
111 return CurrentSubEntries > 7;
116 unsigned CFStack::getSubEntrySize(CFStack::StackItem Item) {
120 case CFStack::FIRST_NON_WQM_PUSH:
121 assert(!ST.hasCaymanISA());
122 if (ST.getGeneration() <= AMDGPUSubtarget::R700) {
123 // +1 For the push operation.
124 // +2 Extra space required.
127 // Some documentation says that this is not necessary on Evergreen,
128 // but experimentation has show that we need to allocate 1 extra
129 // sub-entry for the first non-WQM push.
130 // +1 For the push operation.
131 // +1 Extra space required.
134 case CFStack::FIRST_NON_WQM_PUSH_W_FULL_ENTRY:
135 assert(ST.getGeneration() >= AMDGPUSubtarget::EVERGREEN);
136 // +1 For the push operation.
137 // +1 Extra space required.
139 case CFStack::SUB_ENTRY:
144 void CFStack::updateMaxStackSize() {
145 unsigned CurrentStackSize = CurrentEntries +
146 (RoundUpToAlignment(CurrentSubEntries, 4) / 4);
147 MaxStackSize = std::max(CurrentStackSize, MaxStackSize);
150 void CFStack::pushBranch(unsigned Opcode, bool isWQM) {
151 CFStack::StackItem Item = CFStack::ENTRY;
153 case AMDGPU::CF_PUSH_EG:
154 case AMDGPU::CF_ALU_PUSH_BEFORE:
156 if (!ST.hasCaymanISA() && !branchStackContains(CFStack::FIRST_NON_WQM_PUSH))
157 Item = CFStack::FIRST_NON_WQM_PUSH; // May not be required on Evergreen/NI
159 // CFStack::getSubEntrySize()
160 else if (CurrentEntries > 0 &&
161 ST.getGeneration() > AMDGPUSubtarget::EVERGREEN &&
162 !ST.hasCaymanISA() &&
163 !branchStackContains(CFStack::FIRST_NON_WQM_PUSH_W_FULL_ENTRY))
164 Item = CFStack::FIRST_NON_WQM_PUSH_W_FULL_ENTRY;
166 Item = CFStack::SUB_ENTRY;
168 Item = CFStack::ENTRY;
171 BranchStack.push_back(Item);
172 if (Item == CFStack::ENTRY)
175 CurrentSubEntries += getSubEntrySize(Item);
176 updateMaxStackSize();
179 void CFStack::pushLoop() {
180 LoopStack.push_back(CFStack::ENTRY);
182 updateMaxStackSize();
185 void CFStack::popBranch() {
186 CFStack::StackItem Top = BranchStack.back();
187 if (Top == CFStack::ENTRY)
190 CurrentSubEntries-= getSubEntrySize(Top);
191 BranchStack.pop_back();
194 void CFStack::popLoop() {
196 LoopStack.pop_back();
199 class R600ControlFlowFinalizer : public MachineFunctionPass {
202 typedef std::pair<MachineInstr *, std::vector<MachineInstr *> > ClauseFile;
204 enum ControlFlowInstruction {
219 const R600InstrInfo *TII;
220 const R600RegisterInfo *TRI;
221 unsigned MaxFetchInst;
222 const AMDGPUSubtarget &ST;
224 bool IsTrivialInst(MachineInstr *MI) const {
225 switch (MI->getOpcode()) {
234 const MCInstrDesc &getHWInstrDesc(ControlFlowInstruction CFI) const {
236 bool isEg = (ST.getGeneration() >= AMDGPUSubtarget::EVERGREEN);
239 Opcode = isEg ? AMDGPU::CF_TC_EG : AMDGPU::CF_TC_R600;
242 Opcode = isEg ? AMDGPU::CF_VC_EG : AMDGPU::CF_VC_R600;
245 Opcode = isEg ? AMDGPU::CF_CALL_FS_EG : AMDGPU::CF_CALL_FS_R600;
248 Opcode = isEg ? AMDGPU::WHILE_LOOP_EG : AMDGPU::WHILE_LOOP_R600;
251 Opcode = isEg ? AMDGPU::END_LOOP_EG : AMDGPU::END_LOOP_R600;
254 Opcode = isEg ? AMDGPU::LOOP_BREAK_EG : AMDGPU::LOOP_BREAK_R600;
256 case CF_LOOP_CONTINUE:
257 Opcode = isEg ? AMDGPU::CF_CONTINUE_EG : AMDGPU::CF_CONTINUE_R600;
260 Opcode = isEg ? AMDGPU::CF_JUMP_EG : AMDGPU::CF_JUMP_R600;
263 Opcode = isEg ? AMDGPU::CF_ELSE_EG : AMDGPU::CF_ELSE_R600;
266 Opcode = isEg ? AMDGPU::POP_EG : AMDGPU::POP_R600;
269 if (ST.hasCaymanISA()) {
270 Opcode = AMDGPU::CF_END_CM;
273 Opcode = isEg ? AMDGPU::CF_END_EG : AMDGPU::CF_END_R600;
276 assert (Opcode && "No opcode selected");
277 return TII->get(Opcode);
280 bool isCompatibleWithClause(const MachineInstr *MI,
281 std::set<unsigned> &DstRegs) const {
282 unsigned DstMI, SrcMI;
283 for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
284 E = MI->operands_end(); I != E; ++I) {
285 const MachineOperand &MO = *I;
289 unsigned Reg = MO.getReg();
290 if (AMDGPU::R600_Reg128RegClass.contains(Reg))
293 DstMI = TRI->getMatchingSuperReg(Reg,
294 TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)),
295 &AMDGPU::R600_Reg128RegClass);
298 unsigned Reg = MO.getReg();
299 if (AMDGPU::R600_Reg128RegClass.contains(Reg))
302 SrcMI = TRI->getMatchingSuperReg(Reg,
303 TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)),
304 &AMDGPU::R600_Reg128RegClass);
307 if ((DstRegs.find(SrcMI) == DstRegs.end())) {
308 DstRegs.insert(DstMI);
315 MakeFetchClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I)
317 MachineBasicBlock::iterator ClauseHead = I;
318 std::vector<MachineInstr *> ClauseContent;
319 unsigned AluInstCount = 0;
320 bool IsTex = TII->usesTextureCache(ClauseHead);
321 std::set<unsigned> DstRegs;
322 for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
323 if (IsTrivialInst(I))
325 if (AluInstCount >= MaxFetchInst)
327 if ((IsTex && !TII->usesTextureCache(I)) ||
328 (!IsTex && !TII->usesVertexCache(I)))
330 if (!isCompatibleWithClause(I, DstRegs))
333 ClauseContent.push_back(I);
335 MachineInstr *MIb = BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead),
336 getHWInstrDesc(IsTex?CF_TC:CF_VC))
338 .addImm(AluInstCount - 1); // COUNT
339 return ClauseFile(MIb, ClauseContent);
342 void getLiteral(MachineInstr *MI, std::vector<int64_t> &Lits) const {
343 static const unsigned LiteralRegs[] = {
344 AMDGPU::ALU_LITERAL_X,
345 AMDGPU::ALU_LITERAL_Y,
346 AMDGPU::ALU_LITERAL_Z,
347 AMDGPU::ALU_LITERAL_W
349 const SmallVector<std::pair<MachineOperand *, int64_t>, 3 > Srcs =
351 for (unsigned i = 0, e = Srcs.size(); i < e; ++i) {
352 if (Srcs[i].first->getReg() != AMDGPU::ALU_LITERAL_X)
354 int64_t Imm = Srcs[i].second;
355 std::vector<int64_t>::iterator It =
356 std::find(Lits.begin(), Lits.end(), Imm);
357 if (It != Lits.end()) {
358 unsigned Index = It - Lits.begin();
359 Srcs[i].first->setReg(LiteralRegs[Index]);
361 assert(Lits.size() < 4 && "Too many literals in Instruction Group");
362 Srcs[i].first->setReg(LiteralRegs[Lits.size()]);
368 MachineBasicBlock::iterator insertLiterals(
369 MachineBasicBlock::iterator InsertPos,
370 const std::vector<unsigned> &Literals) const {
371 MachineBasicBlock *MBB = InsertPos->getParent();
372 for (unsigned i = 0, e = Literals.size(); i < e; i+=2) {
373 unsigned LiteralPair0 = Literals[i];
374 unsigned LiteralPair1 = (i + 1 < e)?Literals[i + 1]:0;
375 InsertPos = BuildMI(MBB, InsertPos->getDebugLoc(),
376 TII->get(AMDGPU::LITERALS))
377 .addImm(LiteralPair0)
378 .addImm(LiteralPair1);
384 MakeALUClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I)
386 MachineBasicBlock::iterator ClauseHead = I;
387 std::vector<MachineInstr *> ClauseContent;
389 for (MachineBasicBlock::instr_iterator E = MBB.instr_end(); I != E;) {
390 if (IsTrivialInst(I)) {
394 if (!I->isBundle() && !TII->isALUInstr(I->getOpcode()))
396 std::vector<int64_t> Literals;
398 MachineInstr *DeleteMI = I;
399 MachineBasicBlock::instr_iterator BI = I.getInstrIterator();
400 while (++BI != E && BI->isBundledWithPred()) {
401 BI->unbundleFromPred();
402 for (unsigned i = 0, e = BI->getNumOperands(); i != e; ++i) {
403 MachineOperand &MO = BI->getOperand(i);
404 if (MO.isReg() && MO.isInternalRead())
405 MO.setIsInternalRead(false);
407 getLiteral(BI, Literals);
408 ClauseContent.push_back(BI);
411 DeleteMI->eraseFromParent();
413 getLiteral(I, Literals);
414 ClauseContent.push_back(I);
417 for (unsigned i = 0, e = Literals.size(); i < e; i+=2) {
418 unsigned literal0 = Literals[i];
419 unsigned literal2 = (i + 1 < e)?Literals[i + 1]:0;
420 MachineInstr *MILit = BuildMI(MBB, I, I->getDebugLoc(),
421 TII->get(AMDGPU::LITERALS))
424 ClauseContent.push_back(MILit);
427 assert(ClauseContent.size() < 128 && "ALU clause is too big");
428 ClauseHead->getOperand(7).setImm(ClauseContent.size() - 1);
429 return ClauseFile(ClauseHead, ClauseContent);
433 EmitFetchClause(MachineBasicBlock::iterator InsertPos, ClauseFile &Clause,
435 CounterPropagateAddr(Clause.first, CfCount);
436 MachineBasicBlock *BB = Clause.first->getParent();
437 BuildMI(BB, InsertPos->getDebugLoc(), TII->get(AMDGPU::FETCH_CLAUSE))
439 for (unsigned i = 0, e = Clause.second.size(); i < e; ++i) {
440 BB->splice(InsertPos, BB, Clause.second[i]);
442 CfCount += 2 * Clause.second.size();
446 EmitALUClause(MachineBasicBlock::iterator InsertPos, ClauseFile &Clause,
448 Clause.first->getOperand(0).setImm(0);
449 CounterPropagateAddr(Clause.first, CfCount);
450 MachineBasicBlock *BB = Clause.first->getParent();
451 BuildMI(BB, InsertPos->getDebugLoc(), TII->get(AMDGPU::ALU_CLAUSE))
453 for (unsigned i = 0, e = Clause.second.size(); i < e; ++i) {
454 BB->splice(InsertPos, BB, Clause.second[i]);
456 CfCount += Clause.second.size();
459 void CounterPropagateAddr(MachineInstr *MI, unsigned Addr) const {
460 MI->getOperand(0).setImm(Addr + MI->getOperand(0).getImm());
462 void CounterPropagateAddr(std::set<MachineInstr *> MIs, unsigned Addr)
464 for (std::set<MachineInstr *>::iterator It = MIs.begin(), E = MIs.end();
466 MachineInstr *MI = *It;
467 CounterPropagateAddr(MI, Addr);
472 R600ControlFlowFinalizer(TargetMachine &tm) : MachineFunctionPass(ID),
473 TII (nullptr), TRI(nullptr),
474 ST(tm.getSubtarget<AMDGPUSubtarget>()) {
475 const AMDGPUSubtarget &ST = tm.getSubtarget<AMDGPUSubtarget>();
476 MaxFetchInst = ST.getTexVTXClauseSize();
479 bool runOnMachineFunction(MachineFunction &MF) override {
480 TII = static_cast<const R600InstrInfo *>(MF.getSubtarget().getInstrInfo());
481 TRI = static_cast<const R600RegisterInfo *>(
482 MF.getSubtarget().getRegisterInfo());
483 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
485 CFStack CFStack(ST, MFI->getShaderType());
486 for (MachineFunction::iterator MB = MF.begin(), ME = MF.end(); MB != ME;
488 MachineBasicBlock &MBB = *MB;
489 unsigned CfCount = 0;
490 std::vector<std::pair<unsigned, std::set<MachineInstr *> > > LoopStack;
491 std::vector<MachineInstr * > IfThenElseStack;
492 if (MFI->getShaderType() == ShaderType::VERTEX) {
493 BuildMI(MBB, MBB.begin(), MBB.findDebugLoc(MBB.begin()),
494 getHWInstrDesc(CF_CALL_FS));
497 std::vector<ClauseFile> FetchClauses, AluClauses;
498 std::vector<MachineInstr *> LastAlu(1);
499 std::vector<MachineInstr *> ToPopAfter;
501 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
503 if (TII->usesTextureCache(I) || TII->usesVertexCache(I)) {
504 DEBUG(dbgs() << CfCount << ":"; I->dump(););
505 FetchClauses.push_back(MakeFetchClause(MBB, I));
507 LastAlu.back() = nullptr;
511 MachineBasicBlock::iterator MI = I;
512 if (MI->getOpcode() != AMDGPU::ENDIF)
513 LastAlu.back() = nullptr;
514 if (MI->getOpcode() == AMDGPU::CF_ALU)
517 bool RequiresWorkAround =
518 CFStack.requiresWorkAroundForInst(MI->getOpcode());
519 switch (MI->getOpcode()) {
520 case AMDGPU::CF_ALU_PUSH_BEFORE:
521 if (RequiresWorkAround) {
522 DEBUG(dbgs() << "Applying bug work-around for ALU_PUSH_BEFORE\n");
523 BuildMI(MBB, MI, MBB.findDebugLoc(MI), TII->get(AMDGPU::CF_PUSH_EG))
526 MI->setDesc(TII->get(AMDGPU::CF_ALU));
528 CFStack.pushBranch(AMDGPU::CF_PUSH_EG);
530 CFStack.pushBranch(AMDGPU::CF_ALU_PUSH_BEFORE);
534 AluClauses.push_back(MakeALUClause(MBB, I));
535 DEBUG(dbgs() << CfCount << ":"; MI->dump(););
538 case AMDGPU::WHILELOOP: {
540 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
541 getHWInstrDesc(CF_WHILE_LOOP))
543 std::pair<unsigned, std::set<MachineInstr *> > Pair(CfCount,
544 std::set<MachineInstr *>());
545 Pair.second.insert(MIb);
546 LoopStack.push_back(Pair);
547 MI->eraseFromParent();
551 case AMDGPU::ENDLOOP: {
553 std::pair<unsigned, std::set<MachineInstr *> > Pair =
555 LoopStack.pop_back();
556 CounterPropagateAddr(Pair.second, CfCount);
557 BuildMI(MBB, MI, MBB.findDebugLoc(MI), getHWInstrDesc(CF_END_LOOP))
558 .addImm(Pair.first + 1);
559 MI->eraseFromParent();
563 case AMDGPU::IF_PREDICATE_SET: {
564 LastAlu.push_back(nullptr);
565 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
566 getHWInstrDesc(CF_JUMP))
569 IfThenElseStack.push_back(MIb);
570 DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
571 MI->eraseFromParent();
576 MachineInstr * JumpInst = IfThenElseStack.back();
577 IfThenElseStack.pop_back();
578 CounterPropagateAddr(JumpInst, CfCount);
579 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
580 getHWInstrDesc(CF_ELSE))
583 DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
584 IfThenElseStack.push_back(MIb);
585 MI->eraseFromParent();
589 case AMDGPU::ENDIF: {
591 if (LastAlu.back()) {
592 ToPopAfter.push_back(LastAlu.back());
594 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
595 getHWInstrDesc(CF_POP))
599 DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
603 MachineInstr *IfOrElseInst = IfThenElseStack.back();
604 IfThenElseStack.pop_back();
605 CounterPropagateAddr(IfOrElseInst, CfCount);
606 IfOrElseInst->getOperand(1).setImm(1);
608 MI->eraseFromParent();
611 case AMDGPU::BREAK: {
613 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
614 getHWInstrDesc(CF_LOOP_BREAK))
616 LoopStack.back().second.insert(MIb);
617 MI->eraseFromParent();
620 case AMDGPU::CONTINUE: {
621 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
622 getHWInstrDesc(CF_LOOP_CONTINUE))
624 LoopStack.back().second.insert(MIb);
625 MI->eraseFromParent();
629 case AMDGPU::RETURN: {
630 BuildMI(MBB, MI, MBB.findDebugLoc(MI), getHWInstrDesc(CF_END));
632 MI->eraseFromParent();
634 BuildMI(MBB, I, MBB.findDebugLoc(MI), TII->get(AMDGPU::PAD));
637 for (unsigned i = 0, e = FetchClauses.size(); i < e; i++)
638 EmitFetchClause(I, FetchClauses[i], CfCount);
639 for (unsigned i = 0, e = AluClauses.size(); i < e; i++)
640 EmitALUClause(I, AluClauses[i], CfCount);
643 if (TII->isExport(MI->getOpcode())) {
644 DEBUG(dbgs() << CfCount << ":"; MI->dump(););
650 for (unsigned i = 0, e = ToPopAfter.size(); i < e; ++i) {
651 MachineInstr *Alu = ToPopAfter[i];
652 BuildMI(MBB, Alu, MBB.findDebugLoc((MachineBasicBlock::iterator)Alu),
653 TII->get(AMDGPU::CF_ALU_POP_AFTER))
654 .addImm(Alu->getOperand(0).getImm())
655 .addImm(Alu->getOperand(1).getImm())
656 .addImm(Alu->getOperand(2).getImm())
657 .addImm(Alu->getOperand(3).getImm())
658 .addImm(Alu->getOperand(4).getImm())
659 .addImm(Alu->getOperand(5).getImm())
660 .addImm(Alu->getOperand(6).getImm())
661 .addImm(Alu->getOperand(7).getImm())
662 .addImm(Alu->getOperand(8).getImm());
663 Alu->eraseFromParent();
665 MFI->StackSize = CFStack.MaxStackSize;
671 const char *getPassName() const override {
672 return "R600 Control Flow Finalizer Pass";
676 char R600ControlFlowFinalizer::ID = 0;
678 } // end anonymous namespace
681 llvm::FunctionPass *llvm::createR600ControlFlowFinalizer(TargetMachine &TM) {
682 return new R600ControlFlowFinalizer(TM);