1 //===-- R600ControlFlowFinalizer.cpp - Finalize Control Flow Inst----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This pass compute turns all control flow pseudo instructions into native one
12 /// computing their address on the fly ; it also sets STACK_SIZE info.
13 //===----------------------------------------------------------------------===//
16 #include "R600Defines.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineFunctionInfo.h"
19 #include "R600RegisterInfo.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 class R600ControlFlowFinalizer : public MachineFunctionPass {
30 const R600InstrInfo *TII;
31 unsigned MaxFetchInst;
33 bool isFetch(const MachineInstr *MI) const {
34 switch (MI->getOpcode()) {
35 case AMDGPU::TEX_VTX_CONSTBUF:
36 case AMDGPU::TEX_VTX_TEXBUF:
38 case AMDGPU::TEX_GET_TEXTURE_RESINFO:
39 case AMDGPU::TEX_GET_GRADIENTS_H:
40 case AMDGPU::TEX_GET_GRADIENTS_V:
41 case AMDGPU::TEX_SET_GRADIENTS_H:
42 case AMDGPU::TEX_SET_GRADIENTS_V:
43 case AMDGPU::TEX_SAMPLE:
44 case AMDGPU::TEX_SAMPLE_C:
45 case AMDGPU::TEX_SAMPLE_L:
46 case AMDGPU::TEX_SAMPLE_C_L:
47 case AMDGPU::TEX_SAMPLE_LB:
48 case AMDGPU::TEX_SAMPLE_C_LB:
49 case AMDGPU::TEX_SAMPLE_G:
50 case AMDGPU::TEX_SAMPLE_C_G:
52 case AMDGPU::TXD_SHADOW:
59 bool IsTrivialInst(MachineInstr *MI) const {
60 switch (MI->getOpcode()) {
69 MachineBasicBlock::iterator
70 MakeFetchClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
71 unsigned CfAddress) const {
72 MachineBasicBlock::iterator ClauseHead = I;
73 unsigned AluInstCount = 0;
74 for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
80 if (AluInstCount > MaxFetchInst)
83 BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead),
84 TII->get(AMDGPU::CF_TC))
85 .addImm(CfAddress) // ADDR
86 .addImm(AluInstCount); // COUNT
89 void CounterPropagateAddr(MachineInstr *MI, unsigned Addr) const {
90 switch (MI->getOpcode()) {
91 case AMDGPU::WHILE_LOOP:
92 MI->getOperand(0).setImm(Addr + 1);
95 MI->getOperand(0).setImm(Addr);
99 void CounterPropagateAddr(std::set<MachineInstr *> MIs, unsigned Addr)
101 for (std::set<MachineInstr *>::iterator It = MIs.begin(), E = MIs.end();
103 MachineInstr *MI = *It;
104 CounterPropagateAddr(MI, Addr);
109 R600ControlFlowFinalizer(TargetMachine &tm) : MachineFunctionPass(ID),
110 TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) {
111 const AMDGPUSubtarget &ST = tm.getSubtarget<AMDGPUSubtarget>();
112 if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD4XXX)
118 virtual bool runOnMachineFunction(MachineFunction &MF) {
119 unsigned MaxStack = 0;
120 unsigned CurrentStack = 0;
121 for (MachineFunction::iterator MB = MF.begin(), ME = MF.end(); MB != ME;
123 MachineBasicBlock &MBB = *MB;
124 unsigned CfCount = 0;
125 std::vector<std::pair<unsigned, std::set<MachineInstr *> > > LoopStack;
126 std::vector<std::pair<unsigned, MachineInstr *> > IfThenElseStack;
127 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
128 if (MFI->ShaderType == 1) {
129 BuildMI(MBB, MBB.begin(), MBB.findDebugLoc(MBB.begin()),
130 TII->get(AMDGPU::CF_CALL_FS));
133 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
136 I = MakeFetchClause(MBB, I, 0);
141 MachineBasicBlock::iterator MI = I;
143 switch (MI->getOpcode()) {
144 case AMDGPU::CF_ALU_PUSH_BEFORE:
146 MaxStack = std::max(MaxStack, CurrentStack);
150 case AMDGPU::WHILELOOP: {
152 MaxStack = std::max(MaxStack, CurrentStack);
153 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
154 TII->get(AMDGPU::WHILE_LOOP))
156 std::pair<unsigned, std::set<MachineInstr *> > Pair(CfCount,
157 std::set<MachineInstr *>());
158 Pair.second.insert(MIb);
159 LoopStack.push_back(Pair);
160 MI->eraseFromParent();
164 case AMDGPU::ENDLOOP: {
166 std::pair<unsigned, std::set<MachineInstr *> > Pair =
168 LoopStack.pop_back();
169 CounterPropagateAddr(Pair.second, CfCount);
170 BuildMI(MBB, MI, MBB.findDebugLoc(MI), TII->get(AMDGPU::END_LOOP))
171 .addImm(Pair.first + 1);
172 MI->eraseFromParent();
176 case AMDGPU::IF_PREDICATE_SET: {
177 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
178 TII->get(AMDGPU::CF_JUMP))
181 std::pair<unsigned, MachineInstr *> Pair(CfCount, MIb);
182 IfThenElseStack.push_back(Pair);
183 MI->eraseFromParent();
188 std::pair<unsigned, MachineInstr *> Pair = IfThenElseStack.back();
189 IfThenElseStack.pop_back();
190 CounterPropagateAddr(Pair.second, CfCount);
191 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
192 TII->get(AMDGPU::CF_ELSE))
195 std::pair<unsigned, MachineInstr *> NewPair(CfCount, MIb);
196 IfThenElseStack.push_back(NewPair);
197 MI->eraseFromParent();
201 case AMDGPU::ENDIF: {
203 std::pair<unsigned, MachineInstr *> Pair = IfThenElseStack.back();
204 IfThenElseStack.pop_back();
205 CounterPropagateAddr(Pair.second, CfCount + 1);
206 BuildMI(MBB, MI, MBB.findDebugLoc(MI), TII->get(AMDGPU::POP))
209 MI->eraseFromParent();
213 case AMDGPU::PREDICATED_BREAK: {
216 BuildMI(MBB, MI, MBB.findDebugLoc(MI), TII->get(AMDGPU::CF_JUMP))
219 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
220 TII->get(AMDGPU::LOOP_BREAK))
222 BuildMI(MBB, MI, MBB.findDebugLoc(MI), TII->get(AMDGPU::POP))
225 LoopStack.back().second.insert(MIb);
226 MI->eraseFromParent();
229 case AMDGPU::CONTINUE: {
230 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
231 TII->get(AMDGPU::CF_CONTINUE))
233 LoopStack.back().second.insert(MIb);
234 MI->eraseFromParent();
242 BuildMI(MBB, MBB.begin(), MBB.findDebugLoc(MBB.begin()),
243 TII->get(AMDGPU::STACK_SIZE))
250 const char *getPassName() const {
251 return "R600 Control Flow Finalizer Pass";
255 char R600ControlFlowFinalizer::ID = 0;
260 llvm::FunctionPass *llvm::createR600ControlFlowFinalizer(TargetMachine &TM) {
261 return new R600ControlFlowFinalizer(TM);