1 //===-- R600ControlFlowFinalizer.cpp - Finalize Control Flow Inst----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This pass compute turns all control flow pseudo instructions into native one
12 /// computing their address on the fly ; it also sets STACK_SIZE info.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "r600cf"
16 #include "llvm/Support/Debug.h"
18 #include "R600Defines.h"
19 #include "R600InstrInfo.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/Support/raw_ostream.h"
31 class R600ControlFlowFinalizer : public MachineFunctionPass {
34 typedef std::pair<MachineInstr *, std::vector<MachineInstr *> > ClauseFile;
36 enum ControlFlowInstruction {
51 const R600InstrInfo *TII;
52 const R600RegisterInfo &TRI;
53 unsigned MaxFetchInst;
54 const AMDGPUSubtarget &ST;
56 bool IsTrivialInst(MachineInstr *MI) const {
57 switch (MI->getOpcode()) {
66 const MCInstrDesc &getHWInstrDesc(ControlFlowInstruction CFI) const {
68 bool isEg = (ST.device()->getGeneration() >= AMDGPUDeviceInfo::HD5XXX);
71 Opcode = isEg ? AMDGPU::CF_TC_EG : AMDGPU::CF_TC_R600;
74 Opcode = isEg ? AMDGPU::CF_VC_EG : AMDGPU::CF_VC_R600;
77 Opcode = isEg ? AMDGPU::CF_CALL_FS_EG : AMDGPU::CF_CALL_FS_R600;
80 Opcode = isEg ? AMDGPU::WHILE_LOOP_EG : AMDGPU::WHILE_LOOP_R600;
83 Opcode = isEg ? AMDGPU::END_LOOP_EG : AMDGPU::END_LOOP_R600;
86 Opcode = isEg ? AMDGPU::LOOP_BREAK_EG : AMDGPU::LOOP_BREAK_R600;
88 case CF_LOOP_CONTINUE:
89 Opcode = isEg ? AMDGPU::CF_CONTINUE_EG : AMDGPU::CF_CONTINUE_R600;
92 Opcode = isEg ? AMDGPU::CF_JUMP_EG : AMDGPU::CF_JUMP_R600;
95 Opcode = isEg ? AMDGPU::CF_ELSE_EG : AMDGPU::CF_ELSE_R600;
98 Opcode = isEg ? AMDGPU::POP_EG : AMDGPU::POP_R600;
101 if (ST.device()->getDeviceFlag() == OCL_DEVICE_CAYMAN) {
102 Opcode = AMDGPU::CF_END_CM;
105 Opcode = isEg ? AMDGPU::CF_END_EG : AMDGPU::CF_END_R600;
108 assert (Opcode && "No opcode selected");
109 return TII->get(Opcode);
112 bool isCompatibleWithClause(const MachineInstr *MI,
113 std::set<unsigned> &DstRegs, std::set<unsigned> &SrcRegs) const {
114 unsigned DstMI, SrcMI;
115 for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
116 E = MI->operands_end(); I != E; ++I) {
117 const MachineOperand &MO = *I;
121 unsigned Reg = MO.getReg();
122 if (AMDGPU::R600_Reg128RegClass.contains(Reg))
125 DstMI = TRI.getMatchingSuperReg(Reg,
126 TRI.getSubRegFromChannel(TRI.getHWRegChan(Reg)),
127 &AMDGPU::R600_Reg128RegClass);
130 unsigned Reg = MO.getReg();
131 if (AMDGPU::R600_Reg128RegClass.contains(Reg))
134 SrcMI = TRI.getMatchingSuperReg(Reg,
135 TRI.getSubRegFromChannel(TRI.getHWRegChan(Reg)),
136 &AMDGPU::R600_Reg128RegClass);
139 if ((DstRegs.find(SrcMI) == DstRegs.end()) &&
140 (SrcRegs.find(DstMI) == SrcRegs.end())) {
141 SrcRegs.insert(SrcMI);
142 DstRegs.insert(DstMI);
149 MakeFetchClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I)
151 MachineBasicBlock::iterator ClauseHead = I;
152 std::vector<MachineInstr *> ClauseContent;
153 unsigned AluInstCount = 0;
154 bool IsTex = TII->usesTextureCache(ClauseHead);
155 std::set<unsigned> DstRegs, SrcRegs;
156 for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
157 if (IsTrivialInst(I))
159 if (AluInstCount >= MaxFetchInst)
161 if ((IsTex && !TII->usesTextureCache(I)) ||
162 (!IsTex && !TII->usesVertexCache(I)))
164 if (!isCompatibleWithClause(I, DstRegs, SrcRegs))
167 ClauseContent.push_back(I);
169 MachineInstr *MIb = BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead),
170 getHWInstrDesc(IsTex?CF_TC:CF_VC))
172 .addImm(AluInstCount - 1); // COUNT
173 return ClauseFile(MIb, ClauseContent);
176 void getLiteral(MachineInstr *MI, std::vector<int64_t> &Lits) const {
177 unsigned LiteralRegs[] = {
178 AMDGPU::ALU_LITERAL_X,
179 AMDGPU::ALU_LITERAL_Y,
180 AMDGPU::ALU_LITERAL_Z,
181 AMDGPU::ALU_LITERAL_W
183 const SmallVector<std::pair<MachineOperand *, int64_t>, 3 > Srcs =
185 for (unsigned i = 0, e = Srcs.size(); i < e; ++i) {
186 if (Srcs[i].first->getReg() != AMDGPU::ALU_LITERAL_X)
188 int64_t Imm = Srcs[i].second;
189 std::vector<int64_t>::iterator It =
190 std::find(Lits.begin(), Lits.end(), Imm);
191 if (It != Lits.end()) {
192 unsigned Index = It - Lits.begin();
193 Srcs[i].first->setReg(LiteralRegs[Index]);
195 assert(Lits.size() < 4 && "Too many literals in Instruction Group");
196 Srcs[i].first->setReg(LiteralRegs[Lits.size()]);
202 MachineBasicBlock::iterator insertLiterals(
203 MachineBasicBlock::iterator InsertPos,
204 const std::vector<unsigned> &Literals) const {
205 MachineBasicBlock *MBB = InsertPos->getParent();
206 for (unsigned i = 0, e = Literals.size(); i < e; i+=2) {
207 unsigned LiteralPair0 = Literals[i];
208 unsigned LiteralPair1 = (i + 1 < e)?Literals[i + 1]:0;
209 InsertPos = BuildMI(MBB, InsertPos->getDebugLoc(),
210 TII->get(AMDGPU::LITERALS))
211 .addImm(LiteralPair0)
212 .addImm(LiteralPair1);
218 MakeALUClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I)
220 MachineBasicBlock::iterator ClauseHead = I;
221 std::vector<MachineInstr *> ClauseContent;
223 for (MachineBasicBlock::instr_iterator E = MBB.instr_end(); I != E;) {
224 if (IsTrivialInst(I)) {
228 if (!I->isBundle() && !TII->isALUInstr(I->getOpcode()))
230 std::vector<int64_t> Literals;
232 MachineInstr *DeleteMI = I;
233 MachineBasicBlock::instr_iterator BI = I.getInstrIterator();
234 while (++BI != E && BI->isBundledWithPred()) {
235 BI->unbundleFromPred();
236 for (unsigned i = 0, e = BI->getNumOperands(); i != e; ++i) {
237 MachineOperand &MO = BI->getOperand(i);
238 if (MO.isReg() && MO.isInternalRead())
239 MO.setIsInternalRead(false);
241 getLiteral(BI, Literals);
242 ClauseContent.push_back(BI);
245 DeleteMI->eraseFromParent();
247 getLiteral(I, Literals);
248 ClauseContent.push_back(I);
251 for (unsigned i = 0, e = Literals.size(); i < e; i+=2) {
252 unsigned literal0 = Literals[i];
253 unsigned literal2 = (i + 1 < e)?Literals[i + 1]:0;
254 MachineInstr *MILit = BuildMI(MBB, I, I->getDebugLoc(),
255 TII->get(AMDGPU::LITERALS))
258 ClauseContent.push_back(MILit);
261 ClauseHead->getOperand(7).setImm(ClauseContent.size() - 1);
262 return ClauseFile(ClauseHead, ClauseContent);
266 EmitFetchClause(MachineBasicBlock::iterator InsertPos, ClauseFile &Clause,
268 CounterPropagateAddr(Clause.first, CfCount);
269 MachineBasicBlock *BB = Clause.first->getParent();
270 BuildMI(BB, InsertPos->getDebugLoc(), TII->get(AMDGPU::FETCH_CLAUSE))
272 for (unsigned i = 0, e = Clause.second.size(); i < e; ++i) {
273 BB->splice(InsertPos, BB, Clause.second[i]);
275 CfCount += 2 * Clause.second.size();
279 EmitALUClause(MachineBasicBlock::iterator InsertPos, ClauseFile &Clause,
281 CounterPropagateAddr(Clause.first, CfCount);
282 MachineBasicBlock *BB = Clause.first->getParent();
283 BuildMI(BB, InsertPos->getDebugLoc(), TII->get(AMDGPU::ALU_CLAUSE))
285 for (unsigned i = 0, e = Clause.second.size(); i < e; ++i) {
286 BB->splice(InsertPos, BB, Clause.second[i]);
288 CfCount += Clause.second.size();
291 void CounterPropagateAddr(MachineInstr *MI, unsigned Addr) const {
292 MI->getOperand(0).setImm(Addr + MI->getOperand(0).getImm());
294 void CounterPropagateAddr(std::set<MachineInstr *> MIs, unsigned Addr)
296 for (std::set<MachineInstr *>::iterator It = MIs.begin(), E = MIs.end();
298 MachineInstr *MI = *It;
299 CounterPropagateAddr(MI, Addr);
303 unsigned getHWStackSize(unsigned StackSubEntry, bool hasPush) const {
304 switch (ST.device()->getGeneration()) {
305 case AMDGPUDeviceInfo::HD4XXX:
309 case AMDGPUDeviceInfo::HD5XXX:
312 case AMDGPUDeviceInfo::HD6XXX:
316 return (StackSubEntry + 3)/4; // Need ceil value of StackSubEntry/4
320 R600ControlFlowFinalizer(TargetMachine &tm) : MachineFunctionPass(ID),
321 TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())),
322 TRI(TII->getRegisterInfo()),
323 ST(tm.getSubtarget<AMDGPUSubtarget>()) {
324 const AMDGPUSubtarget &ST = tm.getSubtarget<AMDGPUSubtarget>();
325 MaxFetchInst = ST.getTexVTXClauseSize();
328 virtual bool runOnMachineFunction(MachineFunction &MF) {
329 unsigned MaxStack = 0;
330 unsigned CurrentStack = 0;
331 bool HasPush = false;
332 for (MachineFunction::iterator MB = MF.begin(), ME = MF.end(); MB != ME;
334 MachineBasicBlock &MBB = *MB;
335 unsigned CfCount = 0;
336 std::vector<std::pair<unsigned, std::set<MachineInstr *> > > LoopStack;
337 std::vector<MachineInstr * > IfThenElseStack;
338 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
339 if (MFI->ShaderType == 1) {
340 BuildMI(MBB, MBB.begin(), MBB.findDebugLoc(MBB.begin()),
341 getHWInstrDesc(CF_CALL_FS));
345 std::vector<ClauseFile> FetchClauses, AluClauses;
346 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
348 if (TII->usesTextureCache(I) || TII->usesVertexCache(I)) {
349 DEBUG(dbgs() << CfCount << ":"; I->dump(););
350 FetchClauses.push_back(MakeFetchClause(MBB, I));
355 MachineBasicBlock::iterator MI = I;
357 switch (MI->getOpcode()) {
358 case AMDGPU::CF_ALU_PUSH_BEFORE:
360 MaxStack = std::max(MaxStack, CurrentStack);
364 AluClauses.push_back(MakeALUClause(MBB, I));
365 case AMDGPU::EG_ExportBuf:
366 case AMDGPU::EG_ExportSwz:
367 case AMDGPU::R600_ExportBuf:
368 case AMDGPU::R600_ExportSwz:
369 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
370 case AMDGPU::RAT_WRITE_CACHELESS_128_eg:
371 DEBUG(dbgs() << CfCount << ":"; MI->dump(););
374 case AMDGPU::WHILELOOP: {
376 MaxStack = std::max(MaxStack, CurrentStack);
377 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
378 getHWInstrDesc(CF_WHILE_LOOP))
380 std::pair<unsigned, std::set<MachineInstr *> > Pair(CfCount,
381 std::set<MachineInstr *>());
382 Pair.second.insert(MIb);
383 LoopStack.push_back(Pair);
384 MI->eraseFromParent();
388 case AMDGPU::ENDLOOP: {
390 std::pair<unsigned, std::set<MachineInstr *> > Pair =
392 LoopStack.pop_back();
393 CounterPropagateAddr(Pair.second, CfCount);
394 BuildMI(MBB, MI, MBB.findDebugLoc(MI), getHWInstrDesc(CF_END_LOOP))
395 .addImm(Pair.first + 1);
396 MI->eraseFromParent();
400 case AMDGPU::IF_PREDICATE_SET: {
401 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
402 getHWInstrDesc(CF_JUMP))
405 IfThenElseStack.push_back(MIb);
406 DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
407 MI->eraseFromParent();
412 MachineInstr * JumpInst = IfThenElseStack.back();
413 IfThenElseStack.pop_back();
414 CounterPropagateAddr(JumpInst, CfCount);
415 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
416 getHWInstrDesc(CF_ELSE))
419 DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
420 IfThenElseStack.push_back(MIb);
421 MI->eraseFromParent();
425 case AMDGPU::ENDIF: {
427 MachineInstr *IfOrElseInst = IfThenElseStack.back();
428 IfThenElseStack.pop_back();
429 CounterPropagateAddr(IfOrElseInst, CfCount + 1);
430 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
431 getHWInstrDesc(CF_POP))
435 DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
436 MI->eraseFromParent();
440 case AMDGPU::PREDICATED_BREAK: {
443 BuildMI(MBB, MI, MBB.findDebugLoc(MI), getHWInstrDesc(CF_JUMP))
446 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
447 getHWInstrDesc(CF_LOOP_BREAK))
449 BuildMI(MBB, MI, MBB.findDebugLoc(MI), getHWInstrDesc(CF_POP))
452 LoopStack.back().second.insert(MIb);
453 MI->eraseFromParent();
456 case AMDGPU::CONTINUE: {
457 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
458 getHWInstrDesc(CF_LOOP_CONTINUE))
460 LoopStack.back().second.insert(MIb);
461 MI->eraseFromParent();
465 case AMDGPU::RETURN: {
466 BuildMI(MBB, MI, MBB.findDebugLoc(MI), getHWInstrDesc(CF_END));
468 MI->eraseFromParent();
470 BuildMI(MBB, I, MBB.findDebugLoc(MI), TII->get(AMDGPU::PAD));
473 for (unsigned i = 0, e = FetchClauses.size(); i < e; i++)
474 EmitFetchClause(I, FetchClauses[i], CfCount);
475 for (unsigned i = 0, e = AluClauses.size(); i < e; i++)
476 EmitALUClause(I, AluClauses[i], CfCount);
482 MFI->StackSize = getHWStackSize(MaxStack, HasPush);
488 const char *getPassName() const {
489 return "R600 Control Flow Finalizer Pass";
493 char R600ControlFlowFinalizer::ID = 0;
495 } // end anonymous namespace
498 llvm::FunctionPass *llvm::createR600ControlFlowFinalizer(TargetMachine &TM) {
499 return new R600ControlFlowFinalizer(TM);