1 //===-- R600EmitClauseMarkers.cpp - Emit CF_ALU ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// Add CF_ALU. R600 Alu instructions are grouped in clause which can hold
12 /// 128 Alu instructions ; these instructions can access up to 4 prefetched
13 /// 4 lines of 16 registers from constant buffers. Such ALU clauses are
14 /// initiated by CF_ALU instructions.
15 //===----------------------------------------------------------------------===//
18 #include "R600Defines.h"
19 #include "R600InstrInfo.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 class R600EmitClauseMarkersPass : public MachineFunctionPass {
34 const R600InstrInfo *TII;
37 unsigned OccupiedDwords(MachineInstr *MI) const {
38 switch (MI->getOpcode()) {
39 case AMDGPU::INTERP_PAIR_XY:
40 case AMDGPU::INTERP_PAIR_ZW:
41 case AMDGPU::INTERP_VEC_LOAD:
50 if(TII->isVector(*MI) ||
51 TII->isCubeOp(MI->getOpcode()) ||
52 TII->isReductionOp(MI->getOpcode()))
55 unsigned NumLiteral = 0;
56 for (MachineInstr::mop_iterator It = MI->operands_begin(),
57 E = MI->operands_end(); It != E; ++It) {
58 MachineOperand &MO = *It;
59 if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X)
62 return 1 + NumLiteral;
65 bool isALU(const MachineInstr *MI) const {
66 if (TII->isALUInstr(MI->getOpcode()))
68 if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode()))
70 switch (MI->getOpcode()) {
72 case AMDGPU::INTERP_PAIR_XY:
73 case AMDGPU::INTERP_PAIR_ZW:
74 case AMDGPU::INTERP_VEC_LOAD:
83 bool IsTrivialInst(MachineInstr *MI) const {
84 switch (MI->getOpcode()) {
87 case AMDGPU::IMPLICIT_DEF:
94 std::pair<unsigned, unsigned> getAccessedBankLine(unsigned Sel) const {
95 // Sel is (512 + (kc_bank << 12) + ConstIndex) << 2
96 // (See also R600ISelLowering.cpp)
97 // ConstIndex value is in [0, 4095];
98 return std::pair<unsigned, unsigned>(
99 ((Sel >> 2) - 512) >> 12, // KC_BANK
100 // Line Number of ConstIndex
101 // A line contains 16 constant registers however KCX bank can lock
102 // two line at the same time ; thus we want to get an even line number.
103 // Line number can be retrieved with (>>4), using (>>5) <<1 generates
105 ((((Sel >> 2) - 512) & 4095) >> 5) << 1);
108 bool SubstituteKCacheBank(MachineInstr *MI,
109 std::vector<std::pair<unsigned, unsigned> > &CachedConsts) const {
110 std::vector<std::pair<unsigned, unsigned> > UsedKCache;
111 const SmallVectorImpl<std::pair<MachineOperand *, int64_t> > &Consts =
113 assert((TII->isALUInstr(MI->getOpcode()) ||
114 MI->getOpcode() == AMDGPU::DOT_4) && "Can't assign Const");
115 for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
116 if (Consts[i].first->getReg() != AMDGPU::ALU_CONST)
118 unsigned Sel = Consts[i].second;
119 unsigned Chan = Sel & 3, Index = ((Sel >> 2) - 512) & 31;
120 unsigned KCacheIndex = Index * 4 + Chan;
121 const std::pair<unsigned, unsigned> &BankLine = getAccessedBankLine(Sel);
122 if (CachedConsts.empty()) {
123 CachedConsts.push_back(BankLine);
124 UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
127 if (CachedConsts[0] == BankLine) {
128 UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
131 if (CachedConsts.size() == 1) {
132 CachedConsts.push_back(BankLine);
133 UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
136 if (CachedConsts[1] == BankLine) {
137 UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
143 for (unsigned i = 0, j = 0, n = Consts.size(); i < n; ++i) {
144 if (Consts[i].first->getReg() != AMDGPU::ALU_CONST)
146 switch(UsedKCache[j].first) {
148 Consts[i].first->setReg(
149 AMDGPU::R600_KC0RegClass.getRegister(UsedKCache[j].second));
152 Consts[i].first->setReg(
153 AMDGPU::R600_KC1RegClass.getRegister(UsedKCache[j].second));
156 llvm_unreachable("Wrong Cache Line");
163 MachineBasicBlock::iterator
164 MakeALUClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) {
165 MachineBasicBlock::iterator ClauseHead = I;
166 std::vector<std::pair<unsigned, unsigned> > KCacheBanks;
167 bool PushBeforeModifier = false;
168 unsigned AluInstCount = 0;
169 for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
170 if (IsTrivialInst(I))
174 if (AluInstCount > TII->getMaxAlusPerClause())
176 if (I->getOpcode() == AMDGPU::PRED_X) {
177 // We put PRED_X in its own clause to ensure that ifcvt won't create
178 // clauses with more than 128 insts.
179 // IfCvt is indeed checking that "then" and "else" branches of an if
180 // statement have less than ~60 insts thus converted clauses can't be
181 // bigger than ~121 insts (predicate setter needs to be in the same
182 // clause as predicated alus).
183 if (AluInstCount > 0)
185 if (TII->getFlagOp(I).getImm() & MO_FLAG_PUSH)
186 PushBeforeModifier = true;
190 // XXX: GROUP_BARRIER instructions cannot be in the same ALU clause as:
192 // * KILL or INTERP instructions
193 // * Any instruction that sets UPDATE_EXEC_MASK or UPDATE_PRED bits
194 // * Uses waterfalling (i.e. INDEX_MODE = AR.X)
196 // XXX: These checks have not been implemented yet.
197 if (TII->mustBeLastInClause(I->getOpcode())) {
201 if (TII->isALUInstr(I->getOpcode()) &&
202 !SubstituteKCacheBank(I, KCacheBanks))
204 if (I->getOpcode() == AMDGPU::DOT_4 &&
205 !SubstituteKCacheBank(I, KCacheBanks))
207 AluInstCount += OccupiedDwords(I);
209 unsigned Opcode = PushBeforeModifier ?
210 AMDGPU::CF_ALU_PUSH_BEFORE : AMDGPU::CF_ALU;
211 BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), TII->get(Opcode))
212 // We don't use the ADDR field until R600ControlFlowFinalizer pass, where
213 // it is safe to assume it is 0. However if we always put 0 here, the ifcvt
214 // pass may assume that identical ALU clause starter at the beginning of a
215 // true and false branch can be factorized which is not the case.
216 .addImm(Address++) // ADDR
217 .addImm(KCacheBanks.empty()?0:KCacheBanks[0].first) // KB0
218 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].first) // KB1
219 .addImm(KCacheBanks.empty()?0:2) // KM0
220 .addImm((KCacheBanks.size() < 2)?0:2) // KM1
221 .addImm(KCacheBanks.empty()?0:KCacheBanks[0].second) // KLINE0
222 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].second) // KLINE1
223 .addImm(AluInstCount) // COUNT
224 .addImm(1); // Enabled
229 R600EmitClauseMarkersPass(TargetMachine &tm) : MachineFunctionPass(ID),
230 TII(0), Address(0) { }
232 virtual bool runOnMachineFunction(MachineFunction &MF) {
233 TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
235 for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
237 MachineBasicBlock &MBB = *BB;
238 MachineBasicBlock::iterator I = MBB.begin();
239 if (I->getOpcode() == AMDGPU::CF_ALU)
240 continue; // BB was already parsed
241 for (MachineBasicBlock::iterator E = MBB.end(); I != E;) {
243 I = MakeALUClause(MBB, I);
251 const char *getPassName() const {
252 return "R600 Emit Clause Markers Pass";
256 char R600EmitClauseMarkersPass::ID = 0;
258 } // end anonymous namespace
261 llvm::FunctionPass *llvm::createR600EmitClauseMarkers(TargetMachine &TM) {
262 return new R600EmitClauseMarkersPass(TM);