1 //===-- R600EmitClauseMarkers.cpp - Emit CF_ALU ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// Add CF_ALU. R600 Alu instructions are grouped in clause which can hold
12 /// 128 Alu instructions ; these instructions can access up to 4 prefetched
13 /// 4 lines of 16 registers from constant buffers. Such ALU clauses are
14 /// initiated by CF_ALU instructions.
15 //===----------------------------------------------------------------------===//
18 #include "R600Defines.h"
19 #include "R600InstrInfo.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 class R600EmitClauseMarkersPass : public MachineFunctionPass {
34 const R600InstrInfo *TII;
37 unsigned OccupiedDwords(MachineInstr *MI) const {
38 switch (MI->getOpcode()) {
39 case AMDGPU::INTERP_PAIR_XY:
40 case AMDGPU::INTERP_PAIR_ZW:
41 case AMDGPU::INTERP_VEC_LOAD:
50 if(TII->isVector(*MI) ||
51 TII->isCubeOp(MI->getOpcode()) ||
52 TII->isReductionOp(MI->getOpcode()))
55 unsigned NumLiteral = 0;
56 for (MachineInstr::mop_iterator It = MI->operands_begin(),
57 E = MI->operands_end(); It != E; ++It) {
58 MachineOperand &MO = *It;
59 if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X)
62 return 1 + NumLiteral;
65 bool isALU(const MachineInstr *MI) const {
66 if (TII->isALUInstr(MI->getOpcode()))
68 if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode()))
70 switch (MI->getOpcode()) {
72 case AMDGPU::INTERP_PAIR_XY:
73 case AMDGPU::INTERP_PAIR_ZW:
74 case AMDGPU::INTERP_VEC_LOAD:
83 bool IsTrivialInst(MachineInstr *MI) const {
84 switch (MI->getOpcode()) {
93 std::pair<unsigned, unsigned> getAccessedBankLine(unsigned Sel) const {
94 // Sel is (512 + (kc_bank << 12) + ConstIndex) << 2
95 // (See also R600ISelLowering.cpp)
96 // ConstIndex value is in [0, 4095];
97 return std::pair<unsigned, unsigned>(
98 ((Sel >> 2) - 512) >> 12, // KC_BANK
99 // Line Number of ConstIndex
100 // A line contains 16 constant registers however KCX bank can lock
101 // two line at the same time ; thus we want to get an even line number.
102 // Line number can be retrieved with (>>4), using (>>5) <<1 generates
104 ((((Sel >> 2) - 512) & 4095) >> 5) << 1);
107 bool SubstituteKCacheBank(MachineInstr *MI,
108 std::vector<std::pair<unsigned, unsigned> > &CachedConsts) const {
109 std::vector<std::pair<unsigned, unsigned> > UsedKCache;
110 const SmallVector<std::pair<MachineOperand *, int64_t>, 3> &Consts =
112 assert((TII->isALUInstr(MI->getOpcode()) ||
113 MI->getOpcode() == AMDGPU::DOT_4) && "Can't assign Const");
114 for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
115 if (Consts[i].first->getReg() != AMDGPU::ALU_CONST)
117 unsigned Sel = Consts[i].second;
118 unsigned Chan = Sel & 3, Index = ((Sel >> 2) - 512) & 31;
119 unsigned KCacheIndex = Index * 4 + Chan;
120 const std::pair<unsigned, unsigned> &BankLine = getAccessedBankLine(Sel);
121 if (CachedConsts.empty()) {
122 CachedConsts.push_back(BankLine);
123 UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
126 if (CachedConsts[0] == BankLine) {
127 UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
130 if (CachedConsts.size() == 1) {
131 CachedConsts.push_back(BankLine);
132 UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
135 if (CachedConsts[1] == BankLine) {
136 UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
142 for (unsigned i = 0, j = 0, n = Consts.size(); i < n; ++i) {
143 if (Consts[i].first->getReg() != AMDGPU::ALU_CONST)
145 switch(UsedKCache[j].first) {
147 Consts[i].first->setReg(
148 AMDGPU::R600_KC0RegClass.getRegister(UsedKCache[j].second));
151 Consts[i].first->setReg(
152 AMDGPU::R600_KC1RegClass.getRegister(UsedKCache[j].second));
155 llvm_unreachable("Wrong Cache Line");
162 MachineBasicBlock::iterator
163 MakeALUClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) {
164 MachineBasicBlock::iterator ClauseHead = I;
165 std::vector<std::pair<unsigned, unsigned> > KCacheBanks;
166 bool PushBeforeModifier = false;
167 unsigned AluInstCount = 0;
168 for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
169 if (IsTrivialInst(I))
173 if (AluInstCount > TII->getMaxAlusPerClause())
175 if (I->getOpcode() == AMDGPU::PRED_X) {
176 if (TII->getFlagOp(I).getImm() & MO_FLAG_PUSH)
177 PushBeforeModifier = true;
181 // XXX: GROUP_BARRIER instructions cannot be in the same ALU clause as:
183 // * KILL or INTERP instructions
184 // * Any instruction that sets UPDATE_EXEC_MASK or UPDATE_PRED bits
185 // * Uses waterfalling (i.e. INDEX_MODE = AR.X)
187 // XXX: These checks have not been implemented yet.
188 if (TII->mustBeLastInClause(I->getOpcode())) {
192 if (TII->isALUInstr(I->getOpcode()) &&
193 !SubstituteKCacheBank(I, KCacheBanks))
195 if (I->getOpcode() == AMDGPU::DOT_4 &&
196 !SubstituteKCacheBank(I, KCacheBanks))
198 AluInstCount += OccupiedDwords(I);
200 unsigned Opcode = PushBeforeModifier ?
201 AMDGPU::CF_ALU_PUSH_BEFORE : AMDGPU::CF_ALU;
202 BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), TII->get(Opcode))
203 // We don't use the ADDR field until R600ControlFlowFinalizer pass, where
204 // it is safe to assume it is 0. However if we always put 0 here, the ifcvt
205 // pass may assume that identical ALU clause starter at the beginning of a
206 // true and false branch can be factorized which is not the case.
207 .addImm(Address++) // ADDR
208 .addImm(KCacheBanks.empty()?0:KCacheBanks[0].first) // KB0
209 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].first) // KB1
210 .addImm(KCacheBanks.empty()?0:2) // KM0
211 .addImm((KCacheBanks.size() < 2)?0:2) // KM1
212 .addImm(KCacheBanks.empty()?0:KCacheBanks[0].second) // KLINE0
213 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].second) // KLINE1
214 .addImm(AluInstCount) // COUNT
215 .addImm(1); // Enabled
220 R600EmitClauseMarkersPass(TargetMachine &tm) : MachineFunctionPass(ID),
221 TII(0), Address(0) { }
223 virtual bool runOnMachineFunction(MachineFunction &MF) {
224 TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
226 for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
228 MachineBasicBlock &MBB = *BB;
229 MachineBasicBlock::iterator I = MBB.begin();
230 if (I->getOpcode() == AMDGPU::CF_ALU)
231 continue; // BB was already parsed
232 for (MachineBasicBlock::iterator E = MBB.end(); I != E;) {
234 I = MakeALUClause(MBB, I);
242 const char *getPassName() const {
243 return "R600 Emit Clause Markers Pass";
247 char R600EmitClauseMarkersPass::ID = 0;
249 } // end anonymous namespace
252 llvm::FunctionPass *llvm::createR600EmitClauseMarkers(TargetMachine &TM) {
253 return new R600EmitClauseMarkersPass(TM);