1 //===-- R600EmitClauseMarkers.cpp - Emit CF_ALU ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// Add CF_ALU. R600 Alu instructions are grouped in clause which can hold
12 /// 128 Alu instructions ; these instructions can access up to 4 prefetched
13 /// 4 lines of 16 registers from constant buffers. Such ALU clauses are
14 /// initiated by CF_ALU instructions.
15 //===----------------------------------------------------------------------===//
18 #include "R600Defines.h"
19 #include "R600InstrInfo.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 class R600EmitClauseMarkersPass : public MachineFunctionPass {
34 const R600InstrInfo *TII;
36 unsigned OccupiedDwords(MachineInstr *MI) const {
37 switch (MI->getOpcode()) {
38 case AMDGPU::INTERP_PAIR_XY:
39 case AMDGPU::INTERP_PAIR_ZW:
40 case AMDGPU::INTERP_VEC_LOAD:
49 if(TII->isVector(*MI) ||
50 TII->isCubeOp(MI->getOpcode()) ||
51 TII->isReductionOp(MI->getOpcode()))
54 unsigned NumLiteral = 0;
55 for (MachineInstr::mop_iterator It = MI->operands_begin(),
56 E = MI->operands_end(); It != E; ++It) {
57 MachineOperand &MO = *It;
58 if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X)
61 return 1 + NumLiteral;
64 bool isALU(const MachineInstr *MI) const {
65 if (TII->isALUInstr(MI->getOpcode()))
67 if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode()))
69 switch (MI->getOpcode()) {
71 case AMDGPU::INTERP_PAIR_XY:
72 case AMDGPU::INTERP_PAIR_ZW:
73 case AMDGPU::INTERP_VEC_LOAD:
82 bool IsTrivialInst(MachineInstr *MI) const {
83 switch (MI->getOpcode()) {
92 std::pair<unsigned, unsigned> getAccessedBankLine(unsigned Sel) const {
93 // Sel is (512 + (kc_bank << 12) + ConstIndex) << 2
94 // (See also R600ISelLowering.cpp)
95 // ConstIndex value is in [0, 4095];
96 return std::pair<unsigned, unsigned>(
97 ((Sel >> 2) - 512) >> 12, // KC_BANK
98 // Line Number of ConstIndex
99 // A line contains 16 constant registers however KCX bank can lock
100 // two line at the same time ; thus we want to get an even line number.
101 // Line number can be retrieved with (>>4), using (>>5) <<1 generates
103 ((((Sel >> 2) - 512) & 4095) >> 5) << 1);
106 bool SubstituteKCacheBank(MachineInstr *MI,
107 std::vector<std::pair<unsigned, unsigned> > &CachedConsts) const {
108 std::vector<std::pair<unsigned, unsigned> > UsedKCache;
109 const SmallVector<std::pair<MachineOperand *, int64_t>, 3> &Consts =
111 assert((TII->isALUInstr(MI->getOpcode()) ||
112 MI->getOpcode() == AMDGPU::DOT_4) && "Can't assign Const");
113 for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
114 if (Consts[i].first->getReg() != AMDGPU::ALU_CONST)
116 unsigned Sel = Consts[i].second;
117 unsigned Chan = Sel & 3, Index = ((Sel >> 2) - 512) & 31;
118 unsigned KCacheIndex = Index * 4 + Chan;
119 const std::pair<unsigned, unsigned> &BankLine = getAccessedBankLine(Sel);
120 if (CachedConsts.empty()) {
121 CachedConsts.push_back(BankLine);
122 UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
125 if (CachedConsts[0] == BankLine) {
126 UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
129 if (CachedConsts.size() == 1) {
130 CachedConsts.push_back(BankLine);
131 UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
134 if (CachedConsts[1] == BankLine) {
135 UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
141 for (unsigned i = 0, j = 0, n = Consts.size(); i < n; ++i) {
142 if (Consts[i].first->getReg() != AMDGPU::ALU_CONST)
144 switch(UsedKCache[j].first) {
146 Consts[i].first->setReg(
147 AMDGPU::R600_KC0RegClass.getRegister(UsedKCache[j].second));
150 Consts[i].first->setReg(
151 AMDGPU::R600_KC1RegClass.getRegister(UsedKCache[j].second));
154 llvm_unreachable("Wrong Cache Line");
161 MachineBasicBlock::iterator
162 MakeALUClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const {
163 MachineBasicBlock::iterator ClauseHead = I;
164 std::vector<std::pair<unsigned, unsigned> > KCacheBanks;
165 bool PushBeforeModifier = false;
166 unsigned AluInstCount = 0;
167 for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
168 if (IsTrivialInst(I))
172 if (AluInstCount > TII->getMaxAlusPerClause())
174 if (I->getOpcode() == AMDGPU::PRED_X) {
175 if (TII->getFlagOp(I).getImm() & MO_FLAG_PUSH)
176 PushBeforeModifier = true;
180 if (I->getOpcode() == AMDGPU::KILLGT) {
184 if (TII->isALUInstr(I->getOpcode()) &&
185 !SubstituteKCacheBank(I, KCacheBanks))
187 if (I->getOpcode() == AMDGPU::DOT_4 &&
188 !SubstituteKCacheBank(I, KCacheBanks))
190 AluInstCount += OccupiedDwords(I);
192 unsigned Opcode = PushBeforeModifier ?
193 AMDGPU::CF_ALU_PUSH_BEFORE : AMDGPU::CF_ALU;
194 BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), TII->get(Opcode))
196 .addImm(KCacheBanks.empty()?0:KCacheBanks[0].first) // KB0
197 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].first) // KB1
198 .addImm(KCacheBanks.empty()?0:2) // KM0
199 .addImm((KCacheBanks.size() < 2)?0:2) // KM1
200 .addImm(KCacheBanks.empty()?0:KCacheBanks[0].second) // KLINE0
201 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].second) // KLINE1
202 .addImm(AluInstCount); // COUNT
207 R600EmitClauseMarkersPass(TargetMachine &tm) : MachineFunctionPass(ID),
210 virtual bool runOnMachineFunction(MachineFunction &MF) {
211 TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
213 for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
215 MachineBasicBlock &MBB = *BB;
216 MachineBasicBlock::iterator I = MBB.begin();
217 if (I->getOpcode() == AMDGPU::CF_ALU)
218 continue; // BB was already parsed
219 for (MachineBasicBlock::iterator E = MBB.end(); I != E;) {
221 I = MakeALUClause(MBB, I);
229 const char *getPassName() const {
230 return "R600 Emit Clause Markers Pass";
234 char R600EmitClauseMarkersPass::ID = 0;
236 } // end anonymous namespace
239 llvm::FunctionPass *llvm::createR600EmitClauseMarkers(TargetMachine &TM) {
240 return new R600EmitClauseMarkersPass(TM);