1 //===-- R600ExpandSpecialInstrs.cpp - Expand special instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// Vector, Reduction, and Cube instructions need to fill the entire instruction
12 /// group to work correctly. This pass expands these individual instructions
13 /// into several instructions that will completely fill the instruction group.
15 //===----------------------------------------------------------------------===//
18 #include "R600Defines.h"
19 #include "R600InstrInfo.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 class R600ExpandSpecialInstrsPass : public MachineFunctionPass {
34 const R600InstrInfo *TII;
36 bool ExpandInputPerspective(MachineInstr& MI);
37 bool ExpandInputConstant(MachineInstr& MI);
40 R600ExpandSpecialInstrsPass(TargetMachine &tm) : MachineFunctionPass(ID),
41 TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) { }
43 virtual bool runOnMachineFunction(MachineFunction &MF);
45 const char *getPassName() const {
46 return "R600 Expand special instructions pass";
50 } // End anonymous namespace
52 char R600ExpandSpecialInstrsPass::ID = 0;
54 FunctionPass *llvm::createR600ExpandSpecialInstrsPass(TargetMachine &TM) {
55 return new R600ExpandSpecialInstrsPass(TM);
58 bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
60 const R600RegisterInfo &TRI = TII->getRegisterInfo();
62 for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
64 MachineBasicBlock &MBB = *BB;
65 MachineBasicBlock::iterator I = MBB.begin();
66 while (I != MBB.end()) {
67 MachineInstr &MI = *I;
70 switch (MI.getOpcode()) {
72 // Expand PRED_X to one of the PRED_SET instructions.
73 case AMDGPU::PRED_X: {
74 uint64_t Flags = MI.getOperand(3).getImm();
75 // The native opcode used by PRED_X is stored as an immediate in the
77 MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I,
78 MI.getOperand(2).getImm(), // opcode
79 MI.getOperand(0).getReg(), // dst
80 MI.getOperand(1).getReg(), // src0
81 AMDGPU::ZERO); // src1
82 TII->addFlag(PredSet, 0, MO_FLAG_MASK);
83 if (Flags & MO_FLAG_PUSH) {
84 TII->setImmOperand(PredSet, R600Operands::UPDATE_EXEC_MASK, 1);
86 TII->setImmOperand(PredSet, R600Operands::UPDATE_PREDICATE, 1);
92 MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I,
93 AMDGPU::PRED_SETE_INT,
94 AMDGPU::PREDICATE_BIT,
97 TII->addFlag(PredSet, 0, MO_FLAG_MASK);
98 TII->setImmOperand(PredSet, R600Operands::UPDATE_EXEC_MASK, 1);
100 BuildMI(MBB, I, MBB.findDebugLoc(I),
101 TII->get(AMDGPU::PREDICATED_BREAK))
102 .addReg(AMDGPU::PREDICATE_BIT);
103 MI.eraseFromParent();
107 case AMDGPU::INTERP_PAIR_XY: {
109 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
110 MI.getOperand(2).getImm());
112 for (unsigned Chan = 0; Chan < 4; ++Chan) {
116 DstReg = MI.getOperand(Chan).getReg();
118 DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W;
120 BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_XY,
121 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
124 BMI->bundleWithPred();
127 TII->addFlag(BMI, 0, MO_FLAG_MASK);
129 TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
132 MI.eraseFromParent();
136 case AMDGPU::INTERP_PAIR_ZW: {
138 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
139 MI.getOperand(2).getImm());
141 for (unsigned Chan = 0; Chan < 4; ++Chan) {
145 DstReg = Chan == 0 ? AMDGPU::T0_X : AMDGPU::T0_Y;
147 DstReg = MI.getOperand(Chan-2).getReg();
149 BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_ZW,
150 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg);
153 BMI->bundleWithPred();
156 TII->addFlag(BMI, 0, MO_FLAG_MASK);
158 TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
161 MI.eraseFromParent();
165 case AMDGPU::INTERP_VEC_LOAD: {
166 const R600RegisterInfo &TRI = TII->getRegisterInfo();
168 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
169 MI.getOperand(1).getImm());
170 unsigned DstReg = MI.getOperand(0).getReg();
172 for (unsigned Chan = 0; Chan < 4; ++Chan) {
173 BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_LOAD_P0,
174 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg);
176 BMI->bundleWithPred();
179 TII->addFlag(BMI, 0, MO_FLAG_NOT_LAST);
182 MI.eraseFromParent();
187 bool IsReduction = TII->isReductionOp(MI.getOpcode());
188 bool IsVector = TII->isVector(MI);
189 bool IsCube = TII->isCubeOp(MI.getOpcode());
190 if (!IsReduction && !IsVector && !IsCube) {
194 // Expand the instruction
196 // Reduction instructions:
197 // T0_X = DP4 T1_XYZW, T2_XYZW
199 // TO_X = DP4 T1_X, T2_X
200 // TO_Y (write masked) = DP4 T1_Y, T2_Y
201 // TO_Z (write masked) = DP4 T1_Z, T2_Z
202 // TO_W (write masked) = DP4 T1_W, T2_W
204 // Vector instructions:
205 // T0_X = MULLO_INT T1_X, T2_X
207 // T0_X = MULLO_INT T1_X, T2_X
208 // T0_Y (write masked) = MULLO_INT T1_X, T2_X
209 // T0_Z (write masked) = MULLO_INT T1_X, T2_X
210 // T0_W (write masked) = MULLO_INT T1_X, T2_X
212 // Cube instructions:
213 // T0_XYZW = CUBE T1_XYZW
215 // TO_X = CUBE T1_Z, T1_Y
216 // T0_Y = CUBE T1_Z, T1_X
217 // T0_Z = CUBE T1_X, T1_Z
218 // T0_W = CUBE T1_Y, T1_Z
219 for (unsigned Chan = 0; Chan < 4; Chan++) {
220 unsigned DstReg = MI.getOperand(
221 TII->getOperandIdx(MI, R600Operands::DST)).getReg();
222 unsigned Src0 = MI.getOperand(
223 TII->getOperandIdx(MI, R600Operands::SRC0)).getReg();
226 // Determine the correct source registers
228 int Src1Idx = TII->getOperandIdx(MI, R600Operands::SRC1);
230 Src1 = MI.getOperand(Src1Idx).getReg();
234 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
235 Src0 = TRI.getSubReg(Src0, SubRegIndex);
236 Src1 = TRI.getSubReg(Src1, SubRegIndex);
238 static const int CubeSrcSwz[] = {2, 2, 0, 1};
239 unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]);
240 unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]);
241 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
242 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
245 // Determine the correct destination registers;
249 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
250 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
252 // Mask the write if the original instruction does not write to
253 // the current Channel.
254 Mask = (Chan != TRI.getHWRegChan(DstReg));
255 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
256 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
259 // Set the IsLast bit
260 NotLast = (Chan != 3 );
262 // Add the new instruction
263 unsigned Opcode = MI.getOpcode();
265 case AMDGPU::CUBE_r600_pseudo:
266 Opcode = AMDGPU::CUBE_r600_real;
268 case AMDGPU::CUBE_eg_pseudo:
269 Opcode = AMDGPU::CUBE_eg_real;
271 case AMDGPU::DOT4_r600_pseudo:
272 Opcode = AMDGPU::DOT4_r600_real;
274 case AMDGPU::DOT4_eg_pseudo:
275 Opcode = AMDGPU::DOT4_eg_real;
281 MachineInstr *NewMI =
282 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
285 NewMI->bundleWithPred();
287 TII->addFlag(NewMI, 0, MO_FLAG_MASK);
290 TII->addFlag(NewMI, 0, MO_FLAG_NOT_LAST);
293 MI.eraseFromParent();