1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for R600
13 //===----------------------------------------------------------------------===//
15 #include "R600ISelLowering.h"
16 #include "AMDGPUFrameLowering.h"
17 #include "AMDGPUIntrinsicInfo.h"
18 #include "AMDGPUSubtarget.h"
19 #include "R600Defines.h"
20 #include "R600InstrInfo.h"
21 #include "R600MachineFunctionInfo.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/IR/Argument.h"
29 #include "llvm/IR/Function.h"
33 R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
34 AMDGPUTargetLowering(TM),
35 Gen(TM.getSubtarget<AMDGPUSubtarget>().getGeneration()) {
36 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
37 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
38 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
39 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
40 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
41 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
43 computeRegisterProperties();
45 // Set condition code actions
46 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
47 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
48 setCondCodeAction(ISD::SETLT, MVT::f32, Expand);
49 setCondCodeAction(ISD::SETLE, MVT::f32, Expand);
50 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
51 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
52 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
53 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
54 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
55 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
56 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
57 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
59 setCondCodeAction(ISD::SETLE, MVT::i32, Expand);
60 setCondCodeAction(ISD::SETLT, MVT::i32, Expand);
61 setCondCodeAction(ISD::SETULE, MVT::i32, Expand);
62 setCondCodeAction(ISD::SETULT, MVT::i32, Expand);
64 setOperationAction(ISD::FCOS, MVT::f32, Custom);
65 setOperationAction(ISD::FSIN, MVT::f32, Custom);
67 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
68 setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
70 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
71 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
72 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
74 setOperationAction(ISD::FSUB, MVT::f32, Expand);
76 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
77 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
78 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
80 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
81 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
83 setOperationAction(ISD::SETCC, MVT::i32, Expand);
84 setOperationAction(ISD::SETCC, MVT::f32, Expand);
85 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
86 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
87 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
89 setOperationAction(ISD::SELECT, MVT::i32, Expand);
90 setOperationAction(ISD::SELECT, MVT::f32, Expand);
91 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
92 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
94 // Expand sign extension of vectors
95 if (!Subtarget->hasBFE())
96 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
98 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand);
99 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand);
101 if (!Subtarget->hasBFE())
102 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
103 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand);
104 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand);
106 if (!Subtarget->hasBFE())
107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
108 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand);
109 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
111 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand);
113 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand);
115 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
118 // Legalize loads and stores to the private address space.
119 setOperationAction(ISD::LOAD, MVT::i32, Custom);
120 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
121 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
123 // EXTLOAD should be the same as ZEXTLOAD. It is legal for some address
124 // spaces, so it is custom lowered to handle those where it isn't.
125 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
126 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
127 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
128 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
129 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
130 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Custom);
132 setOperationAction(ISD::STORE, MVT::i8, Custom);
133 setOperationAction(ISD::STORE, MVT::i32, Custom);
134 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
135 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
136 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
137 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
139 setOperationAction(ISD::LOAD, MVT::i32, Custom);
140 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
141 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
143 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom);
144 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom);
145 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
146 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
148 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom);
149 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom);
150 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
151 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
153 setTargetDAGCombine(ISD::FP_ROUND);
154 setTargetDAGCombine(ISD::FP_TO_SINT);
155 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
156 setTargetDAGCombine(ISD::SELECT_CC);
157 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
159 setOperationAction(ISD::SUB, MVT::i64, Expand);
161 // These should be replaced by UDVIREM, but it does not happen automatically
162 // during Type Legalization
163 setOperationAction(ISD::UDIV, MVT::i64, Custom);
164 setOperationAction(ISD::UREM, MVT::i64, Custom);
165 setOperationAction(ISD::SDIV, MVT::i64, Custom);
166 setOperationAction(ISD::SREM, MVT::i64, Custom);
168 // We don't have 64-bit shifts. Thus we need either SHX i64 or SHX_PARTS i32
169 // to be Legal/Custom in order to avoid library calls.
170 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
171 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
172 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
174 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
176 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
177 for (MVT VT : ScalarIntVTs) {
178 setOperationAction(ISD::ADDC, VT, Expand);
179 setOperationAction(ISD::SUBC, VT, Expand);
180 setOperationAction(ISD::ADDE, VT, Expand);
181 setOperationAction(ISD::SUBE, VT, Expand);
184 setBooleanContents(ZeroOrNegativeOneBooleanContent);
185 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
186 setSchedulingPreference(Sched::Source);
189 MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
190 MachineInstr * MI, MachineBasicBlock * BB) const {
191 MachineFunction * MF = BB->getParent();
192 MachineRegisterInfo &MRI = MF->getRegInfo();
193 MachineBasicBlock::iterator I = *MI;
194 const R600InstrInfo *TII =
195 static_cast<const R600InstrInfo *>(MF->getSubtarget().getInstrInfo());
197 switch (MI->getOpcode()) {
199 // Replace LDS_*_RET instruction that don't have any uses with the
200 // equivalent LDS_*_NORET instruction.
201 if (TII->isLDSRetInstr(MI->getOpcode())) {
202 int DstIdx = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
203 assert(DstIdx != -1);
204 MachineInstrBuilder NewMI;
205 if (!MRI.use_empty(MI->getOperand(DstIdx).getReg()))
208 NewMI = BuildMI(*BB, I, BB->findDebugLoc(I),
209 TII->get(AMDGPU::getLDSNoRetOp(MI->getOpcode())));
210 for (unsigned i = 1, e = MI->getNumOperands(); i < e; ++i) {
211 NewMI.addOperand(MI->getOperand(i));
214 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
217 case AMDGPU::CLAMP_R600: {
218 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
220 MI->getOperand(0).getReg(),
221 MI->getOperand(1).getReg());
222 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
226 case AMDGPU::FABS_R600: {
227 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
229 MI->getOperand(0).getReg(),
230 MI->getOperand(1).getReg());
231 TII->addFlag(NewMI, 0, MO_FLAG_ABS);
235 case AMDGPU::FNEG_R600: {
236 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
238 MI->getOperand(0).getReg(),
239 MI->getOperand(1).getReg());
240 TII->addFlag(NewMI, 0, MO_FLAG_NEG);
244 case AMDGPU::MASK_WRITE: {
245 unsigned maskedRegister = MI->getOperand(0).getReg();
246 assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
247 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
248 TII->addFlag(defInstr, 0, MO_FLAG_MASK);
252 case AMDGPU::MOV_IMM_F32:
253 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
254 MI->getOperand(1).getFPImm()->getValueAPF()
255 .bitcastToAPInt().getZExtValue());
257 case AMDGPU::MOV_IMM_I32:
258 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
259 MI->getOperand(1).getImm());
261 case AMDGPU::CONST_COPY: {
262 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
263 MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
264 TII->setImmOperand(NewMI, AMDGPU::OpName::src0_sel,
265 MI->getOperand(1).getImm());
269 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
270 case AMDGPU::RAT_WRITE_CACHELESS_64_eg:
271 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
272 unsigned EOP = (std::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
274 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
275 .addOperand(MI->getOperand(0))
276 .addOperand(MI->getOperand(1))
277 .addImm(EOP); // Set End of program bit
282 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
283 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
284 MachineOperand &RID = MI->getOperand(4);
285 MachineOperand &SID = MI->getOperand(5);
286 unsigned TextureId = MI->getOperand(6).getImm();
287 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
288 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
300 case 8: // ShadowRect
311 case 11: // Shadow1DArray
315 case 12: // Shadow2DArray
319 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
320 .addOperand(MI->getOperand(3))
338 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
339 .addOperand(MI->getOperand(2))
357 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
358 .addOperand(MI->getOperand(0))
359 .addOperand(MI->getOperand(1))
377 .addReg(T0, RegState::Implicit)
378 .addReg(T1, RegState::Implicit);
382 case AMDGPU::TXD_SHADOW: {
383 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
384 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
385 MachineOperand &RID = MI->getOperand(4);
386 MachineOperand &SID = MI->getOperand(5);
387 unsigned TextureId = MI->getOperand(6).getImm();
388 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
389 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
401 case 8: // ShadowRect
412 case 11: // Shadow1DArray
416 case 12: // Shadow2DArray
421 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
422 .addOperand(MI->getOperand(3))
440 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
441 .addOperand(MI->getOperand(2))
459 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
460 .addOperand(MI->getOperand(0))
461 .addOperand(MI->getOperand(1))
479 .addReg(T0, RegState::Implicit)
480 .addReg(T1, RegState::Implicit);
485 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
486 .addOperand(MI->getOperand(0));
489 case AMDGPU::BRANCH_COND_f32: {
490 MachineInstr *NewMI =
491 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
492 AMDGPU::PREDICATE_BIT)
493 .addOperand(MI->getOperand(1))
494 .addImm(OPCODE_IS_NOT_ZERO)
496 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
497 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
498 .addOperand(MI->getOperand(0))
499 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
503 case AMDGPU::BRANCH_COND_i32: {
504 MachineInstr *NewMI =
505 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
506 AMDGPU::PREDICATE_BIT)
507 .addOperand(MI->getOperand(1))
508 .addImm(OPCODE_IS_NOT_ZERO_INT)
510 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
511 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
512 .addOperand(MI->getOperand(0))
513 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
517 case AMDGPU::EG_ExportSwz:
518 case AMDGPU::R600_ExportSwz: {
519 // Instruction is left unmodified if its not the last one of its type
520 bool isLastInstructionOfItsType = true;
521 unsigned InstExportType = MI->getOperand(1).getImm();
522 for (MachineBasicBlock::iterator NextExportInst = std::next(I),
523 EndBlock = BB->end(); NextExportInst != EndBlock;
524 NextExportInst = std::next(NextExportInst)) {
525 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
526 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
527 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
529 if (CurrentInstExportType == InstExportType) {
530 isLastInstructionOfItsType = false;
535 bool EOP = (std::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
536 if (!EOP && !isLastInstructionOfItsType)
538 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
539 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
540 .addOperand(MI->getOperand(0))
541 .addOperand(MI->getOperand(1))
542 .addOperand(MI->getOperand(2))
543 .addOperand(MI->getOperand(3))
544 .addOperand(MI->getOperand(4))
545 .addOperand(MI->getOperand(5))
546 .addOperand(MI->getOperand(6))
551 case AMDGPU::RETURN: {
552 // RETURN instructions must have the live-out registers as implicit uses,
553 // otherwise they appear dead.
554 R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
555 MachineInstrBuilder MIB(*MF, MI);
556 for (unsigned i = 0, e = MFI->LiveOuts.size(); i != e; ++i)
557 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
562 MI->eraseFromParent();
566 //===----------------------------------------------------------------------===//
567 // Custom DAG Lowering Operations
568 //===----------------------------------------------------------------------===//
570 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
571 MachineFunction &MF = DAG.getMachineFunction();
572 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
573 switch (Op.getOpcode()) {
574 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
575 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
576 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
577 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
579 case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG);
581 case ISD::FSIN: return LowerTrig(Op, DAG);
582 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
583 case ISD::STORE: return LowerSTORE(Op, DAG);
585 SDValue Result = LowerLOAD(Op, DAG);
586 assert((!Result.getNode() ||
587 Result.getNode()->getNumValues() == 2) &&
588 "Load should return a value and a chain");
592 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
593 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
594 case ISD::INTRINSIC_VOID: {
595 SDValue Chain = Op.getOperand(0);
596 unsigned IntrinsicID =
597 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
598 switch (IntrinsicID) {
599 case AMDGPUIntrinsic::AMDGPU_store_output: {
600 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
601 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
602 MFI->LiveOuts.push_back(Reg);
603 return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2));
605 case AMDGPUIntrinsic::R600_store_swizzle: {
606 const SDValue Args[8] = {
608 Op.getOperand(2), // Export Value
609 Op.getOperand(3), // ArrayBase
610 Op.getOperand(4), // Type
611 DAG.getConstant(0, MVT::i32), // SWZ_X
612 DAG.getConstant(1, MVT::i32), // SWZ_Y
613 DAG.getConstant(2, MVT::i32), // SWZ_Z
614 DAG.getConstant(3, MVT::i32) // SWZ_W
616 return DAG.getNode(AMDGPUISD::EXPORT, SDLoc(Op), Op.getValueType(), Args);
619 // default for switch(IntrinsicID)
622 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
625 case ISD::INTRINSIC_WO_CHAIN: {
626 unsigned IntrinsicID =
627 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
628 EVT VT = Op.getValueType();
630 switch(IntrinsicID) {
631 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
632 case AMDGPUIntrinsic::R600_load_input: {
633 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
634 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
635 MachineFunction &MF = DAG.getMachineFunction();
636 MachineRegisterInfo &MRI = MF.getRegInfo();
638 return DAG.getCopyFromReg(DAG.getEntryNode(),
639 SDLoc(DAG.getEntryNode()), Reg, VT);
642 case AMDGPUIntrinsic::R600_interp_input: {
643 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
644 int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
645 MachineSDNode *interp;
647 const MachineFunction &MF = DAG.getMachineFunction();
648 const R600InstrInfo *TII = static_cast<const R600InstrInfo *>(
649 MF.getSubtarget().getInstrInfo());
650 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
651 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
652 return DAG.getTargetExtractSubreg(
653 TII->getRegisterInfo().getSubRegFromChannel(slot % 4),
654 DL, MVT::f32, SDValue(interp, 0));
656 MachineFunction &MF = DAG.getMachineFunction();
657 MachineRegisterInfo &MRI = MF.getRegInfo();
658 unsigned RegisterI = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb);
659 unsigned RegisterJ = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1);
660 MRI.addLiveIn(RegisterI);
661 MRI.addLiveIn(RegisterJ);
662 SDValue RegisterINode = DAG.getCopyFromReg(DAG.getEntryNode(),
663 SDLoc(DAG.getEntryNode()), RegisterI, MVT::f32);
664 SDValue RegisterJNode = DAG.getCopyFromReg(DAG.getEntryNode(),
665 SDLoc(DAG.getEntryNode()), RegisterJ, MVT::f32);
668 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
669 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
670 RegisterJNode, RegisterINode);
672 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
673 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
674 RegisterJNode, RegisterINode);
675 return SDValue(interp, slot % 2);
677 case AMDGPUIntrinsic::R600_interp_xy:
678 case AMDGPUIntrinsic::R600_interp_zw: {
679 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
680 MachineSDNode *interp;
681 SDValue RegisterINode = Op.getOperand(2);
682 SDValue RegisterJNode = Op.getOperand(3);
684 if (IntrinsicID == AMDGPUIntrinsic::R600_interp_xy)
685 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
686 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, MVT::i32),
687 RegisterJNode, RegisterINode);
689 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
690 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, MVT::i32),
691 RegisterJNode, RegisterINode);
692 return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32,
693 SDValue(interp, 0), SDValue(interp, 1));
695 case AMDGPUIntrinsic::R600_tex:
696 case AMDGPUIntrinsic::R600_texc:
697 case AMDGPUIntrinsic::R600_txl:
698 case AMDGPUIntrinsic::R600_txlc:
699 case AMDGPUIntrinsic::R600_txb:
700 case AMDGPUIntrinsic::R600_txbc:
701 case AMDGPUIntrinsic::R600_txf:
702 case AMDGPUIntrinsic::R600_txq:
703 case AMDGPUIntrinsic::R600_ddx:
704 case AMDGPUIntrinsic::R600_ddy:
705 case AMDGPUIntrinsic::R600_ldptr: {
707 switch (IntrinsicID) {
708 case AMDGPUIntrinsic::R600_tex:
711 case AMDGPUIntrinsic::R600_texc:
714 case AMDGPUIntrinsic::R600_txl:
717 case AMDGPUIntrinsic::R600_txlc:
720 case AMDGPUIntrinsic::R600_txb:
723 case AMDGPUIntrinsic::R600_txbc:
726 case AMDGPUIntrinsic::R600_txf:
729 case AMDGPUIntrinsic::R600_txq:
732 case AMDGPUIntrinsic::R600_ddx:
735 case AMDGPUIntrinsic::R600_ddy:
738 case AMDGPUIntrinsic::R600_ldptr:
742 llvm_unreachable("Unknow Texture Operation");
745 SDValue TexArgs[19] = {
746 DAG.getConstant(TextureOp, MVT::i32),
748 DAG.getConstant(0, MVT::i32),
749 DAG.getConstant(1, MVT::i32),
750 DAG.getConstant(2, MVT::i32),
751 DAG.getConstant(3, MVT::i32),
755 DAG.getConstant(0, MVT::i32),
756 DAG.getConstant(1, MVT::i32),
757 DAG.getConstant(2, MVT::i32),
758 DAG.getConstant(3, MVT::i32),
766 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs);
768 case AMDGPUIntrinsic::AMDGPU_dp4: {
770 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
771 DAG.getConstant(0, MVT::i32)),
772 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
773 DAG.getConstant(0, MVT::i32)),
774 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
775 DAG.getConstant(1, MVT::i32)),
776 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
777 DAG.getConstant(1, MVT::i32)),
778 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
779 DAG.getConstant(2, MVT::i32)),
780 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
781 DAG.getConstant(2, MVT::i32)),
782 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
783 DAG.getConstant(3, MVT::i32)),
784 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
785 DAG.getConstant(3, MVT::i32))
787 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args);
790 case Intrinsic::r600_read_ngroups_x:
791 return LowerImplicitParameter(DAG, VT, DL, 0);
792 case Intrinsic::r600_read_ngroups_y:
793 return LowerImplicitParameter(DAG, VT, DL, 1);
794 case Intrinsic::r600_read_ngroups_z:
795 return LowerImplicitParameter(DAG, VT, DL, 2);
796 case Intrinsic::r600_read_global_size_x:
797 return LowerImplicitParameter(DAG, VT, DL, 3);
798 case Intrinsic::r600_read_global_size_y:
799 return LowerImplicitParameter(DAG, VT, DL, 4);
800 case Intrinsic::r600_read_global_size_z:
801 return LowerImplicitParameter(DAG, VT, DL, 5);
802 case Intrinsic::r600_read_local_size_x:
803 return LowerImplicitParameter(DAG, VT, DL, 6);
804 case Intrinsic::r600_read_local_size_y:
805 return LowerImplicitParameter(DAG, VT, DL, 7);
806 case Intrinsic::r600_read_local_size_z:
807 return LowerImplicitParameter(DAG, VT, DL, 8);
809 case Intrinsic::r600_read_tgid_x:
810 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
812 case Intrinsic::r600_read_tgid_y:
813 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
815 case Intrinsic::r600_read_tgid_z:
816 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
818 case Intrinsic::r600_read_tidig_x:
819 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
821 case Intrinsic::r600_read_tidig_y:
822 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
824 case Intrinsic::r600_read_tidig_z:
825 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
827 case Intrinsic::AMDGPU_rsq:
828 // XXX - I'm assuming SI's RSQ_LEGACY matches R600's behavior.
829 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
831 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
834 } // end switch(Op.getOpcode())
838 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
839 SmallVectorImpl<SDValue> &Results,
840 SelectionDAG &DAG) const {
841 switch (N->getOpcode()) {
843 AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG);
845 case ISD::FP_TO_UINT:
846 if (N->getValueType(0) == MVT::i1) {
847 Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
850 // Fall-through. Since we don't care about out of bounds values
851 // we can use FP_TO_SINT for uints too. The DAGLegalizer code for uint
852 // considers some extra cases which are not necessary here.
853 case ISD::FP_TO_SINT: {
855 if (expandFP_TO_SINT(N, Result, DAG))
856 Results.push_back(Result);
860 SDValue Op = SDValue(N, 0);
862 EVT VT = Op.getValueType();
863 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
864 N->getOperand(0), N->getOperand(1));
865 Results.push_back(UDIVREM);
869 SDValue Op = SDValue(N, 0);
871 EVT VT = Op.getValueType();
872 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
873 N->getOperand(0), N->getOperand(1));
874 Results.push_back(UDIVREM.getValue(1));
878 SDValue Op = SDValue(N, 0);
880 EVT VT = Op.getValueType();
881 SDValue SDIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(VT, VT),
882 N->getOperand(0), N->getOperand(1));
883 Results.push_back(SDIVREM);
887 SDValue Op = SDValue(N, 0);
889 EVT VT = Op.getValueType();
890 SDValue SDIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(VT, VT),
891 N->getOperand(0), N->getOperand(1));
892 Results.push_back(SDIVREM.getValue(1));
896 SDValue Op = SDValue(N, 1);
897 SDValue RES = LowerSDIVREM(Op, DAG);
898 Results.push_back(RES);
899 Results.push_back(RES.getValue(1));
903 SDValue Op = SDValue(N, 0);
905 EVT VT = Op.getValueType();
906 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
908 SDValue one = DAG.getConstant(1, HalfVT);
909 SDValue zero = DAG.getConstant(0, HalfVT);
912 SDValue LHS = N->getOperand(0);
913 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
914 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
916 SDValue RHS = N->getOperand(1);
917 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
918 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
920 // Get Speculative values
921 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
922 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
924 SDValue REM_Hi = zero;
925 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
927 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
928 SDValue DIV_Lo = zero;
930 const unsigned halfBitWidth = HalfVT.getSizeInBits();
932 for (unsigned i = 0; i < halfBitWidth; ++i) {
933 SDValue POS = DAG.getConstant(halfBitWidth - i - 1, HalfVT);
934 // Get Value of high bit
936 if (halfBitWidth == 32 && Subtarget->hasBFE()) {
937 HBit = DAG.getNode(AMDGPUISD::BFE_U32, DL, HalfVT, LHS_Lo, POS, one);
939 HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
940 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
943 SDValue Carry = DAG.getNode(ISD::SRL, DL, HalfVT, REM_Lo,
944 DAG.getConstant(halfBitWidth - 1, HalfVT));
945 REM_Hi = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Hi, one);
946 REM_Hi = DAG.getNode(ISD::OR, DL, HalfVT, REM_Hi, Carry);
948 REM_Lo = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Lo, one);
949 REM_Lo = DAG.getNode(ISD::OR, DL, HalfVT, REM_Lo, HBit);
952 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
954 SDValue BIT = DAG.getConstant(1 << (halfBitWidth - i - 1), HalfVT);
955 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETGE);
957 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
961 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
963 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETGE);
964 REM_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, zero);
965 REM_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, one);
968 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
969 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
970 Results.push_back(DIV);
971 Results.push_back(REM);
977 SDValue R600TargetLowering::vectorToVerticalVector(SelectionDAG &DAG,
978 SDValue Vector) const {
981 EVT VecVT = Vector.getValueType();
982 EVT EltVT = VecVT.getVectorElementType();
983 SmallVector<SDValue, 8> Args;
985 for (unsigned i = 0, e = VecVT.getVectorNumElements();
987 Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
988 Vector, DAG.getConstant(i, getVectorIdxTy())));
991 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args);
994 SDValue R600TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
995 SelectionDAG &DAG) const {
998 SDValue Vector = Op.getOperand(0);
999 SDValue Index = Op.getOperand(1);
1001 if (isa<ConstantSDNode>(Index) ||
1002 Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
1005 Vector = vectorToVerticalVector(DAG, Vector);
1006 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(),
1010 SDValue R600TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
1011 SelectionDAG &DAG) const {
1013 SDValue Vector = Op.getOperand(0);
1014 SDValue Value = Op.getOperand(1);
1015 SDValue Index = Op.getOperand(2);
1017 if (isa<ConstantSDNode>(Index) ||
1018 Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
1021 Vector = vectorToVerticalVector(DAG, Vector);
1022 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(),
1023 Vector, Value, Index);
1024 return vectorToVerticalVector(DAG, Insert);
1027 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
1028 // On hw >= R700, COS/SIN input must be between -1. and 1.
1029 // Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5)
1030 EVT VT = Op.getValueType();
1031 SDValue Arg = Op.getOperand(0);
1032 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
1033 DAG.getNode(ISD::FADD, SDLoc(Op), VT,
1034 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
1035 DAG.getConstantFP(0.15915494309, MVT::f32)),
1036 DAG.getConstantFP(0.5, MVT::f32)));
1038 switch (Op.getOpcode()) {
1040 TrigNode = AMDGPUISD::COS_HW;
1043 TrigNode = AMDGPUISD::SIN_HW;
1046 llvm_unreachable("Wrong trig opcode");
1048 SDValue TrigVal = DAG.getNode(TrigNode, SDLoc(Op), VT,
1049 DAG.getNode(ISD::FADD, SDLoc(Op), VT, FractPart,
1050 DAG.getConstantFP(-0.5, MVT::f32)));
1051 if (Gen >= AMDGPUSubtarget::R700)
1053 // On R600 hw, COS/SIN input must be between -Pi and Pi.
1054 return DAG.getNode(ISD::FMUL, SDLoc(Op), VT, TrigVal,
1055 DAG.getConstantFP(3.14159265359, MVT::f32));
1058 SDValue R600TargetLowering::LowerSHLParts(SDValue Op, SelectionDAG &DAG) const {
1060 EVT VT = Op.getValueType();
1062 SDValue Lo = Op.getOperand(0);
1063 SDValue Hi = Op.getOperand(1);
1064 SDValue Shift = Op.getOperand(2);
1065 SDValue Zero = DAG.getConstant(0, VT);
1066 SDValue One = DAG.getConstant(1, VT);
1068 SDValue Width = DAG.getConstant(VT.getSizeInBits(), VT);
1069 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, VT);
1070 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
1071 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
1073 // The dance around Width1 is necessary for 0 special case.
1074 // Without it the CompShift might be 32, producing incorrect results in
1075 // Overflow. So we do the shift in two steps, the alternative is to
1076 // add a conditional to filter the special case.
1078 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift);
1079 Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One);
1081 SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift);
1082 HiSmall = DAG.getNode(ISD::OR, DL, VT, HiSmall, Overflow);
1083 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift);
1085 SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift);
1086 SDValue LoBig = Zero;
1088 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
1089 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
1091 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
1094 SDValue R600TargetLowering::LowerSRXParts(SDValue Op, SelectionDAG &DAG) const {
1096 EVT VT = Op.getValueType();
1098 SDValue Lo = Op.getOperand(0);
1099 SDValue Hi = Op.getOperand(1);
1100 SDValue Shift = Op.getOperand(2);
1101 SDValue Zero = DAG.getConstant(0, VT);
1102 SDValue One = DAG.getConstant(1, VT);
1104 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS;
1106 SDValue Width = DAG.getConstant(VT.getSizeInBits(), VT);
1107 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, VT);
1108 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
1109 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
1111 // The dance around Width1 is necessary for 0 special case.
1112 // Without it the CompShift might be 32, producing incorrect results in
1113 // Overflow. So we do the shift in two steps, the alternative is to
1114 // add a conditional to filter the special case.
1116 SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift);
1117 Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One);
1119 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift);
1120 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift);
1121 LoSmall = DAG.getNode(ISD::OR, DL, VT, LoSmall, Overflow);
1123 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift);
1124 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero;
1126 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
1127 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
1129 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
1132 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
1137 Op, DAG.getConstantFP(0.0f, MVT::f32),
1138 DAG.getCondCode(ISD::SETNE)
1142 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
1144 unsigned DwordOffset) const {
1145 unsigned ByteOffset = DwordOffset * 4;
1146 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1147 AMDGPUAS::CONSTANT_BUFFER_0);
1149 // We shouldn't be using an offset wider than 16-bits for implicit parameters.
1150 assert(isInt<16>(ByteOffset));
1152 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
1153 DAG.getConstant(ByteOffset, MVT::i32), // PTR
1154 MachinePointerInfo(ConstantPointerNull::get(PtrType)),
1155 false, false, false, 0);
1158 bool R600TargetLowering::isZero(SDValue Op) const {
1159 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
1160 return Cst->isNullValue();
1161 } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
1162 return CstFP->isZero();
1168 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
1170 EVT VT = Op.getValueType();
1172 SDValue LHS = Op.getOperand(0);
1173 SDValue RHS = Op.getOperand(1);
1174 SDValue True = Op.getOperand(2);
1175 SDValue False = Op.getOperand(3);
1176 SDValue CC = Op.getOperand(4);
1179 // LHS and RHS are guaranteed to be the same value type
1180 EVT CompareVT = LHS.getValueType();
1182 // Check if we can lower this to a native operation.
1184 // Try to lower to a SET* instruction:
1186 // SET* can match the following patterns:
1188 // select_cc f32, f32, -1, 0, cc_supported
1189 // select_cc f32, f32, 1.0f, 0.0f, cc_supported
1190 // select_cc i32, i32, -1, 0, cc_supported
1193 // Move hardware True/False values to the correct operand.
1194 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1195 ISD::CondCode InverseCC =
1196 ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
1197 if (isHWTrueValue(False) && isHWFalseValue(True)) {
1198 if (isCondCodeLegal(InverseCC, CompareVT.getSimpleVT())) {
1199 std::swap(False, True);
1200 CC = DAG.getCondCode(InverseCC);
1202 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InverseCC);
1203 if (isCondCodeLegal(SwapInvCC, CompareVT.getSimpleVT())) {
1204 std::swap(False, True);
1205 std::swap(LHS, RHS);
1206 CC = DAG.getCondCode(SwapInvCC);
1211 if (isHWTrueValue(True) && isHWFalseValue(False) &&
1212 (CompareVT == VT || VT == MVT::i32)) {
1213 // This can be matched by a SET* instruction.
1214 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
1217 // Try to lower to a CND* instruction:
1219 // CND* can match the following patterns:
1221 // select_cc f32, 0.0, f32, f32, cc_supported
1222 // select_cc f32, 0.0, i32, i32, cc_supported
1223 // select_cc i32, 0, f32, f32, cc_supported
1224 // select_cc i32, 0, i32, i32, cc_supported
1227 // Try to move the zero value to the RHS
1229 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1230 // Try swapping the operands
1231 ISD::CondCode CCSwapped = ISD::getSetCCSwappedOperands(CCOpcode);
1232 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
1233 std::swap(LHS, RHS);
1234 CC = DAG.getCondCode(CCSwapped);
1236 // Try inverting the conditon and then swapping the operands
1237 ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT.isInteger());
1238 CCSwapped = ISD::getSetCCSwappedOperands(CCInv);
1239 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
1240 std::swap(True, False);
1241 std::swap(LHS, RHS);
1242 CC = DAG.getCondCode(CCSwapped);
1249 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1250 if (CompareVT != VT) {
1251 // Bitcast True / False to the correct types. This will end up being
1252 // a nop, but it allows us to define only a single pattern in the
1253 // .TD files for each CND* instruction rather than having to have
1254 // one pattern for integer True/False and one for fp True/False
1255 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
1256 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
1263 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
1271 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
1274 DAG.getCondCode(CCOpcode));
1275 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
1278 // If we make it this for it means we have no native instructions to handle
1279 // this SELECT_CC, so we must lower it.
1280 SDValue HWTrue, HWFalse;
1282 if (CompareVT == MVT::f32) {
1283 HWTrue = DAG.getConstantFP(1.0f, CompareVT);
1284 HWFalse = DAG.getConstantFP(0.0f, CompareVT);
1285 } else if (CompareVT == MVT::i32) {
1286 HWTrue = DAG.getConstant(-1, CompareVT);
1287 HWFalse = DAG.getConstant(0, CompareVT);
1290 llvm_unreachable("Unhandled value type in LowerSELECT_CC");
1293 // Lower this unsupported SELECT_CC into a combination of two supported
1294 // SELECT_CC operations.
1295 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
1297 return DAG.getNode(ISD::SELECT_CC, DL, VT,
1300 DAG.getCondCode(ISD::SETNE));
1303 /// LLVM generates byte-addressed pointers. For indirect addressing, we need to
1304 /// convert these pointers to a register index. Each register holds
1305 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
1306 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
1307 /// for indirect addressing.
1308 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
1309 unsigned StackWidth,
1310 SelectionDAG &DAG) const {
1312 switch(StackWidth) {
1322 default: llvm_unreachable("Invalid stack width");
1325 return DAG.getNode(ISD::SRL, SDLoc(Ptr), Ptr.getValueType(), Ptr,
1326 DAG.getConstant(SRLPad, MVT::i32));
1329 void R600TargetLowering::getStackAddress(unsigned StackWidth,
1332 unsigned &PtrIncr) const {
1333 switch (StackWidth) {
1344 Channel = ElemIdx % 2;
1358 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1360 StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
1361 SDValue Chain = Op.getOperand(0);
1362 SDValue Value = Op.getOperand(1);
1363 SDValue Ptr = Op.getOperand(2);
1365 SDValue Result = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1366 if (Result.getNode()) {
1370 if (StoreNode->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS) {
1371 if (StoreNode->isTruncatingStore()) {
1372 EVT VT = Value.getValueType();
1373 assert(VT.bitsLE(MVT::i32));
1374 EVT MemVT = StoreNode->getMemoryVT();
1375 SDValue MaskConstant;
1376 if (MemVT == MVT::i8) {
1377 MaskConstant = DAG.getConstant(0xFF, MVT::i32);
1379 assert(MemVT == MVT::i16);
1380 MaskConstant = DAG.getConstant(0xFFFF, MVT::i32);
1382 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, VT, Ptr,
1383 DAG.getConstant(2, MVT::i32));
1384 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, Ptr.getValueType(), Ptr,
1385 DAG.getConstant(0x00000003, VT));
1386 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant);
1387 SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex,
1388 DAG.getConstant(3, VT));
1389 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, Shift);
1390 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, Shift);
1391 // XXX: If we add a 64-bit ZW register class, then we could use a 2 x i32
1395 DAG.getConstant(0, MVT::i32),
1396 DAG.getConstant(0, MVT::i32),
1399 SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src);
1400 SDValue Args[3] = { Chain, Input, DWordAddr };
1401 return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL,
1402 Op->getVTList(), Args, MemVT,
1403 StoreNode->getMemOperand());
1404 } else if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR &&
1405 Value.getValueType().bitsGE(MVT::i32)) {
1406 // Convert pointer from byte address to dword address.
1407 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(),
1408 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
1409 Ptr, DAG.getConstant(2, MVT::i32)));
1411 if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
1412 llvm_unreachable("Truncated and indexed stores not supported yet");
1414 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
1420 EVT ValueVT = Value.getValueType();
1422 if (StoreNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1426 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1427 if (Ret.getNode()) {
1430 // Lowering for indirect addressing
1432 const MachineFunction &MF = DAG.getMachineFunction();
1433 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>(
1434 getTargetMachine().getSubtargetImpl()->getFrameLowering());
1435 unsigned StackWidth = TFL->getStackWidth(MF);
1437 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1439 if (ValueVT.isVector()) {
1440 unsigned NumElemVT = ValueVT.getVectorNumElements();
1441 EVT ElemVT = ValueVT.getVectorElementType();
1442 SmallVector<SDValue, 4> Stores(NumElemVT);
1444 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1445 "vector width in load");
1447 for (unsigned i = 0; i < NumElemVT; ++i) {
1448 unsigned Channel, PtrIncr;
1449 getStackAddress(StackWidth, i, Channel, PtrIncr);
1450 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1451 DAG.getConstant(PtrIncr, MVT::i32));
1452 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
1453 Value, DAG.getConstant(i, MVT::i32));
1455 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1457 DAG.getTargetConstant(Channel, MVT::i32));
1459 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores);
1461 if (ValueVT == MVT::i8) {
1462 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
1464 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
1465 DAG.getTargetConstant(0, MVT::i32)); // Channel
1471 // return (512 + (kc_bank << 12)
1473 ConstantAddressBlock(unsigned AddressSpace) {
1474 switch (AddressSpace) {
1475 case AMDGPUAS::CONSTANT_BUFFER_0:
1477 case AMDGPUAS::CONSTANT_BUFFER_1:
1479 case AMDGPUAS::CONSTANT_BUFFER_2:
1480 return 512 + 4096 * 2;
1481 case AMDGPUAS::CONSTANT_BUFFER_3:
1482 return 512 + 4096 * 3;
1483 case AMDGPUAS::CONSTANT_BUFFER_4:
1484 return 512 + 4096 * 4;
1485 case AMDGPUAS::CONSTANT_BUFFER_5:
1486 return 512 + 4096 * 5;
1487 case AMDGPUAS::CONSTANT_BUFFER_6:
1488 return 512 + 4096 * 6;
1489 case AMDGPUAS::CONSTANT_BUFFER_7:
1490 return 512 + 4096 * 7;
1491 case AMDGPUAS::CONSTANT_BUFFER_8:
1492 return 512 + 4096 * 8;
1493 case AMDGPUAS::CONSTANT_BUFFER_9:
1494 return 512 + 4096 * 9;
1495 case AMDGPUAS::CONSTANT_BUFFER_10:
1496 return 512 + 4096 * 10;
1497 case AMDGPUAS::CONSTANT_BUFFER_11:
1498 return 512 + 4096 * 11;
1499 case AMDGPUAS::CONSTANT_BUFFER_12:
1500 return 512 + 4096 * 12;
1501 case AMDGPUAS::CONSTANT_BUFFER_13:
1502 return 512 + 4096 * 13;
1503 case AMDGPUAS::CONSTANT_BUFFER_14:
1504 return 512 + 4096 * 14;
1505 case AMDGPUAS::CONSTANT_BUFFER_15:
1506 return 512 + 4096 * 15;
1512 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
1514 EVT VT = Op.getValueType();
1516 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1517 SDValue Chain = Op.getOperand(0);
1518 SDValue Ptr = Op.getOperand(1);
1519 SDValue LoweredLoad;
1521 SDValue Ret = AMDGPUTargetLowering::LowerLOAD(Op, DAG);
1522 if (Ret.getNode()) {
1527 return DAG.getMergeValues(Ops, DL);
1530 // Lower loads constant address space global variable loads
1531 if (LoadNode->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
1532 isa<GlobalVariable>(
1533 GetUnderlyingObject(LoadNode->getMemOperand()->getValue()))) {
1535 SDValue Ptr = DAG.getZExtOrTrunc(LoadNode->getBasePtr(), DL,
1536 getPointerTy(AMDGPUAS::PRIVATE_ADDRESS));
1537 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
1538 DAG.getConstant(2, MVT::i32));
1539 return DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op->getVTList(),
1540 LoadNode->getChain(), Ptr,
1541 DAG.getTargetConstant(0, MVT::i32), Op.getOperand(2));
1544 if (LoadNode->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS && VT.isVector()) {
1545 SDValue MergedValues[2] = {
1546 ScalarizeVectorLoad(Op, DAG),
1549 return DAG.getMergeValues(MergedValues, DL);
1552 int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
1553 if (ConstantBlock > -1 &&
1554 ((LoadNode->getExtensionType() == ISD::NON_EXTLOAD) ||
1555 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) {
1557 if (isa<ConstantExpr>(LoadNode->getMemOperand()->getValue()) ||
1558 isa<Constant>(LoadNode->getMemOperand()->getValue()) ||
1559 isa<ConstantSDNode>(Ptr)) {
1561 for (unsigned i = 0; i < 4; i++) {
1562 // We want Const position encoded with the following formula :
1563 // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
1564 // const_index is Ptr computed by llvm using an alignment of 16.
1565 // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
1566 // then div by 4 at the ISel step
1567 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1568 DAG.getConstant(4 * i + ConstantBlock * 16, MVT::i32));
1569 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1571 EVT NewVT = MVT::v4i32;
1572 unsigned NumElements = 4;
1573 if (VT.isVector()) {
1575 NumElements = VT.getVectorNumElements();
1577 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT,
1578 makeArrayRef(Slots, NumElements));
1580 // non-constant ptr can't be folded, keeps it as a v4f32 load
1581 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
1582 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
1583 DAG.getConstant(LoadNode->getAddressSpace() -
1584 AMDGPUAS::CONSTANT_BUFFER_0, MVT::i32)
1588 if (!VT.isVector()) {
1589 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1590 DAG.getConstant(0, MVT::i32));
1593 SDValue MergedValues[2] = {
1597 return DAG.getMergeValues(MergedValues, DL);
1600 // For most operations returning SDValue() will result in the node being
1601 // expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so we
1602 // need to manually expand loads that may be legal in some address spaces and
1603 // illegal in others. SEXT loads from CONSTANT_BUFFER_0 are supported for
1604 // compute shaders, since the data is sign extended when it is uploaded to the
1605 // buffer. However SEXT loads from other address spaces are not supported, so
1606 // we need to expand them here.
1607 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
1608 EVT MemVT = LoadNode->getMemoryVT();
1609 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
1610 SDValue ShiftAmount =
1611 DAG.getConstant(VT.getSizeInBits() - MemVT.getSizeInBits(), MVT::i32);
1612 SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr,
1613 LoadNode->getPointerInfo(), MemVT,
1614 LoadNode->isVolatile(),
1615 LoadNode->isNonTemporal(),
1616 LoadNode->isInvariant(),
1617 LoadNode->getAlignment());
1618 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, NewLoad, ShiftAmount);
1619 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Shl, ShiftAmount);
1621 SDValue MergedValues[2] = { Sra, Chain };
1622 return DAG.getMergeValues(MergedValues, DL);
1625 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1629 // Lowering for indirect addressing
1630 const MachineFunction &MF = DAG.getMachineFunction();
1631 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>(
1632 getTargetMachine().getSubtargetImpl()->getFrameLowering());
1633 unsigned StackWidth = TFL->getStackWidth(MF);
1635 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1637 if (VT.isVector()) {
1638 unsigned NumElemVT = VT.getVectorNumElements();
1639 EVT ElemVT = VT.getVectorElementType();
1642 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1643 "vector width in load");
1645 for (unsigned i = 0; i < NumElemVT; ++i) {
1646 unsigned Channel, PtrIncr;
1647 getStackAddress(StackWidth, i, Channel, PtrIncr);
1648 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1649 DAG.getConstant(PtrIncr, MVT::i32));
1650 Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT,
1652 DAG.getTargetConstant(Channel, MVT::i32),
1655 for (unsigned i = NumElemVT; i < 4; ++i) {
1656 Loads[i] = DAG.getUNDEF(ElemVT);
1658 EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4);
1659 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads);
1661 LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
1663 DAG.getTargetConstant(0, MVT::i32), // Channel
1672 return DAG.getMergeValues(Ops, DL);
1675 SDValue R600TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1676 SDValue Chain = Op.getOperand(0);
1677 SDValue Cond = Op.getOperand(1);
1678 SDValue Jump = Op.getOperand(2);
1680 return DAG.getNode(AMDGPUISD::BRANCH_COND, SDLoc(Op), Op.getValueType(),
1684 /// XXX Only kernel functions are supported, so we can assume for now that
1685 /// every function is a kernel function, but in the future we should use
1686 /// separate calling conventions for kernel and non-kernel functions.
1687 SDValue R600TargetLowering::LowerFormalArguments(
1689 CallingConv::ID CallConv,
1691 const SmallVectorImpl<ISD::InputArg> &Ins,
1692 SDLoc DL, SelectionDAG &DAG,
1693 SmallVectorImpl<SDValue> &InVals) const {
1694 SmallVector<CCValAssign, 16> ArgLocs;
1695 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1697 MachineFunction &MF = DAG.getMachineFunction();
1698 unsigned ShaderType = MF.getInfo<R600MachineFunctionInfo>()->getShaderType();
1700 SmallVector<ISD::InputArg, 8> LocalIns;
1702 getOriginalFunctionArgs(DAG, MF.getFunction(), Ins, LocalIns);
1704 AnalyzeFormalArguments(CCInfo, LocalIns);
1706 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1707 CCValAssign &VA = ArgLocs[i];
1708 const ISD::InputArg &In = Ins[i];
1710 EVT MemVT = VA.getLocVT();
1711 if (!VT.isVector() && MemVT.isVector()) {
1712 // Get load source type if scalarized.
1713 MemVT = MemVT.getVectorElementType();
1716 if (ShaderType != ShaderType::COMPUTE) {
1717 unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass);
1718 SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT);
1719 InVals.push_back(Register);
1723 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1724 AMDGPUAS::CONSTANT_BUFFER_0);
1726 // i64 isn't a legal type, so the register type used ends up as i32, which
1727 // isn't expected here. It attempts to create this sextload, but it ends up
1728 // being invalid. Somehow this seems to work with i64 arguments, but breaks
1731 // The first 36 bytes of the input buffer contains information about
1732 // thread group and global sizes.
1733 ISD::LoadExtType Ext = ISD::NON_EXTLOAD;
1734 if (MemVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) {
1735 // FIXME: This should really check the extload type, but the handling of
1736 // extload vector parameters seems to be broken.
1738 // Ext = In.Flags.isSExt() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
1739 Ext = ISD::SEXTLOAD;
1742 // Compute the offset from the value.
1743 // XXX - I think PartOffset should give you this, but it seems to give the
1744 // size of the register which isn't useful.
1746 unsigned ValBase = ArgLocs[In.OrigArgIndex].getLocMemOffset();
1747 unsigned PartOffset = VA.getLocMemOffset();
1749 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy), PartOffset - ValBase);
1750 SDValue Arg = DAG.getLoad(ISD::UNINDEXED, Ext, VT, DL, Chain,
1751 DAG.getConstant(36 + PartOffset, MVT::i32),
1752 DAG.getUNDEF(MVT::i32),
1754 MemVT, false, true, true, 4);
1756 // 4 is the preferred alignment for the CONSTANT memory space.
1757 InVals.push_back(Arg);
1762 EVT R600TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1765 return VT.changeVectorElementTypeToInteger();
1768 static SDValue CompactSwizzlableVector(
1769 SelectionDAG &DAG, SDValue VectorEntry,
1770 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1771 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1772 assert(RemapSwizzle.empty());
1773 SDValue NewBldVec[4] = {
1774 VectorEntry.getOperand(0),
1775 VectorEntry.getOperand(1),
1776 VectorEntry.getOperand(2),
1777 VectorEntry.getOperand(3)
1780 for (unsigned i = 0; i < 4; i++) {
1781 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1782 // We mask write here to teach later passes that the ith element of this
1783 // vector is undef. Thus we can use it to reduce 128 bits reg usage,
1784 // break false dependencies and additionnaly make assembly easier to read.
1785 RemapSwizzle[i] = 7; // SEL_MASK_WRITE
1786 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(NewBldVec[i])) {
1788 RemapSwizzle[i] = 4; // SEL_0
1789 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1790 } else if (C->isExactlyValue(1.0)) {
1791 RemapSwizzle[i] = 5; // SEL_1
1792 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1796 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1798 for (unsigned j = 0; j < i; j++) {
1799 if (NewBldVec[i] == NewBldVec[j]) {
1800 NewBldVec[i] = DAG.getUNDEF(NewBldVec[i].getValueType());
1801 RemapSwizzle[i] = j;
1807 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1808 VectorEntry.getValueType(), NewBldVec);
1811 static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
1812 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1813 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1814 assert(RemapSwizzle.empty());
1815 SDValue NewBldVec[4] = {
1816 VectorEntry.getOperand(0),
1817 VectorEntry.getOperand(1),
1818 VectorEntry.getOperand(2),
1819 VectorEntry.getOperand(3)
1821 bool isUnmovable[4] = { false, false, false, false };
1822 for (unsigned i = 0; i < 4; i++) {
1823 RemapSwizzle[i] = i;
1824 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1825 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1828 isUnmovable[Idx] = true;
1832 for (unsigned i = 0; i < 4; i++) {
1833 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1834 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1836 if (isUnmovable[Idx])
1839 std::swap(NewBldVec[Idx], NewBldVec[i]);
1840 std::swap(RemapSwizzle[i], RemapSwizzle[Idx]);
1845 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1846 VectorEntry.getValueType(), NewBldVec);
1850 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector,
1851 SDValue Swz[4], SelectionDAG &DAG) const {
1852 assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR);
1853 // Old -> New swizzle values
1854 DenseMap<unsigned, unsigned> SwizzleRemap;
1856 BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap);
1857 for (unsigned i = 0; i < 4; i++) {
1858 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1859 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1860 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1863 SwizzleRemap.clear();
1864 BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap);
1865 for (unsigned i = 0; i < 4; i++) {
1866 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1867 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1868 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1875 //===----------------------------------------------------------------------===//
1876 // Custom DAG Optimizations
1877 //===----------------------------------------------------------------------===//
1879 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1880 DAGCombinerInfo &DCI) const {
1881 SelectionDAG &DAG = DCI.DAG;
1883 switch (N->getOpcode()) {
1884 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1885 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1886 case ISD::FP_ROUND: {
1887 SDValue Arg = N->getOperand(0);
1888 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1889 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), N->getValueType(0),
1895 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1896 // (i32 select_cc f32, f32, -1, 0 cc)
1898 // Mesa's GLSL frontend generates the above pattern a lot and we can lower
1899 // this to one of the SET*_DX10 instructions.
1900 case ISD::FP_TO_SINT: {
1901 SDValue FNeg = N->getOperand(0);
1902 if (FNeg.getOpcode() != ISD::FNEG) {
1905 SDValue SelectCC = FNeg.getOperand(0);
1906 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1907 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1908 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1909 !isHWTrueValue(SelectCC.getOperand(2)) ||
1910 !isHWFalseValue(SelectCC.getOperand(3))) {
1914 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
1915 SelectCC.getOperand(0), // LHS
1916 SelectCC.getOperand(1), // RHS
1917 DAG.getConstant(-1, MVT::i32), // True
1918 DAG.getConstant(0, MVT::i32), // Flase
1919 SelectCC.getOperand(4)); // CC
1924 // insert_vector_elt (build_vector elt0, ... , eltN), NewEltIdx, idx
1925 // => build_vector elt0, ... , NewEltIdx, ... , eltN
1926 case ISD::INSERT_VECTOR_ELT: {
1927 SDValue InVec = N->getOperand(0);
1928 SDValue InVal = N->getOperand(1);
1929 SDValue EltNo = N->getOperand(2);
1932 // If the inserted element is an UNDEF, just use the input vector.
1933 if (InVal.getOpcode() == ISD::UNDEF)
1936 EVT VT = InVec.getValueType();
1938 // If we can't generate a legal BUILD_VECTOR, exit
1939 if (!isOperationLegal(ISD::BUILD_VECTOR, VT))
1942 // Check that we know which element is being inserted
1943 if (!isa<ConstantSDNode>(EltNo))
1945 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
1947 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
1948 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
1950 SmallVector<SDValue, 8> Ops;
1951 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
1952 Ops.append(InVec.getNode()->op_begin(),
1953 InVec.getNode()->op_end());
1954 } else if (InVec.getOpcode() == ISD::UNDEF) {
1955 unsigned NElts = VT.getVectorNumElements();
1956 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
1961 // Insert the element
1962 if (Elt < Ops.size()) {
1963 // All the operands of BUILD_VECTOR must have the same type;
1964 // we enforce that here.
1965 EVT OpVT = Ops[0].getValueType();
1966 if (InVal.getValueType() != OpVT)
1967 InVal = OpVT.bitsGT(InVal.getValueType()) ?
1968 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
1969 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
1973 // Return the new vector
1974 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
1977 // Extract_vec (Build_vector) generated by custom lowering
1978 // also needs to be customly combined
1979 case ISD::EXTRACT_VECTOR_ELT: {
1980 SDValue Arg = N->getOperand(0);
1981 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1982 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1983 unsigned Element = Const->getZExtValue();
1984 return Arg->getOperand(Element);
1987 if (Arg.getOpcode() == ISD::BITCAST &&
1988 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1989 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1990 unsigned Element = Const->getZExtValue();
1991 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getVTList(),
1992 Arg->getOperand(0).getOperand(Element));
1997 case ISD::SELECT_CC: {
1998 // Try common optimizations
1999 SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
2003 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
2004 // selectcc x, y, a, b, inv(cc)
2006 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
2007 // selectcc x, y, a, b, cc
2008 SDValue LHS = N->getOperand(0);
2009 if (LHS.getOpcode() != ISD::SELECT_CC) {
2013 SDValue RHS = N->getOperand(1);
2014 SDValue True = N->getOperand(2);
2015 SDValue False = N->getOperand(3);
2016 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
2018 if (LHS.getOperand(2).getNode() != True.getNode() ||
2019 LHS.getOperand(3).getNode() != False.getNode() ||
2020 RHS.getNode() != False.getNode()) {
2025 default: return SDValue();
2026 case ISD::SETNE: return LHS;
2028 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
2029 LHSCC = ISD::getSetCCInverse(LHSCC,
2030 LHS.getOperand(0).getValueType().isInteger());
2031 if (DCI.isBeforeLegalizeOps() ||
2032 isCondCodeLegal(LHSCC, LHS.getOperand(0).getSimpleValueType()))
2033 return DAG.getSelectCC(SDLoc(N),
2045 case AMDGPUISD::EXPORT: {
2046 SDValue Arg = N->getOperand(1);
2047 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
2050 SDValue NewArgs[8] = {
2051 N->getOperand(0), // Chain
2053 N->getOperand(2), // ArrayBase
2054 N->getOperand(3), // Type
2055 N->getOperand(4), // SWZ_X
2056 N->getOperand(5), // SWZ_Y
2057 N->getOperand(6), // SWZ_Z
2058 N->getOperand(7) // SWZ_W
2061 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG);
2062 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs);
2064 case AMDGPUISD::TEXTURE_FETCH: {
2065 SDValue Arg = N->getOperand(1);
2066 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
2069 SDValue NewArgs[19] = {
2090 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG);
2091 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, SDLoc(N), N->getVTList(),
2096 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
2100 FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src, SDValue &Neg,
2101 SDValue &Abs, SDValue &Sel, SDValue &Imm, SelectionDAG &DAG) {
2102 const R600InstrInfo *TII =
2103 static_cast<const R600InstrInfo *>(DAG.getSubtarget().getInstrInfo());
2104 if (!Src.isMachineOpcode())
2106 switch (Src.getMachineOpcode()) {
2107 case AMDGPU::FNEG_R600:
2110 Src = Src.getOperand(0);
2111 Neg = DAG.getTargetConstant(1, MVT::i32);
2113 case AMDGPU::FABS_R600:
2116 Src = Src.getOperand(0);
2117 Abs = DAG.getTargetConstant(1, MVT::i32);
2119 case AMDGPU::CONST_COPY: {
2120 unsigned Opcode = ParentNode->getMachineOpcode();
2121 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2126 SDValue CstOffset = Src.getOperand(0);
2127 if (ParentNode->getValueType(0).isVector())
2130 // Gather constants values
2131 int SrcIndices[] = {
2132 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
2133 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
2134 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2),
2135 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
2136 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
2137 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
2138 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
2139 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
2140 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
2141 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
2142 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
2144 std::vector<unsigned> Consts;
2145 for (int OtherSrcIdx : SrcIndices) {
2146 int OtherSelIdx = TII->getSelIdx(Opcode, OtherSrcIdx);
2147 if (OtherSrcIdx < 0 || OtherSelIdx < 0)
2153 if (RegisterSDNode *Reg =
2154 dyn_cast<RegisterSDNode>(ParentNode->getOperand(OtherSrcIdx))) {
2155 if (Reg->getReg() == AMDGPU::ALU_CONST) {
2157 = cast<ConstantSDNode>(ParentNode->getOperand(OtherSelIdx));
2158 Consts.push_back(Cst->getZExtValue());
2163 ConstantSDNode *Cst = cast<ConstantSDNode>(CstOffset);
2164 Consts.push_back(Cst->getZExtValue());
2165 if (!TII->fitsConstReadLimitations(Consts)) {
2170 Src = DAG.getRegister(AMDGPU::ALU_CONST, MVT::f32);
2173 case AMDGPU::MOV_IMM_I32:
2174 case AMDGPU::MOV_IMM_F32: {
2175 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
2176 uint64_t ImmValue = 0;
2179 if (Src.getMachineOpcode() == AMDGPU::MOV_IMM_F32) {
2180 ConstantFPSDNode *FPC = dyn_cast<ConstantFPSDNode>(Src.getOperand(0));
2181 float FloatValue = FPC->getValueAPF().convertToFloat();
2182 if (FloatValue == 0.0) {
2183 ImmReg = AMDGPU::ZERO;
2184 } else if (FloatValue == 0.5) {
2185 ImmReg = AMDGPU::HALF;
2186 } else if (FloatValue == 1.0) {
2187 ImmReg = AMDGPU::ONE;
2189 ImmValue = FPC->getValueAPF().bitcastToAPInt().getZExtValue();
2192 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src.getOperand(0));
2193 uint64_t Value = C->getZExtValue();
2195 ImmReg = AMDGPU::ZERO;
2196 } else if (Value == 1) {
2197 ImmReg = AMDGPU::ONE_INT;
2203 // Check that we aren't already using an immediate.
2204 // XXX: It's possible for an instruction to have more than one
2205 // immediate operand, but this is not supported yet.
2206 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
2209 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Imm);
2211 if (C->getZExtValue())
2213 Imm = DAG.getTargetConstant(ImmValue, MVT::i32);
2215 Src = DAG.getRegister(ImmReg, MVT::i32);
2224 /// \brief Fold the instructions after selecting them
2225 SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node,
2226 SelectionDAG &DAG) const {
2227 const R600InstrInfo *TII =
2228 static_cast<const R600InstrInfo *>(DAG.getSubtarget().getInstrInfo());
2229 if (!Node->isMachineOpcode())
2231 unsigned Opcode = Node->getMachineOpcode();
2234 std::vector<SDValue> Ops;
2235 for (const SDUse &I : Node->ops())
2238 if (Opcode == AMDGPU::DOT_4) {
2239 int OperandIdx[] = {
2240 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
2241 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
2242 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
2243 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
2244 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
2245 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
2246 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
2247 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
2250 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_X),
2251 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Y),
2252 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Z),
2253 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_W),
2254 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_X),
2255 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Y),
2256 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Z),
2257 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_W)
2260 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_X),
2261 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Y),
2262 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Z),
2263 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_W),
2264 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_X),
2265 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Y),
2266 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Z),
2267 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_W)
2269 for (unsigned i = 0; i < 8; i++) {
2270 if (OperandIdx[i] < 0)
2272 SDValue &Src = Ops[OperandIdx[i] - 1];
2273 SDValue &Neg = Ops[NegIdx[i] - 1];
2274 SDValue &Abs = Ops[AbsIdx[i] - 1];
2275 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2276 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
2279 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2280 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, FakeOp, DAG))
2281 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2283 } else if (Opcode == AMDGPU::REG_SEQUENCE) {
2284 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) {
2285 SDValue &Src = Ops[i];
2286 if (FoldOperand(Node, i, Src, FakeOp, FakeOp, FakeOp, FakeOp, DAG))
2287 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2289 } else if (Opcode == AMDGPU::CLAMP_R600) {
2290 SDValue Src = Node->getOperand(0);
2291 if (!Src.isMachineOpcode() ||
2292 !TII->hasInstrModifiers(Src.getMachineOpcode()))
2294 int ClampIdx = TII->getOperandIdx(Src.getMachineOpcode(),
2295 AMDGPU::OpName::clamp);
2298 std::vector<SDValue> Ops;
2299 unsigned NumOp = Src.getNumOperands();
2300 for(unsigned i = 0; i < NumOp; ++i)
2301 Ops.push_back(Src.getOperand(i));
2302 Ops[ClampIdx - 1] = DAG.getTargetConstant(1, MVT::i32);
2303 return DAG.getMachineNode(Src.getMachineOpcode(), SDLoc(Node),
2304 Node->getVTList(), Ops);
2306 if (!TII->hasInstrModifiers(Opcode))
2308 int OperandIdx[] = {
2309 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
2310 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
2311 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2)
2314 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg),
2315 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg),
2316 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2_neg)
2319 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs),
2320 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs),
2323 for (unsigned i = 0; i < 3; i++) {
2324 if (OperandIdx[i] < 0)
2326 SDValue &Src = Ops[OperandIdx[i] - 1];
2327 SDValue &Neg = Ops[NegIdx[i] - 1];
2329 SDValue &Abs = (AbsIdx[i] > -1) ? Ops[AbsIdx[i] - 1] : FakeAbs;
2330 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2331 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
2332 int ImmIdx = TII->getOperandIdx(Opcode, AMDGPU::OpName::literal);
2337 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2338 SDValue &Imm = Ops[ImmIdx];
2339 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, Imm, DAG))
2340 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);