1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for R600
13 //===----------------------------------------------------------------------===//
15 #include "R600ISelLowering.h"
16 #include "R600Defines.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineFunctionInfo.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/IR/Argument.h"
24 #include "llvm/IR/Function.h"
28 R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
29 AMDGPUTargetLowering(TM),
30 Gen(TM.getSubtarget<AMDGPUSubtarget>().getGeneration()) {
31 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
32 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
33 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
34 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
35 computeRegisterProperties();
37 setOperationAction(ISD::FADD, MVT::v4f32, Expand);
38 setOperationAction(ISD::FMUL, MVT::v4f32, Expand);
39 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
40 setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
42 setOperationAction(ISD::FCOS, MVT::f32, Custom);
43 setOperationAction(ISD::FSIN, MVT::f32, Custom);
45 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Expand);
46 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Expand);
47 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Expand);
48 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand);
49 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
51 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
52 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
54 setOperationAction(ISD::FSUB, MVT::f32, Expand);
56 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
57 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
58 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
60 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
61 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
63 setOperationAction(ISD::SETCC, MVT::i32, Expand);
64 setOperationAction(ISD::SETCC, MVT::f32, Expand);
65 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
67 setOperationAction(ISD::SELECT, MVT::i32, Custom);
68 setOperationAction(ISD::SELECT, MVT::f32, Custom);
70 setOperationAction(ISD::VSELECT, MVT::v4i32, Expand);
71 setOperationAction(ISD::VSELECT, MVT::v2i32, Expand);
73 // Legalize loads and stores to the private address space.
74 setOperationAction(ISD::LOAD, MVT::i32, Custom);
75 setOperationAction(ISD::LOAD, MVT::v2i32, Expand);
76 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
77 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
78 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
79 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
80 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Custom);
81 setOperationAction(ISD::STORE, MVT::i8, Custom);
82 setOperationAction(ISD::STORE, MVT::i32, Custom);
83 setOperationAction(ISD::STORE, MVT::v2i32, Expand);
84 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
86 setOperationAction(ISD::LOAD, MVT::i32, Custom);
87 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
88 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
90 setTargetDAGCombine(ISD::FP_ROUND);
91 setTargetDAGCombine(ISD::FP_TO_SINT);
92 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
93 setTargetDAGCombine(ISD::SELECT_CC);
95 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
97 setBooleanContents(ZeroOrNegativeOneBooleanContent);
98 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
99 setSchedulingPreference(Sched::VLIW);
102 MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
103 MachineInstr * MI, MachineBasicBlock * BB) const {
104 MachineFunction * MF = BB->getParent();
105 MachineRegisterInfo &MRI = MF->getRegInfo();
106 MachineBasicBlock::iterator I = *MI;
107 const R600InstrInfo *TII =
108 static_cast<const R600InstrInfo*>(MF->getTarget().getInstrInfo());
110 switch (MI->getOpcode()) {
111 default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
112 case AMDGPU::CLAMP_R600: {
113 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
115 MI->getOperand(0).getReg(),
116 MI->getOperand(1).getReg());
117 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
121 case AMDGPU::FABS_R600: {
122 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
124 MI->getOperand(0).getReg(),
125 MI->getOperand(1).getReg());
126 TII->addFlag(NewMI, 0, MO_FLAG_ABS);
130 case AMDGPU::FNEG_R600: {
131 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
133 MI->getOperand(0).getReg(),
134 MI->getOperand(1).getReg());
135 TII->addFlag(NewMI, 0, MO_FLAG_NEG);
139 case AMDGPU::MASK_WRITE: {
140 unsigned maskedRegister = MI->getOperand(0).getReg();
141 assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
142 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
143 TII->addFlag(defInstr, 0, MO_FLAG_MASK);
147 case AMDGPU::LDS_READ_RET: {
148 MachineInstrBuilder NewMI = BuildMI(*BB, I, BB->findDebugLoc(I),
149 TII->get(MI->getOpcode()),
151 for (unsigned i = 1, e = MI->getNumOperands(); i < e; ++i) {
152 NewMI.addOperand(MI->getOperand(i));
154 TII->buildDefaultInstruction(*BB, I, AMDGPU::MOV,
155 MI->getOperand(0).getReg(),
160 case AMDGPU::MOV_IMM_F32:
161 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
162 MI->getOperand(1).getFPImm()->getValueAPF()
163 .bitcastToAPInt().getZExtValue());
165 case AMDGPU::MOV_IMM_I32:
166 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
167 MI->getOperand(1).getImm());
169 case AMDGPU::CONST_COPY: {
170 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
171 MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
172 TII->setImmOperand(NewMI, AMDGPU::OpName::src0_sel,
173 MI->getOperand(1).getImm());
177 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
178 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
179 unsigned EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
181 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
182 .addOperand(MI->getOperand(0))
183 .addOperand(MI->getOperand(1))
184 .addImm(EOP); // Set End of program bit
189 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
190 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
191 MachineOperand &RID = MI->getOperand(4);
192 MachineOperand &SID = MI->getOperand(5);
193 unsigned TextureId = MI->getOperand(6).getImm();
194 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
195 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
207 case 8: // ShadowRect
218 case 11: // Shadow1DArray
222 case 12: // Shadow2DArray
226 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
227 .addOperand(MI->getOperand(3))
245 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
246 .addOperand(MI->getOperand(2))
264 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
265 .addOperand(MI->getOperand(0))
266 .addOperand(MI->getOperand(1))
284 .addReg(T0, RegState::Implicit)
285 .addReg(T1, RegState::Implicit);
289 case AMDGPU::TXD_SHADOW: {
290 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
291 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
292 MachineOperand &RID = MI->getOperand(4);
293 MachineOperand &SID = MI->getOperand(5);
294 unsigned TextureId = MI->getOperand(6).getImm();
295 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
296 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
308 case 8: // ShadowRect
319 case 11: // Shadow1DArray
323 case 12: // Shadow2DArray
328 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
329 .addOperand(MI->getOperand(3))
347 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
348 .addOperand(MI->getOperand(2))
366 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
367 .addOperand(MI->getOperand(0))
368 .addOperand(MI->getOperand(1))
386 .addReg(T0, RegState::Implicit)
387 .addReg(T1, RegState::Implicit);
392 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
393 .addOperand(MI->getOperand(0));
396 case AMDGPU::BRANCH_COND_f32: {
397 MachineInstr *NewMI =
398 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
399 AMDGPU::PREDICATE_BIT)
400 .addOperand(MI->getOperand(1))
401 .addImm(OPCODE_IS_NOT_ZERO)
403 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
404 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
405 .addOperand(MI->getOperand(0))
406 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
410 case AMDGPU::BRANCH_COND_i32: {
411 MachineInstr *NewMI =
412 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
413 AMDGPU::PREDICATE_BIT)
414 .addOperand(MI->getOperand(1))
415 .addImm(OPCODE_IS_NOT_ZERO_INT)
417 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
418 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
419 .addOperand(MI->getOperand(0))
420 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
424 case AMDGPU::EG_ExportSwz:
425 case AMDGPU::R600_ExportSwz: {
426 // Instruction is left unmodified if its not the last one of its type
427 bool isLastInstructionOfItsType = true;
428 unsigned InstExportType = MI->getOperand(1).getImm();
429 for (MachineBasicBlock::iterator NextExportInst = llvm::next(I),
430 EndBlock = BB->end(); NextExportInst != EndBlock;
431 NextExportInst = llvm::next(NextExportInst)) {
432 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
433 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
434 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
436 if (CurrentInstExportType == InstExportType) {
437 isLastInstructionOfItsType = false;
442 bool EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN)? 1 : 0;
443 if (!EOP && !isLastInstructionOfItsType)
445 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
446 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
447 .addOperand(MI->getOperand(0))
448 .addOperand(MI->getOperand(1))
449 .addOperand(MI->getOperand(2))
450 .addOperand(MI->getOperand(3))
451 .addOperand(MI->getOperand(4))
452 .addOperand(MI->getOperand(5))
453 .addOperand(MI->getOperand(6))
458 case AMDGPU::RETURN: {
459 // RETURN instructions must have the live-out registers as implicit uses,
460 // otherwise they appear dead.
461 R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
462 MachineInstrBuilder MIB(*MF, MI);
463 for (unsigned i = 0, e = MFI->LiveOuts.size(); i != e; ++i)
464 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
469 MI->eraseFromParent();
473 //===----------------------------------------------------------------------===//
474 // Custom DAG Lowering Operations
475 //===----------------------------------------------------------------------===//
477 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
478 MachineFunction &MF = DAG.getMachineFunction();
479 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
480 switch (Op.getOpcode()) {
481 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
483 case ISD::FSIN: return LowerTrig(Op, DAG);
484 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
485 case ISD::SELECT: return LowerSELECT(Op, DAG);
486 case ISD::STORE: return LowerSTORE(Op, DAG);
487 case ISD::LOAD: return LowerLOAD(Op, DAG);
488 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
489 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
490 case ISD::INTRINSIC_VOID: {
491 SDValue Chain = Op.getOperand(0);
492 unsigned IntrinsicID =
493 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
494 switch (IntrinsicID) {
495 case AMDGPUIntrinsic::AMDGPU_store_output: {
496 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
497 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
498 MFI->LiveOuts.push_back(Reg);
499 return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2));
501 case AMDGPUIntrinsic::R600_store_swizzle: {
502 const SDValue Args[8] = {
504 Op.getOperand(2), // Export Value
505 Op.getOperand(3), // ArrayBase
506 Op.getOperand(4), // Type
507 DAG.getConstant(0, MVT::i32), // SWZ_X
508 DAG.getConstant(1, MVT::i32), // SWZ_Y
509 DAG.getConstant(2, MVT::i32), // SWZ_Z
510 DAG.getConstant(3, MVT::i32) // SWZ_W
512 return DAG.getNode(AMDGPUISD::EXPORT, SDLoc(Op), Op.getValueType(),
516 // default for switch(IntrinsicID)
519 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
522 case ISD::INTRINSIC_WO_CHAIN: {
523 unsigned IntrinsicID =
524 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
525 EVT VT = Op.getValueType();
527 switch(IntrinsicID) {
528 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
529 case AMDGPUIntrinsic::R600_load_input: {
530 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
531 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
532 MachineFunction &MF = DAG.getMachineFunction();
533 MachineRegisterInfo &MRI = MF.getRegInfo();
535 return DAG.getCopyFromReg(DAG.getEntryNode(),
536 SDLoc(DAG.getEntryNode()), Reg, VT);
539 case AMDGPUIntrinsic::R600_interp_input: {
540 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
541 int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
542 MachineSDNode *interp;
544 const MachineFunction &MF = DAG.getMachineFunction();
545 const R600InstrInfo *TII =
546 static_cast<const R600InstrInfo*>(MF.getTarget().getInstrInfo());
547 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
548 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
549 return DAG.getTargetExtractSubreg(
550 TII->getRegisterInfo().getSubRegFromChannel(slot % 4),
551 DL, MVT::f32, SDValue(interp, 0));
554 MachineFunction &MF = DAG.getMachineFunction();
555 MachineRegisterInfo &MRI = MF.getRegInfo();
556 unsigned RegisterI = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb);
557 unsigned RegisterJ = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1);
558 MRI.addLiveIn(RegisterI);
559 MRI.addLiveIn(RegisterJ);
560 SDValue RegisterINode = DAG.getCopyFromReg(DAG.getEntryNode(),
561 SDLoc(DAG.getEntryNode()), RegisterI, MVT::f32);
562 SDValue RegisterJNode = DAG.getCopyFromReg(DAG.getEntryNode(),
563 SDLoc(DAG.getEntryNode()), RegisterJ, MVT::f32);
566 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
567 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
568 RegisterJNode, RegisterINode);
570 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
571 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
572 RegisterJNode, RegisterINode);
573 return SDValue(interp, slot % 2);
575 case AMDGPUIntrinsic::R600_tex:
576 case AMDGPUIntrinsic::R600_texc:
577 case AMDGPUIntrinsic::R600_txl:
578 case AMDGPUIntrinsic::R600_txlc:
579 case AMDGPUIntrinsic::R600_txb:
580 case AMDGPUIntrinsic::R600_txbc:
581 case AMDGPUIntrinsic::R600_txf:
582 case AMDGPUIntrinsic::R600_txq:
583 case AMDGPUIntrinsic::R600_ddx:
584 case AMDGPUIntrinsic::R600_ddy: {
586 switch (IntrinsicID) {
587 case AMDGPUIntrinsic::R600_tex:
590 case AMDGPUIntrinsic::R600_texc:
593 case AMDGPUIntrinsic::R600_txl:
596 case AMDGPUIntrinsic::R600_txlc:
599 case AMDGPUIntrinsic::R600_txb:
602 case AMDGPUIntrinsic::R600_txbc:
605 case AMDGPUIntrinsic::R600_txf:
608 case AMDGPUIntrinsic::R600_txq:
611 case AMDGPUIntrinsic::R600_ddx:
614 case AMDGPUIntrinsic::R600_ddy:
618 llvm_unreachable("Unknow Texture Operation");
621 SDValue TexArgs[19] = {
622 DAG.getConstant(TextureOp, MVT::i32),
624 DAG.getConstant(0, MVT::i32),
625 DAG.getConstant(1, MVT::i32),
626 DAG.getConstant(2, MVT::i32),
627 DAG.getConstant(3, MVT::i32),
631 DAG.getConstant(0, MVT::i32),
632 DAG.getConstant(1, MVT::i32),
633 DAG.getConstant(2, MVT::i32),
634 DAG.getConstant(3, MVT::i32),
642 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs, 19);
644 case AMDGPUIntrinsic::AMDGPU_dp4: {
646 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
647 DAG.getConstant(0, MVT::i32)),
648 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
649 DAG.getConstant(0, MVT::i32)),
650 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
651 DAG.getConstant(1, MVT::i32)),
652 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
653 DAG.getConstant(1, MVT::i32)),
654 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
655 DAG.getConstant(2, MVT::i32)),
656 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
657 DAG.getConstant(2, MVT::i32)),
658 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
659 DAG.getConstant(3, MVT::i32)),
660 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
661 DAG.getConstant(3, MVT::i32))
663 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args, 8);
666 case Intrinsic::r600_read_ngroups_x:
667 return LowerImplicitParameter(DAG, VT, DL, 0);
668 case Intrinsic::r600_read_ngroups_y:
669 return LowerImplicitParameter(DAG, VT, DL, 1);
670 case Intrinsic::r600_read_ngroups_z:
671 return LowerImplicitParameter(DAG, VT, DL, 2);
672 case Intrinsic::r600_read_global_size_x:
673 return LowerImplicitParameter(DAG, VT, DL, 3);
674 case Intrinsic::r600_read_global_size_y:
675 return LowerImplicitParameter(DAG, VT, DL, 4);
676 case Intrinsic::r600_read_global_size_z:
677 return LowerImplicitParameter(DAG, VT, DL, 5);
678 case Intrinsic::r600_read_local_size_x:
679 return LowerImplicitParameter(DAG, VT, DL, 6);
680 case Intrinsic::r600_read_local_size_y:
681 return LowerImplicitParameter(DAG, VT, DL, 7);
682 case Intrinsic::r600_read_local_size_z:
683 return LowerImplicitParameter(DAG, VT, DL, 8);
685 case Intrinsic::r600_read_tgid_x:
686 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
688 case Intrinsic::r600_read_tgid_y:
689 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
691 case Intrinsic::r600_read_tgid_z:
692 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
694 case Intrinsic::r600_read_tidig_x:
695 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
697 case Intrinsic::r600_read_tidig_y:
698 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
700 case Intrinsic::r600_read_tidig_z:
701 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
704 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
707 } // end switch(Op.getOpcode())
711 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
712 SmallVectorImpl<SDValue> &Results,
713 SelectionDAG &DAG) const {
714 switch (N->getOpcode()) {
716 case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
719 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
720 Results.push_back(SDValue(Node, 0));
721 Results.push_back(SDValue(Node, 1));
722 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
724 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
728 SDNode *Node = LowerSTORE(SDValue(N, 0), DAG).getNode();
729 Results.push_back(SDValue(Node, 0));
734 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
735 // On hw >= R700, COS/SIN input must be between -1. and 1.
736 // Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5)
737 EVT VT = Op.getValueType();
738 SDValue Arg = Op.getOperand(0);
739 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
740 DAG.getNode(ISD::FADD, SDLoc(Op), VT,
741 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
742 DAG.getConstantFP(0.15915494309, MVT::f32)),
743 DAG.getConstantFP(0.5, MVT::f32)));
745 switch (Op.getOpcode()) {
747 TrigNode = AMDGPUISD::COS_HW;
750 TrigNode = AMDGPUISD::SIN_HW;
753 llvm_unreachable("Wrong trig opcode");
755 SDValue TrigVal = DAG.getNode(TrigNode, SDLoc(Op), VT,
756 DAG.getNode(ISD::FADD, SDLoc(Op), VT, FractPart,
757 DAG.getConstantFP(-0.5, MVT::f32)));
758 if (Gen >= AMDGPUSubtarget::R700)
760 // On R600 hw, COS/SIN input must be between -Pi and Pi.
761 return DAG.getNode(ISD::FMUL, SDLoc(Op), VT, TrigVal,
762 DAG.getConstantFP(3.14159265359, MVT::f32));
765 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
770 Op, DAG.getConstantFP(0.0f, MVT::f32),
771 DAG.getCondCode(ISD::SETNE)
775 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
777 unsigned DwordOffset) const {
778 unsigned ByteOffset = DwordOffset * 4;
779 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
780 AMDGPUAS::PARAM_I_ADDRESS);
782 // We shouldn't be using an offset wider than 16-bits for implicit parameters.
783 assert(isInt<16>(ByteOffset));
785 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
786 DAG.getConstant(ByteOffset, MVT::i32), // PTR
787 MachinePointerInfo(ConstantPointerNull::get(PtrType)),
788 false, false, false, 0);
791 SDValue R600TargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
793 MachineFunction &MF = DAG.getMachineFunction();
794 const AMDGPUFrameLowering *TFL =
795 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
797 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op);
800 unsigned FrameIndex = FIN->getIndex();
801 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
802 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), MVT::i32);
805 bool R600TargetLowering::isZero(SDValue Op) const {
806 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
807 return Cst->isNullValue();
808 } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
809 return CstFP->isZero();
815 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
817 EVT VT = Op.getValueType();
819 SDValue LHS = Op.getOperand(0);
820 SDValue RHS = Op.getOperand(1);
821 SDValue True = Op.getOperand(2);
822 SDValue False = Op.getOperand(3);
823 SDValue CC = Op.getOperand(4);
826 // LHS and RHS are guaranteed to be the same value type
827 EVT CompareVT = LHS.getValueType();
829 // Check if we can lower this to a native operation.
831 // Try to lower to a SET* instruction:
833 // SET* can match the following patterns:
835 // select_cc f32, f32, -1, 0, cc_any
836 // select_cc f32, f32, 1.0f, 0.0f, cc_any
837 // select_cc i32, i32, -1, 0, cc_any
840 // Move hardware True/False values to the correct operand.
841 if (isHWTrueValue(False) && isHWFalseValue(True)) {
842 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
843 std::swap(False, True);
844 CC = DAG.getCondCode(ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32));
847 if (isHWTrueValue(True) && isHWFalseValue(False) &&
848 (CompareVT == VT || VT == MVT::i32)) {
849 // This can be matched by a SET* instruction.
850 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
853 // Try to lower to a CND* instruction:
855 // CND* can match the following patterns:
857 // select_cc f32, 0.0, f32, f32, cc_any
858 // select_cc f32, 0.0, i32, i32, cc_any
859 // select_cc i32, 0, f32, f32, cc_any
860 // select_cc i32, 0, i32, i32, cc_any
862 if (isZero(LHS) || isZero(RHS)) {
863 SDValue Cond = (isZero(LHS) ? RHS : LHS);
864 SDValue Zero = (isZero(LHS) ? LHS : RHS);
865 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
866 if (CompareVT != VT) {
867 // Bitcast True / False to the correct types. This will end up being
868 // a nop, but it allows us to define only a single pattern in the
869 // .TD files for each CND* instruction rather than having to have
870 // one pattern for integer True/False and one for fp True/False
871 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
872 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
875 CCOpcode = ISD::getSetCCSwappedOperands(CCOpcode);
888 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
896 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
899 DAG.getCondCode(CCOpcode));
900 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
904 // Possible Min/Max pattern
905 SDValue MinMax = LowerMinMax(Op, DAG);
906 if (MinMax.getNode()) {
910 // If we make it this for it means we have no native instructions to handle
911 // this SELECT_CC, so we must lower it.
912 SDValue HWTrue, HWFalse;
914 if (CompareVT == MVT::f32) {
915 HWTrue = DAG.getConstantFP(1.0f, CompareVT);
916 HWFalse = DAG.getConstantFP(0.0f, CompareVT);
917 } else if (CompareVT == MVT::i32) {
918 HWTrue = DAG.getConstant(-1, CompareVT);
919 HWFalse = DAG.getConstant(0, CompareVT);
922 assert(!"Unhandled value type in LowerSELECT_CC");
925 // Lower this unsupported SELECT_CC into a combination of two supported
926 // SELECT_CC operations.
927 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
929 return DAG.getNode(ISD::SELECT_CC, DL, VT,
932 DAG.getCondCode(ISD::SETNE));
935 SDValue R600TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
936 return DAG.getNode(ISD::SELECT_CC,
940 DAG.getConstant(0, MVT::i32),
943 DAG.getCondCode(ISD::SETNE));
946 /// LLVM generates byte-addresed pointers. For indirect addressing, we need to
947 /// convert these pointers to a register index. Each register holds
948 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
949 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
950 /// for indirect addressing.
951 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
953 SelectionDAG &DAG) const {
965 default: llvm_unreachable("Invalid stack width");
968 return DAG.getNode(ISD::SRL, SDLoc(Ptr), Ptr.getValueType(), Ptr,
969 DAG.getConstant(SRLPad, MVT::i32));
972 void R600TargetLowering::getStackAddress(unsigned StackWidth,
975 unsigned &PtrIncr) const {
976 switch (StackWidth) {
987 Channel = ElemIdx % 2;
1001 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1003 StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
1004 SDValue Chain = Op.getOperand(0);
1005 SDValue Value = Op.getOperand(1);
1006 SDValue Ptr = Op.getOperand(2);
1008 if (StoreNode->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
1009 Ptr->getOpcode() != AMDGPUISD::DWORDADDR) {
1010 // Convert pointer from byte address to dword address.
1011 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(),
1012 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
1013 Ptr, DAG.getConstant(2, MVT::i32)));
1015 if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
1016 assert(!"Truncated and indexed stores not supported yet");
1018 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
1023 EVT ValueVT = Value.getValueType();
1025 if (StoreNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1029 // Lowering for indirect addressing
1031 const MachineFunction &MF = DAG.getMachineFunction();
1032 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
1033 getTargetMachine().getFrameLowering());
1034 unsigned StackWidth = TFL->getStackWidth(MF);
1036 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1038 if (ValueVT.isVector()) {
1039 unsigned NumElemVT = ValueVT.getVectorNumElements();
1040 EVT ElemVT = ValueVT.getVectorElementType();
1043 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1044 "vector width in load");
1046 for (unsigned i = 0; i < NumElemVT; ++i) {
1047 unsigned Channel, PtrIncr;
1048 getStackAddress(StackWidth, i, Channel, PtrIncr);
1049 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1050 DAG.getConstant(PtrIncr, MVT::i32));
1051 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
1052 Value, DAG.getConstant(i, MVT::i32));
1054 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1056 DAG.getTargetConstant(Channel, MVT::i32));
1058 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores, NumElemVT);
1060 if (ValueVT == MVT::i8) {
1061 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
1063 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
1064 DAG.getTargetConstant(0, MVT::i32)); // Channel
1070 // return (512 + (kc_bank << 12)
1072 ConstantAddressBlock(unsigned AddressSpace) {
1073 switch (AddressSpace) {
1074 case AMDGPUAS::CONSTANT_BUFFER_0:
1076 case AMDGPUAS::CONSTANT_BUFFER_1:
1078 case AMDGPUAS::CONSTANT_BUFFER_2:
1079 return 512 + 4096 * 2;
1080 case AMDGPUAS::CONSTANT_BUFFER_3:
1081 return 512 + 4096 * 3;
1082 case AMDGPUAS::CONSTANT_BUFFER_4:
1083 return 512 + 4096 * 4;
1084 case AMDGPUAS::CONSTANT_BUFFER_5:
1085 return 512 + 4096 * 5;
1086 case AMDGPUAS::CONSTANT_BUFFER_6:
1087 return 512 + 4096 * 6;
1088 case AMDGPUAS::CONSTANT_BUFFER_7:
1089 return 512 + 4096 * 7;
1090 case AMDGPUAS::CONSTANT_BUFFER_8:
1091 return 512 + 4096 * 8;
1092 case AMDGPUAS::CONSTANT_BUFFER_9:
1093 return 512 + 4096 * 9;
1094 case AMDGPUAS::CONSTANT_BUFFER_10:
1095 return 512 + 4096 * 10;
1096 case AMDGPUAS::CONSTANT_BUFFER_11:
1097 return 512 + 4096 * 11;
1098 case AMDGPUAS::CONSTANT_BUFFER_12:
1099 return 512 + 4096 * 12;
1100 case AMDGPUAS::CONSTANT_BUFFER_13:
1101 return 512 + 4096 * 13;
1102 case AMDGPUAS::CONSTANT_BUFFER_14:
1103 return 512 + 4096 * 14;
1104 case AMDGPUAS::CONSTANT_BUFFER_15:
1105 return 512 + 4096 * 15;
1111 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
1113 EVT VT = Op.getValueType();
1115 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1116 SDValue Chain = Op.getOperand(0);
1117 SDValue Ptr = Op.getOperand(1);
1118 SDValue LoweredLoad;
1120 int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
1121 if (ConstantBlock > -1) {
1123 if (dyn_cast<ConstantExpr>(LoadNode->getSrcValue()) ||
1124 dyn_cast<Constant>(LoadNode->getSrcValue()) ||
1125 dyn_cast<ConstantSDNode>(Ptr)) {
1127 for (unsigned i = 0; i < 4; i++) {
1128 // We want Const position encoded with the following formula :
1129 // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
1130 // const_index is Ptr computed by llvm using an alignment of 16.
1131 // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
1132 // then div by 4 at the ISel step
1133 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1134 DAG.getConstant(4 * i + ConstantBlock * 16, MVT::i32));
1135 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1137 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Slots, 4);
1139 // non constant ptr cant be folded, keeps it as a v4f32 load
1140 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
1141 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
1142 DAG.getConstant(LoadNode->getAddressSpace() -
1143 AMDGPUAS::CONSTANT_BUFFER_0, MVT::i32)
1147 if (!VT.isVector()) {
1148 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1149 DAG.getConstant(0, MVT::i32));
1152 SDValue MergedValues[2] = {
1156 return DAG.getMergeValues(MergedValues, 2, DL);
1159 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1163 // Lowering for indirect addressing
1164 const MachineFunction &MF = DAG.getMachineFunction();
1165 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
1166 getTargetMachine().getFrameLowering());
1167 unsigned StackWidth = TFL->getStackWidth(MF);
1169 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1171 if (VT.isVector()) {
1172 unsigned NumElemVT = VT.getVectorNumElements();
1173 EVT ElemVT = VT.getVectorElementType();
1176 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1177 "vector width in load");
1179 for (unsigned i = 0; i < NumElemVT; ++i) {
1180 unsigned Channel, PtrIncr;
1181 getStackAddress(StackWidth, i, Channel, PtrIncr);
1182 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1183 DAG.getConstant(PtrIncr, MVT::i32));
1184 Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT,
1186 DAG.getTargetConstant(Channel, MVT::i32),
1189 for (unsigned i = NumElemVT; i < 4; ++i) {
1190 Loads[i] = DAG.getUNDEF(ElemVT);
1192 EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4);
1193 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads, 4);
1195 LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
1197 DAG.getTargetConstant(0, MVT::i32), // Channel
1202 Ops[0] = LoweredLoad;
1205 return DAG.getMergeValues(Ops, 2, DL);
1208 /// XXX Only kernel functions are supported, so we can assume for now that
1209 /// every function is a kernel function, but in the future we should use
1210 /// separate calling conventions for kernel and non-kernel functions.
1211 SDValue R600TargetLowering::LowerFormalArguments(
1213 CallingConv::ID CallConv,
1215 const SmallVectorImpl<ISD::InputArg> &Ins,
1216 SDLoc DL, SelectionDAG &DAG,
1217 SmallVectorImpl<SDValue> &InVals) const {
1218 unsigned ParamOffsetBytes = 36;
1219 Function::const_arg_iterator FuncArg =
1220 DAG.getMachineFunction().getFunction()->arg_begin();
1221 for (unsigned i = 0, e = Ins.size(); i < e; ++i, ++FuncArg) {
1223 Type *ArgType = FuncArg->getType();
1224 unsigned ArgSizeInBits = ArgType->isPointerTy() ?
1225 32 : ArgType->getPrimitiveSizeInBits();
1226 unsigned ArgBytes = ArgSizeInBits >> 3;
1228 if (ArgSizeInBits < VT.getSizeInBits()) {
1229 assert(!ArgType->isFloatTy() &&
1230 "Extending floating point arguments not supported yet");
1231 ArgVT = MVT::getIntegerVT(ArgSizeInBits);
1235 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1236 AMDGPUAS::PARAM_I_ADDRESS);
1237 SDValue Arg = DAG.getExtLoad(ISD::ZEXTLOAD, DL, VT, DAG.getRoot(),
1238 DAG.getConstant(ParamOffsetBytes, MVT::i32),
1239 MachinePointerInfo(UndefValue::get(PtrTy)),
1240 ArgVT, false, false, ArgBytes);
1241 InVals.push_back(Arg);
1242 ParamOffsetBytes += ArgBytes;
1247 EVT R600TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1248 if (!VT.isVector()) return MVT::i32;
1249 return VT.changeVectorElementTypeToInteger();
1253 CompactSwizzlableVector(SelectionDAG &DAG, SDValue VectorEntry,
1254 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1255 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1256 assert(RemapSwizzle.empty());
1257 SDValue NewBldVec[4] = {
1258 VectorEntry.getOperand(0),
1259 VectorEntry.getOperand(1),
1260 VectorEntry.getOperand(2),
1261 VectorEntry.getOperand(3)
1264 for (unsigned i = 0; i < 4; i++) {
1265 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(NewBldVec[i])) {
1267 RemapSwizzle[i] = 4; // SEL_0
1268 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1269 } else if (C->isExactlyValue(1.0)) {
1270 RemapSwizzle[i] = 5; // SEL_1
1271 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1275 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1277 for (unsigned j = 0; j < i; j++) {
1278 if (NewBldVec[i] == NewBldVec[j]) {
1279 NewBldVec[i] = DAG.getUNDEF(NewBldVec[i].getValueType());
1280 RemapSwizzle[i] = j;
1286 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1287 VectorEntry.getValueType(), NewBldVec, 4);
1290 static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
1291 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1292 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1293 assert(RemapSwizzle.empty());
1294 SDValue NewBldVec[4] = {
1295 VectorEntry.getOperand(0),
1296 VectorEntry.getOperand(1),
1297 VectorEntry.getOperand(2),
1298 VectorEntry.getOperand(3)
1300 bool isUnmovable[4] = { false, false, false, false };
1301 for (unsigned i = 0; i < 4; i++)
1302 RemapSwizzle[i] = i;
1304 for (unsigned i = 0; i < 4; i++) {
1305 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1306 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1308 if (!isUnmovable[Idx]) {
1310 std::swap(NewBldVec[Idx], NewBldVec[i]);
1311 std::swap(RemapSwizzle[RemapSwizzle[Idx]], RemapSwizzle[RemapSwizzle[i]]);
1313 isUnmovable[Idx] = true;
1317 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1318 VectorEntry.getValueType(), NewBldVec, 4);
1322 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector,
1323 SDValue Swz[4], SelectionDAG &DAG) const {
1324 assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR);
1325 // Old -> New swizzle values
1326 DenseMap<unsigned, unsigned> SwizzleRemap;
1328 BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap);
1329 for (unsigned i = 0; i < 4; i++) {
1330 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1331 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1332 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1335 SwizzleRemap.clear();
1336 BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap);
1337 for (unsigned i = 0; i < 4; i++) {
1338 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1339 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1340 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1347 //===----------------------------------------------------------------------===//
1348 // Custom DAG Optimizations
1349 //===----------------------------------------------------------------------===//
1351 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1352 DAGCombinerInfo &DCI) const {
1353 SelectionDAG &DAG = DCI.DAG;
1355 switch (N->getOpcode()) {
1356 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1357 case ISD::FP_ROUND: {
1358 SDValue Arg = N->getOperand(0);
1359 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1360 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), N->getValueType(0),
1366 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1367 // (i32 select_cc f32, f32, -1, 0 cc)
1369 // Mesa's GLSL frontend generates the above pattern a lot and we can lower
1370 // this to one of the SET*_DX10 instructions.
1371 case ISD::FP_TO_SINT: {
1372 SDValue FNeg = N->getOperand(0);
1373 if (FNeg.getOpcode() != ISD::FNEG) {
1376 SDValue SelectCC = FNeg.getOperand(0);
1377 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1378 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1379 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1380 !isHWTrueValue(SelectCC.getOperand(2)) ||
1381 !isHWFalseValue(SelectCC.getOperand(3))) {
1385 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
1386 SelectCC.getOperand(0), // LHS
1387 SelectCC.getOperand(1), // RHS
1388 DAG.getConstant(-1, MVT::i32), // True
1389 DAG.getConstant(0, MVT::i32), // Flase
1390 SelectCC.getOperand(4)); // CC
1394 // Extract_vec (Build_vector) generated by custom lowering
1395 // also needs to be customly combined
1396 case ISD::EXTRACT_VECTOR_ELT: {
1397 SDValue Arg = N->getOperand(0);
1398 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1399 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1400 unsigned Element = Const->getZExtValue();
1401 return Arg->getOperand(Element);
1404 if (Arg.getOpcode() == ISD::BITCAST &&
1405 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1406 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1407 unsigned Element = Const->getZExtValue();
1408 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getVTList(),
1409 Arg->getOperand(0).getOperand(Element));
1414 case ISD::SELECT_CC: {
1415 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1416 // selectcc x, y, a, b, inv(cc)
1418 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
1419 // selectcc x, y, a, b, cc
1420 SDValue LHS = N->getOperand(0);
1421 if (LHS.getOpcode() != ISD::SELECT_CC) {
1425 SDValue RHS = N->getOperand(1);
1426 SDValue True = N->getOperand(2);
1427 SDValue False = N->getOperand(3);
1428 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1430 if (LHS.getOperand(2).getNode() != True.getNode() ||
1431 LHS.getOperand(3).getNode() != False.getNode() ||
1432 RHS.getNode() != False.getNode()) {
1437 default: return SDValue();
1438 case ISD::SETNE: return LHS;
1440 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
1441 LHSCC = ISD::getSetCCInverse(LHSCC,
1442 LHS.getOperand(0).getValueType().isInteger());
1443 return DAG.getSelectCC(SDLoc(N),
1452 case AMDGPUISD::EXPORT: {
1453 SDValue Arg = N->getOperand(1);
1454 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1457 SDValue NewArgs[8] = {
1458 N->getOperand(0), // Chain
1460 N->getOperand(2), // ArrayBase
1461 N->getOperand(3), // Type
1462 N->getOperand(4), // SWZ_X
1463 N->getOperand(5), // SWZ_Y
1464 N->getOperand(6), // SWZ_Z
1465 N->getOperand(7) // SWZ_W
1468 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG);
1469 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs, 8);
1471 case AMDGPUISD::TEXTURE_FETCH: {
1472 SDValue Arg = N->getOperand(1);
1473 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1476 SDValue NewArgs[19] = {
1497 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG);
1498 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, SDLoc(N), N->getVTList(),