1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for R600
13 //===----------------------------------------------------------------------===//
15 #include "R600ISelLowering.h"
16 #include "R600Defines.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineFunctionInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/IR/Argument.h"
25 #include "llvm/IR/Function.h"
29 R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
30 AMDGPUTargetLowering(TM),
31 Gen(TM.getSubtarget<AMDGPUSubtarget>().getGeneration()) {
32 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
34 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
35 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
36 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
37 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
39 computeRegisterProperties();
41 // Set condition code actions
42 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
43 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
44 setCondCodeAction(ISD::SETLT, MVT::f32, Expand);
45 setCondCodeAction(ISD::SETLE, MVT::f32, Expand);
46 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
47 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
48 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
49 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
50 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
51 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
52 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
53 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
55 setCondCodeAction(ISD::SETLE, MVT::i32, Expand);
56 setCondCodeAction(ISD::SETLT, MVT::i32, Expand);
57 setCondCodeAction(ISD::SETULE, MVT::i32, Expand);
58 setCondCodeAction(ISD::SETULT, MVT::i32, Expand);
60 setOperationAction(ISD::FCOS, MVT::f32, Custom);
61 setOperationAction(ISD::FSIN, MVT::f32, Custom);
63 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
64 setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
66 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
67 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
69 setOperationAction(ISD::FSUB, MVT::f32, Expand);
71 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
72 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
73 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
75 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
76 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
78 setOperationAction(ISD::SETCC, MVT::i32, Expand);
79 setOperationAction(ISD::SETCC, MVT::f32, Expand);
80 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
82 setOperationAction(ISD::SELECT, MVT::i32, Expand);
83 setOperationAction(ISD::SELECT, MVT::f32, Expand);
84 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
85 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
87 // Expand sign extension of vectors
88 if (!Subtarget->hasBFE())
89 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
91 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand);
92 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand);
94 if (!Subtarget->hasBFE())
95 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
96 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand);
97 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand);
99 if (!Subtarget->hasBFE())
100 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand);
102 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
104 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
105 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand);
106 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand);
108 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
111 // Legalize loads and stores to the private address space.
112 setOperationAction(ISD::LOAD, MVT::i32, Custom);
113 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
114 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
116 // EXTLOAD should be the same as ZEXTLOAD. It is legal for some address
117 // spaces, so it is custom lowered to handle those where it isn't.
118 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
119 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
120 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
121 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
122 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
123 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Custom);
125 setOperationAction(ISD::STORE, MVT::i8, Custom);
126 setOperationAction(ISD::STORE, MVT::i32, Custom);
127 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
128 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
129 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
130 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
132 setOperationAction(ISD::LOAD, MVT::i32, Custom);
133 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
134 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
136 setTargetDAGCombine(ISD::FP_ROUND);
137 setTargetDAGCombine(ISD::FP_TO_SINT);
138 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
139 setTargetDAGCombine(ISD::SELECT_CC);
140 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
142 // These should be replaced by UDVIREM, but it does not happen automatically
143 // during Type Legalization
144 setOperationAction(ISD::UDIV, MVT::i64, Custom);
145 setOperationAction(ISD::UREM, MVT::i64, Custom);
147 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
149 setBooleanContents(ZeroOrNegativeOneBooleanContent);
150 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
151 setSchedulingPreference(Sched::Source);
154 MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
155 MachineInstr * MI, MachineBasicBlock * BB) const {
156 MachineFunction * MF = BB->getParent();
157 MachineRegisterInfo &MRI = MF->getRegInfo();
158 MachineBasicBlock::iterator I = *MI;
159 const R600InstrInfo *TII =
160 static_cast<const R600InstrInfo*>(MF->getTarget().getInstrInfo());
162 switch (MI->getOpcode()) {
164 // Replace LDS_*_RET instruction that don't have any uses with the
165 // equivalent LDS_*_NORET instruction.
166 if (TII->isLDSRetInstr(MI->getOpcode())) {
167 int DstIdx = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
168 assert(DstIdx != -1);
169 MachineInstrBuilder NewMI;
170 if (!MRI.use_empty(MI->getOperand(DstIdx).getReg()))
173 NewMI = BuildMI(*BB, I, BB->findDebugLoc(I),
174 TII->get(AMDGPU::getLDSNoRetOp(MI->getOpcode())));
175 for (unsigned i = 1, e = MI->getNumOperands(); i < e; ++i) {
176 NewMI.addOperand(MI->getOperand(i));
179 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
182 case AMDGPU::CLAMP_R600: {
183 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
185 MI->getOperand(0).getReg(),
186 MI->getOperand(1).getReg());
187 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
191 case AMDGPU::FABS_R600: {
192 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
194 MI->getOperand(0).getReg(),
195 MI->getOperand(1).getReg());
196 TII->addFlag(NewMI, 0, MO_FLAG_ABS);
200 case AMDGPU::FNEG_R600: {
201 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
203 MI->getOperand(0).getReg(),
204 MI->getOperand(1).getReg());
205 TII->addFlag(NewMI, 0, MO_FLAG_NEG);
209 case AMDGPU::MASK_WRITE: {
210 unsigned maskedRegister = MI->getOperand(0).getReg();
211 assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
212 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
213 TII->addFlag(defInstr, 0, MO_FLAG_MASK);
217 case AMDGPU::MOV_IMM_F32:
218 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
219 MI->getOperand(1).getFPImm()->getValueAPF()
220 .bitcastToAPInt().getZExtValue());
222 case AMDGPU::MOV_IMM_I32:
223 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
224 MI->getOperand(1).getImm());
226 case AMDGPU::CONST_COPY: {
227 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
228 MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
229 TII->setImmOperand(NewMI, AMDGPU::OpName::src0_sel,
230 MI->getOperand(1).getImm());
234 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
235 case AMDGPU::RAT_WRITE_CACHELESS_64_eg:
236 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
237 unsigned EOP = (std::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
239 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
240 .addOperand(MI->getOperand(0))
241 .addOperand(MI->getOperand(1))
242 .addImm(EOP); // Set End of program bit
247 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
248 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
249 MachineOperand &RID = MI->getOperand(4);
250 MachineOperand &SID = MI->getOperand(5);
251 unsigned TextureId = MI->getOperand(6).getImm();
252 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
253 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
265 case 8: // ShadowRect
276 case 11: // Shadow1DArray
280 case 12: // Shadow2DArray
284 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
285 .addOperand(MI->getOperand(3))
303 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
304 .addOperand(MI->getOperand(2))
322 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
323 .addOperand(MI->getOperand(0))
324 .addOperand(MI->getOperand(1))
342 .addReg(T0, RegState::Implicit)
343 .addReg(T1, RegState::Implicit);
347 case AMDGPU::TXD_SHADOW: {
348 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
349 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
350 MachineOperand &RID = MI->getOperand(4);
351 MachineOperand &SID = MI->getOperand(5);
352 unsigned TextureId = MI->getOperand(6).getImm();
353 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
354 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
366 case 8: // ShadowRect
377 case 11: // Shadow1DArray
381 case 12: // Shadow2DArray
386 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
387 .addOperand(MI->getOperand(3))
405 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
406 .addOperand(MI->getOperand(2))
424 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
425 .addOperand(MI->getOperand(0))
426 .addOperand(MI->getOperand(1))
444 .addReg(T0, RegState::Implicit)
445 .addReg(T1, RegState::Implicit);
450 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
451 .addOperand(MI->getOperand(0));
454 case AMDGPU::BRANCH_COND_f32: {
455 MachineInstr *NewMI =
456 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
457 AMDGPU::PREDICATE_BIT)
458 .addOperand(MI->getOperand(1))
459 .addImm(OPCODE_IS_NOT_ZERO)
461 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
462 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
463 .addOperand(MI->getOperand(0))
464 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
468 case AMDGPU::BRANCH_COND_i32: {
469 MachineInstr *NewMI =
470 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
471 AMDGPU::PREDICATE_BIT)
472 .addOperand(MI->getOperand(1))
473 .addImm(OPCODE_IS_NOT_ZERO_INT)
475 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
476 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
477 .addOperand(MI->getOperand(0))
478 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
482 case AMDGPU::EG_ExportSwz:
483 case AMDGPU::R600_ExportSwz: {
484 // Instruction is left unmodified if its not the last one of its type
485 bool isLastInstructionOfItsType = true;
486 unsigned InstExportType = MI->getOperand(1).getImm();
487 for (MachineBasicBlock::iterator NextExportInst = std::next(I),
488 EndBlock = BB->end(); NextExportInst != EndBlock;
489 NextExportInst = std::next(NextExportInst)) {
490 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
491 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
492 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
494 if (CurrentInstExportType == InstExportType) {
495 isLastInstructionOfItsType = false;
500 bool EOP = (std::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
501 if (!EOP && !isLastInstructionOfItsType)
503 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
504 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
505 .addOperand(MI->getOperand(0))
506 .addOperand(MI->getOperand(1))
507 .addOperand(MI->getOperand(2))
508 .addOperand(MI->getOperand(3))
509 .addOperand(MI->getOperand(4))
510 .addOperand(MI->getOperand(5))
511 .addOperand(MI->getOperand(6))
516 case AMDGPU::RETURN: {
517 // RETURN instructions must have the live-out registers as implicit uses,
518 // otherwise they appear dead.
519 R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
520 MachineInstrBuilder MIB(*MF, MI);
521 for (unsigned i = 0, e = MFI->LiveOuts.size(); i != e; ++i)
522 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
527 MI->eraseFromParent();
531 //===----------------------------------------------------------------------===//
532 // Custom DAG Lowering Operations
533 //===----------------------------------------------------------------------===//
535 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
536 MachineFunction &MF = DAG.getMachineFunction();
537 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
538 switch (Op.getOpcode()) {
539 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
541 case ISD::FSIN: return LowerTrig(Op, DAG);
542 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
543 case ISD::STORE: return LowerSTORE(Op, DAG);
544 case ISD::LOAD: return LowerLOAD(Op, DAG);
545 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
546 case ISD::INTRINSIC_VOID: {
547 SDValue Chain = Op.getOperand(0);
548 unsigned IntrinsicID =
549 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
550 switch (IntrinsicID) {
551 case AMDGPUIntrinsic::AMDGPU_store_output: {
552 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
553 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
554 MFI->LiveOuts.push_back(Reg);
555 return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2));
557 case AMDGPUIntrinsic::R600_store_swizzle: {
558 const SDValue Args[8] = {
560 Op.getOperand(2), // Export Value
561 Op.getOperand(3), // ArrayBase
562 Op.getOperand(4), // Type
563 DAG.getConstant(0, MVT::i32), // SWZ_X
564 DAG.getConstant(1, MVT::i32), // SWZ_Y
565 DAG.getConstant(2, MVT::i32), // SWZ_Z
566 DAG.getConstant(3, MVT::i32) // SWZ_W
568 return DAG.getNode(AMDGPUISD::EXPORT, SDLoc(Op), Op.getValueType(), Args);
571 // default for switch(IntrinsicID)
574 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
577 case ISD::INTRINSIC_WO_CHAIN: {
578 unsigned IntrinsicID =
579 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
580 EVT VT = Op.getValueType();
582 switch(IntrinsicID) {
583 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
584 case AMDGPUIntrinsic::R600_load_input: {
585 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
586 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
587 MachineFunction &MF = DAG.getMachineFunction();
588 MachineRegisterInfo &MRI = MF.getRegInfo();
590 return DAG.getCopyFromReg(DAG.getEntryNode(),
591 SDLoc(DAG.getEntryNode()), Reg, VT);
594 case AMDGPUIntrinsic::R600_interp_input: {
595 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
596 int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
597 MachineSDNode *interp;
599 const MachineFunction &MF = DAG.getMachineFunction();
600 const R600InstrInfo *TII =
601 static_cast<const R600InstrInfo*>(MF.getTarget().getInstrInfo());
602 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
603 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
604 return DAG.getTargetExtractSubreg(
605 TII->getRegisterInfo().getSubRegFromChannel(slot % 4),
606 DL, MVT::f32, SDValue(interp, 0));
608 MachineFunction &MF = DAG.getMachineFunction();
609 MachineRegisterInfo &MRI = MF.getRegInfo();
610 unsigned RegisterI = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb);
611 unsigned RegisterJ = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1);
612 MRI.addLiveIn(RegisterI);
613 MRI.addLiveIn(RegisterJ);
614 SDValue RegisterINode = DAG.getCopyFromReg(DAG.getEntryNode(),
615 SDLoc(DAG.getEntryNode()), RegisterI, MVT::f32);
616 SDValue RegisterJNode = DAG.getCopyFromReg(DAG.getEntryNode(),
617 SDLoc(DAG.getEntryNode()), RegisterJ, MVT::f32);
620 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
621 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
622 RegisterJNode, RegisterINode);
624 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
625 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
626 RegisterJNode, RegisterINode);
627 return SDValue(interp, slot % 2);
629 case AMDGPUIntrinsic::R600_interp_xy:
630 case AMDGPUIntrinsic::R600_interp_zw: {
631 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
632 MachineSDNode *interp;
633 SDValue RegisterINode = Op.getOperand(2);
634 SDValue RegisterJNode = Op.getOperand(3);
636 if (IntrinsicID == AMDGPUIntrinsic::R600_interp_xy)
637 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
638 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, MVT::i32),
639 RegisterJNode, RegisterINode);
641 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
642 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, MVT::i32),
643 RegisterJNode, RegisterINode);
644 return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32,
645 SDValue(interp, 0), SDValue(interp, 1));
647 case AMDGPUIntrinsic::R600_tex:
648 case AMDGPUIntrinsic::R600_texc:
649 case AMDGPUIntrinsic::R600_txl:
650 case AMDGPUIntrinsic::R600_txlc:
651 case AMDGPUIntrinsic::R600_txb:
652 case AMDGPUIntrinsic::R600_txbc:
653 case AMDGPUIntrinsic::R600_txf:
654 case AMDGPUIntrinsic::R600_txq:
655 case AMDGPUIntrinsic::R600_ddx:
656 case AMDGPUIntrinsic::R600_ddy:
657 case AMDGPUIntrinsic::R600_ldptr: {
659 switch (IntrinsicID) {
660 case AMDGPUIntrinsic::R600_tex:
663 case AMDGPUIntrinsic::R600_texc:
666 case AMDGPUIntrinsic::R600_txl:
669 case AMDGPUIntrinsic::R600_txlc:
672 case AMDGPUIntrinsic::R600_txb:
675 case AMDGPUIntrinsic::R600_txbc:
678 case AMDGPUIntrinsic::R600_txf:
681 case AMDGPUIntrinsic::R600_txq:
684 case AMDGPUIntrinsic::R600_ddx:
687 case AMDGPUIntrinsic::R600_ddy:
690 case AMDGPUIntrinsic::R600_ldptr:
694 llvm_unreachable("Unknow Texture Operation");
697 SDValue TexArgs[19] = {
698 DAG.getConstant(TextureOp, MVT::i32),
700 DAG.getConstant(0, MVT::i32),
701 DAG.getConstant(1, MVT::i32),
702 DAG.getConstant(2, MVT::i32),
703 DAG.getConstant(3, MVT::i32),
707 DAG.getConstant(0, MVT::i32),
708 DAG.getConstant(1, MVT::i32),
709 DAG.getConstant(2, MVT::i32),
710 DAG.getConstant(3, MVT::i32),
718 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs);
720 case AMDGPUIntrinsic::AMDGPU_dp4: {
722 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
723 DAG.getConstant(0, MVT::i32)),
724 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
725 DAG.getConstant(0, MVT::i32)),
726 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
727 DAG.getConstant(1, MVT::i32)),
728 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
729 DAG.getConstant(1, MVT::i32)),
730 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
731 DAG.getConstant(2, MVT::i32)),
732 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
733 DAG.getConstant(2, MVT::i32)),
734 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
735 DAG.getConstant(3, MVT::i32)),
736 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
737 DAG.getConstant(3, MVT::i32))
739 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args);
742 case Intrinsic::r600_read_ngroups_x:
743 return LowerImplicitParameter(DAG, VT, DL, 0);
744 case Intrinsic::r600_read_ngroups_y:
745 return LowerImplicitParameter(DAG, VT, DL, 1);
746 case Intrinsic::r600_read_ngroups_z:
747 return LowerImplicitParameter(DAG, VT, DL, 2);
748 case Intrinsic::r600_read_global_size_x:
749 return LowerImplicitParameter(DAG, VT, DL, 3);
750 case Intrinsic::r600_read_global_size_y:
751 return LowerImplicitParameter(DAG, VT, DL, 4);
752 case Intrinsic::r600_read_global_size_z:
753 return LowerImplicitParameter(DAG, VT, DL, 5);
754 case Intrinsic::r600_read_local_size_x:
755 return LowerImplicitParameter(DAG, VT, DL, 6);
756 case Intrinsic::r600_read_local_size_y:
757 return LowerImplicitParameter(DAG, VT, DL, 7);
758 case Intrinsic::r600_read_local_size_z:
759 return LowerImplicitParameter(DAG, VT, DL, 8);
761 case Intrinsic::r600_read_tgid_x:
762 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
764 case Intrinsic::r600_read_tgid_y:
765 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
767 case Intrinsic::r600_read_tgid_z:
768 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
770 case Intrinsic::r600_read_tidig_x:
771 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
773 case Intrinsic::r600_read_tidig_y:
774 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
776 case Intrinsic::r600_read_tidig_z:
777 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
780 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
783 } // end switch(Op.getOpcode())
787 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
788 SmallVectorImpl<SDValue> &Results,
789 SelectionDAG &DAG) const {
790 switch (N->getOpcode()) {
792 AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG);
794 case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
797 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
798 Results.push_back(SDValue(Node, 0));
799 Results.push_back(SDValue(Node, 1));
800 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
802 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
806 SDNode *Node = LowerSTORE(SDValue(N, 0), DAG).getNode();
807 Results.push_back(SDValue(Node, 0));
812 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
813 // On hw >= R700, COS/SIN input must be between -1. and 1.
814 // Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5)
815 EVT VT = Op.getValueType();
816 SDValue Arg = Op.getOperand(0);
817 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
818 DAG.getNode(ISD::FADD, SDLoc(Op), VT,
819 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
820 DAG.getConstantFP(0.15915494309, MVT::f32)),
821 DAG.getConstantFP(0.5, MVT::f32)));
823 switch (Op.getOpcode()) {
825 TrigNode = AMDGPUISD::COS_HW;
828 TrigNode = AMDGPUISD::SIN_HW;
831 llvm_unreachable("Wrong trig opcode");
833 SDValue TrigVal = DAG.getNode(TrigNode, SDLoc(Op), VT,
834 DAG.getNode(ISD::FADD, SDLoc(Op), VT, FractPart,
835 DAG.getConstantFP(-0.5, MVT::f32)));
836 if (Gen >= AMDGPUSubtarget::R700)
838 // On R600 hw, COS/SIN input must be between -Pi and Pi.
839 return DAG.getNode(ISD::FMUL, SDLoc(Op), VT, TrigVal,
840 DAG.getConstantFP(3.14159265359, MVT::f32));
843 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
848 Op, DAG.getConstantFP(0.0f, MVT::f32),
849 DAG.getCondCode(ISD::SETNE)
853 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
855 unsigned DwordOffset) const {
856 unsigned ByteOffset = DwordOffset * 4;
857 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
858 AMDGPUAS::CONSTANT_BUFFER_0);
860 // We shouldn't be using an offset wider than 16-bits for implicit parameters.
861 assert(isInt<16>(ByteOffset));
863 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
864 DAG.getConstant(ByteOffset, MVT::i32), // PTR
865 MachinePointerInfo(ConstantPointerNull::get(PtrType)),
866 false, false, false, 0);
869 bool R600TargetLowering::isZero(SDValue Op) const {
870 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
871 return Cst->isNullValue();
872 } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
873 return CstFP->isZero();
879 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
881 EVT VT = Op.getValueType();
883 SDValue LHS = Op.getOperand(0);
884 SDValue RHS = Op.getOperand(1);
885 SDValue True = Op.getOperand(2);
886 SDValue False = Op.getOperand(3);
887 SDValue CC = Op.getOperand(4);
890 // LHS and RHS are guaranteed to be the same value type
891 EVT CompareVT = LHS.getValueType();
893 // Check if we can lower this to a native operation.
895 // Try to lower to a SET* instruction:
897 // SET* can match the following patterns:
899 // select_cc f32, f32, -1, 0, cc_supported
900 // select_cc f32, f32, 1.0f, 0.0f, cc_supported
901 // select_cc i32, i32, -1, 0, cc_supported
904 // Move hardware True/False values to the correct operand.
905 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
906 ISD::CondCode InverseCC =
907 ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
908 if (isHWTrueValue(False) && isHWFalseValue(True)) {
909 if (isCondCodeLegal(InverseCC, CompareVT.getSimpleVT())) {
910 std::swap(False, True);
911 CC = DAG.getCondCode(InverseCC);
913 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InverseCC);
914 if (isCondCodeLegal(SwapInvCC, CompareVT.getSimpleVT())) {
915 std::swap(False, True);
917 CC = DAG.getCondCode(SwapInvCC);
922 if (isHWTrueValue(True) && isHWFalseValue(False) &&
923 (CompareVT == VT || VT == MVT::i32)) {
924 // This can be matched by a SET* instruction.
925 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
928 // Try to lower to a CND* instruction:
930 // CND* can match the following patterns:
932 // select_cc f32, 0.0, f32, f32, cc_supported
933 // select_cc f32, 0.0, i32, i32, cc_supported
934 // select_cc i32, 0, f32, f32, cc_supported
935 // select_cc i32, 0, i32, i32, cc_supported
938 // Try to move the zero value to the RHS
940 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
941 // Try swapping the operands
942 ISD::CondCode CCSwapped = ISD::getSetCCSwappedOperands(CCOpcode);
943 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
945 CC = DAG.getCondCode(CCSwapped);
947 // Try inverting the conditon and then swapping the operands
948 ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT.isInteger());
949 CCSwapped = ISD::getSetCCSwappedOperands(CCInv);
950 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
951 std::swap(True, False);
953 CC = DAG.getCondCode(CCSwapped);
960 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
961 if (CompareVT != VT) {
962 // Bitcast True / False to the correct types. This will end up being
963 // a nop, but it allows us to define only a single pattern in the
964 // .TD files for each CND* instruction rather than having to have
965 // one pattern for integer True/False and one for fp True/False
966 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
967 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
974 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
982 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
985 DAG.getCondCode(CCOpcode));
986 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
990 // Possible Min/Max pattern
991 SDValue MinMax = LowerMinMax(Op, DAG);
992 if (MinMax.getNode()) {
996 // If we make it this for it means we have no native instructions to handle
997 // this SELECT_CC, so we must lower it.
998 SDValue HWTrue, HWFalse;
1000 if (CompareVT == MVT::f32) {
1001 HWTrue = DAG.getConstantFP(1.0f, CompareVT);
1002 HWFalse = DAG.getConstantFP(0.0f, CompareVT);
1003 } else if (CompareVT == MVT::i32) {
1004 HWTrue = DAG.getConstant(-1, CompareVT);
1005 HWFalse = DAG.getConstant(0, CompareVT);
1008 llvm_unreachable("Unhandled value type in LowerSELECT_CC");
1011 // Lower this unsupported SELECT_CC into a combination of two supported
1012 // SELECT_CC operations.
1013 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
1015 return DAG.getNode(ISD::SELECT_CC, DL, VT,
1018 DAG.getCondCode(ISD::SETNE));
1021 /// LLVM generates byte-addressed pointers. For indirect addressing, we need to
1022 /// convert these pointers to a register index. Each register holds
1023 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
1024 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
1025 /// for indirect addressing.
1026 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
1027 unsigned StackWidth,
1028 SelectionDAG &DAG) const {
1030 switch(StackWidth) {
1040 default: llvm_unreachable("Invalid stack width");
1043 return DAG.getNode(ISD::SRL, SDLoc(Ptr), Ptr.getValueType(), Ptr,
1044 DAG.getConstant(SRLPad, MVT::i32));
1047 void R600TargetLowering::getStackAddress(unsigned StackWidth,
1050 unsigned &PtrIncr) const {
1051 switch (StackWidth) {
1062 Channel = ElemIdx % 2;
1076 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1078 StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
1079 SDValue Chain = Op.getOperand(0);
1080 SDValue Value = Op.getOperand(1);
1081 SDValue Ptr = Op.getOperand(2);
1083 SDValue Result = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1084 if (Result.getNode()) {
1088 if (StoreNode->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS) {
1089 if (StoreNode->isTruncatingStore()) {
1090 EVT VT = Value.getValueType();
1091 assert(VT.bitsLE(MVT::i32));
1092 EVT MemVT = StoreNode->getMemoryVT();
1093 SDValue MaskConstant;
1094 if (MemVT == MVT::i8) {
1095 MaskConstant = DAG.getConstant(0xFF, MVT::i32);
1097 assert(MemVT == MVT::i16);
1098 MaskConstant = DAG.getConstant(0xFFFF, MVT::i32);
1100 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, VT, Ptr,
1101 DAG.getConstant(2, MVT::i32));
1102 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, Ptr.getValueType(), Ptr,
1103 DAG.getConstant(0x00000003, VT));
1104 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant);
1105 SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex,
1106 DAG.getConstant(3, VT));
1107 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, Shift);
1108 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, Shift);
1109 // XXX: If we add a 64-bit ZW register class, then we could use a 2 x i32
1113 DAG.getConstant(0, MVT::i32),
1114 DAG.getConstant(0, MVT::i32),
1117 SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src);
1118 SDValue Args[3] = { Chain, Input, DWordAddr };
1119 return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL,
1120 Op->getVTList(), Args, MemVT,
1121 StoreNode->getMemOperand());
1122 } else if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR &&
1123 Value.getValueType().bitsGE(MVT::i32)) {
1124 // Convert pointer from byte address to dword address.
1125 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(),
1126 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
1127 Ptr, DAG.getConstant(2, MVT::i32)));
1129 if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
1130 llvm_unreachable("Truncated and indexed stores not supported yet");
1132 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
1138 EVT ValueVT = Value.getValueType();
1140 if (StoreNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1144 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1145 if (Ret.getNode()) {
1148 // Lowering for indirect addressing
1150 const MachineFunction &MF = DAG.getMachineFunction();
1151 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
1152 getTargetMachine().getFrameLowering());
1153 unsigned StackWidth = TFL->getStackWidth(MF);
1155 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1157 if (ValueVT.isVector()) {
1158 unsigned NumElemVT = ValueVT.getVectorNumElements();
1159 EVT ElemVT = ValueVT.getVectorElementType();
1160 SmallVector<SDValue, 4> Stores(NumElemVT);
1162 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1163 "vector width in load");
1165 for (unsigned i = 0; i < NumElemVT; ++i) {
1166 unsigned Channel, PtrIncr;
1167 getStackAddress(StackWidth, i, Channel, PtrIncr);
1168 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1169 DAG.getConstant(PtrIncr, MVT::i32));
1170 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
1171 Value, DAG.getConstant(i, MVT::i32));
1173 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1175 DAG.getTargetConstant(Channel, MVT::i32));
1177 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores);
1179 if (ValueVT == MVT::i8) {
1180 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
1182 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
1183 DAG.getTargetConstant(0, MVT::i32)); // Channel
1189 // return (512 + (kc_bank << 12)
1191 ConstantAddressBlock(unsigned AddressSpace) {
1192 switch (AddressSpace) {
1193 case AMDGPUAS::CONSTANT_BUFFER_0:
1195 case AMDGPUAS::CONSTANT_BUFFER_1:
1197 case AMDGPUAS::CONSTANT_BUFFER_2:
1198 return 512 + 4096 * 2;
1199 case AMDGPUAS::CONSTANT_BUFFER_3:
1200 return 512 + 4096 * 3;
1201 case AMDGPUAS::CONSTANT_BUFFER_4:
1202 return 512 + 4096 * 4;
1203 case AMDGPUAS::CONSTANT_BUFFER_5:
1204 return 512 + 4096 * 5;
1205 case AMDGPUAS::CONSTANT_BUFFER_6:
1206 return 512 + 4096 * 6;
1207 case AMDGPUAS::CONSTANT_BUFFER_7:
1208 return 512 + 4096 * 7;
1209 case AMDGPUAS::CONSTANT_BUFFER_8:
1210 return 512 + 4096 * 8;
1211 case AMDGPUAS::CONSTANT_BUFFER_9:
1212 return 512 + 4096 * 9;
1213 case AMDGPUAS::CONSTANT_BUFFER_10:
1214 return 512 + 4096 * 10;
1215 case AMDGPUAS::CONSTANT_BUFFER_11:
1216 return 512 + 4096 * 11;
1217 case AMDGPUAS::CONSTANT_BUFFER_12:
1218 return 512 + 4096 * 12;
1219 case AMDGPUAS::CONSTANT_BUFFER_13:
1220 return 512 + 4096 * 13;
1221 case AMDGPUAS::CONSTANT_BUFFER_14:
1222 return 512 + 4096 * 14;
1223 case AMDGPUAS::CONSTANT_BUFFER_15:
1224 return 512 + 4096 * 15;
1230 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
1232 EVT VT = Op.getValueType();
1234 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1235 SDValue Chain = Op.getOperand(0);
1236 SDValue Ptr = Op.getOperand(1);
1237 SDValue LoweredLoad;
1239 SDValue Ret = AMDGPUTargetLowering::LowerLOAD(Op, DAG);
1240 if (Ret.getNode()) {
1245 return DAG.getMergeValues(Ops, DL);
1249 if (LoadNode->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS && VT.isVector()) {
1250 SDValue MergedValues[2] = {
1251 SplitVectorLoad(Op, DAG),
1254 return DAG.getMergeValues(MergedValues, DL);
1257 int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
1258 if (ConstantBlock > -1 &&
1259 ((LoadNode->getExtensionType() == ISD::NON_EXTLOAD) ||
1260 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) {
1262 if (isa<ConstantExpr>(LoadNode->getMemOperand()->getValue()) ||
1263 isa<Constant>(LoadNode->getMemOperand()->getValue()) ||
1264 isa<ConstantSDNode>(Ptr)) {
1266 for (unsigned i = 0; i < 4; i++) {
1267 // We want Const position encoded with the following formula :
1268 // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
1269 // const_index is Ptr computed by llvm using an alignment of 16.
1270 // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
1271 // then div by 4 at the ISel step
1272 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1273 DAG.getConstant(4 * i + ConstantBlock * 16, MVT::i32));
1274 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1276 EVT NewVT = MVT::v4i32;
1277 unsigned NumElements = 4;
1278 if (VT.isVector()) {
1280 NumElements = VT.getVectorNumElements();
1282 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT,
1283 makeArrayRef(Slots, NumElements));
1285 // non-constant ptr can't be folded, keeps it as a v4f32 load
1286 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
1287 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
1288 DAG.getConstant(LoadNode->getAddressSpace() -
1289 AMDGPUAS::CONSTANT_BUFFER_0, MVT::i32)
1293 if (!VT.isVector()) {
1294 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1295 DAG.getConstant(0, MVT::i32));
1298 SDValue MergedValues[2] = {
1302 return DAG.getMergeValues(MergedValues, DL);
1305 // For most operations returning SDValue() will result in the node being
1306 // expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so we
1307 // need to manually expand loads that may be legal in some address spaces and
1308 // illegal in others. SEXT loads from CONSTANT_BUFFER_0 are supported for
1309 // compute shaders, since the data is sign extended when it is uploaded to the
1310 // buffer. However SEXT loads from other address spaces are not supported, so
1311 // we need to expand them here.
1312 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
1313 EVT MemVT = LoadNode->getMemoryVT();
1314 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
1315 SDValue ShiftAmount =
1316 DAG.getConstant(VT.getSizeInBits() - MemVT.getSizeInBits(), MVT::i32);
1317 SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr,
1318 LoadNode->getPointerInfo(), MemVT,
1319 LoadNode->isVolatile(),
1320 LoadNode->isNonTemporal(),
1321 LoadNode->getAlignment());
1322 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, NewLoad, ShiftAmount);
1323 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Shl, ShiftAmount);
1325 SDValue MergedValues[2] = { Sra, Chain };
1326 return DAG.getMergeValues(MergedValues, DL);
1329 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1333 // Lowering for indirect addressing
1334 const MachineFunction &MF = DAG.getMachineFunction();
1335 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
1336 getTargetMachine().getFrameLowering());
1337 unsigned StackWidth = TFL->getStackWidth(MF);
1339 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1341 if (VT.isVector()) {
1342 unsigned NumElemVT = VT.getVectorNumElements();
1343 EVT ElemVT = VT.getVectorElementType();
1346 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1347 "vector width in load");
1349 for (unsigned i = 0; i < NumElemVT; ++i) {
1350 unsigned Channel, PtrIncr;
1351 getStackAddress(StackWidth, i, Channel, PtrIncr);
1352 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1353 DAG.getConstant(PtrIncr, MVT::i32));
1354 Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT,
1356 DAG.getTargetConstant(Channel, MVT::i32),
1359 for (unsigned i = NumElemVT; i < 4; ++i) {
1360 Loads[i] = DAG.getUNDEF(ElemVT);
1362 EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4);
1363 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads);
1365 LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
1367 DAG.getTargetConstant(0, MVT::i32), // Channel
1376 return DAG.getMergeValues(Ops, DL);
1379 /// XXX Only kernel functions are supported, so we can assume for now that
1380 /// every function is a kernel function, but in the future we should use
1381 /// separate calling conventions for kernel and non-kernel functions.
1382 SDValue R600TargetLowering::LowerFormalArguments(
1384 CallingConv::ID CallConv,
1386 const SmallVectorImpl<ISD::InputArg> &Ins,
1387 SDLoc DL, SelectionDAG &DAG,
1388 SmallVectorImpl<SDValue> &InVals) const {
1389 SmallVector<CCValAssign, 16> ArgLocs;
1390 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1391 getTargetMachine(), ArgLocs, *DAG.getContext());
1392 MachineFunction &MF = DAG.getMachineFunction();
1393 unsigned ShaderType = MF.getInfo<R600MachineFunctionInfo>()->ShaderType;
1395 SmallVector<ISD::InputArg, 8> LocalIns;
1397 getOriginalFunctionArgs(DAG, MF.getFunction(), Ins, LocalIns);
1399 AnalyzeFormalArguments(CCInfo, LocalIns);
1401 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1402 CCValAssign &VA = ArgLocs[i];
1404 EVT MemVT = LocalIns[i].VT;
1406 if (ShaderType != ShaderType::COMPUTE) {
1407 unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass);
1408 SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT);
1409 InVals.push_back(Register);
1413 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1414 AMDGPUAS::CONSTANT_BUFFER_0);
1416 // i64 isn't a legal type, so the register type used ends up as i32, which
1417 // isn't expected here. It attempts to create this sextload, but it ends up
1418 // being invalid. Somehow this seems to work with i64 arguments, but breaks
1421 // The first 36 bytes of the input buffer contains information about
1422 // thread group and global sizes.
1424 // FIXME: This should really check the extload type, but the handling of
1425 // extload vecto parameters seems to be broken.
1426 //ISD::LoadExtType Ext = Ins[i].Flags.isSExt() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
1427 ISD::LoadExtType Ext = ISD::SEXTLOAD;
1428 SDValue Arg = DAG.getExtLoad(Ext, DL, VT, Chain,
1429 DAG.getConstant(36 + VA.getLocMemOffset(), MVT::i32),
1430 MachinePointerInfo(UndefValue::get(PtrTy)),
1431 MemVT, false, false, 4);
1433 // 4 is the preferred alignment for the CONSTANT memory space.
1434 InVals.push_back(Arg);
1439 EVT R600TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1442 return VT.changeVectorElementTypeToInteger();
1445 static SDValue CompactSwizzlableVector(
1446 SelectionDAG &DAG, SDValue VectorEntry,
1447 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1448 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1449 assert(RemapSwizzle.empty());
1450 SDValue NewBldVec[4] = {
1451 VectorEntry.getOperand(0),
1452 VectorEntry.getOperand(1),
1453 VectorEntry.getOperand(2),
1454 VectorEntry.getOperand(3)
1457 for (unsigned i = 0; i < 4; i++) {
1458 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1459 // We mask write here to teach later passes that the ith element of this
1460 // vector is undef. Thus we can use it to reduce 128 bits reg usage,
1461 // break false dependencies and additionnaly make assembly easier to read.
1462 RemapSwizzle[i] = 7; // SEL_MASK_WRITE
1463 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(NewBldVec[i])) {
1465 RemapSwizzle[i] = 4; // SEL_0
1466 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1467 } else if (C->isExactlyValue(1.0)) {
1468 RemapSwizzle[i] = 5; // SEL_1
1469 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1473 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1475 for (unsigned j = 0; j < i; j++) {
1476 if (NewBldVec[i] == NewBldVec[j]) {
1477 NewBldVec[i] = DAG.getUNDEF(NewBldVec[i].getValueType());
1478 RemapSwizzle[i] = j;
1484 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1485 VectorEntry.getValueType(), NewBldVec);
1488 static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
1489 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1490 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1491 assert(RemapSwizzle.empty());
1492 SDValue NewBldVec[4] = {
1493 VectorEntry.getOperand(0),
1494 VectorEntry.getOperand(1),
1495 VectorEntry.getOperand(2),
1496 VectorEntry.getOperand(3)
1498 bool isUnmovable[4] = { false, false, false, false };
1499 for (unsigned i = 0; i < 4; i++) {
1500 RemapSwizzle[i] = i;
1501 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1502 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1505 isUnmovable[Idx] = true;
1509 for (unsigned i = 0; i < 4; i++) {
1510 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1511 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1513 if (isUnmovable[Idx])
1516 std::swap(NewBldVec[Idx], NewBldVec[i]);
1517 std::swap(RemapSwizzle[i], RemapSwizzle[Idx]);
1522 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1523 VectorEntry.getValueType(), NewBldVec);
1527 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector,
1528 SDValue Swz[4], SelectionDAG &DAG) const {
1529 assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR);
1530 // Old -> New swizzle values
1531 DenseMap<unsigned, unsigned> SwizzleRemap;
1533 BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap);
1534 for (unsigned i = 0; i < 4; i++) {
1535 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1536 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1537 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1540 SwizzleRemap.clear();
1541 BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap);
1542 for (unsigned i = 0; i < 4; i++) {
1543 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1544 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1545 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1552 //===----------------------------------------------------------------------===//
1553 // Custom DAG Optimizations
1554 //===----------------------------------------------------------------------===//
1556 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1557 DAGCombinerInfo &DCI) const {
1558 SelectionDAG &DAG = DCI.DAG;
1560 switch (N->getOpcode()) {
1561 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1562 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1563 case ISD::FP_ROUND: {
1564 SDValue Arg = N->getOperand(0);
1565 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1566 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), N->getValueType(0),
1572 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1573 // (i32 select_cc f32, f32, -1, 0 cc)
1575 // Mesa's GLSL frontend generates the above pattern a lot and we can lower
1576 // this to one of the SET*_DX10 instructions.
1577 case ISD::FP_TO_SINT: {
1578 SDValue FNeg = N->getOperand(0);
1579 if (FNeg.getOpcode() != ISD::FNEG) {
1582 SDValue SelectCC = FNeg.getOperand(0);
1583 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1584 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1585 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1586 !isHWTrueValue(SelectCC.getOperand(2)) ||
1587 !isHWFalseValue(SelectCC.getOperand(3))) {
1591 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
1592 SelectCC.getOperand(0), // LHS
1593 SelectCC.getOperand(1), // RHS
1594 DAG.getConstant(-1, MVT::i32), // True
1595 DAG.getConstant(0, MVT::i32), // Flase
1596 SelectCC.getOperand(4)); // CC
1601 // insert_vector_elt (build_vector elt0, ... , eltN), NewEltIdx, idx
1602 // => build_vector elt0, ... , NewEltIdx, ... , eltN
1603 case ISD::INSERT_VECTOR_ELT: {
1604 SDValue InVec = N->getOperand(0);
1605 SDValue InVal = N->getOperand(1);
1606 SDValue EltNo = N->getOperand(2);
1609 // If the inserted element is an UNDEF, just use the input vector.
1610 if (InVal.getOpcode() == ISD::UNDEF)
1613 EVT VT = InVec.getValueType();
1615 // If we can't generate a legal BUILD_VECTOR, exit
1616 if (!isOperationLegal(ISD::BUILD_VECTOR, VT))
1619 // Check that we know which element is being inserted
1620 if (!isa<ConstantSDNode>(EltNo))
1622 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
1624 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
1625 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
1627 SmallVector<SDValue, 8> Ops;
1628 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
1629 Ops.append(InVec.getNode()->op_begin(),
1630 InVec.getNode()->op_end());
1631 } else if (InVec.getOpcode() == ISD::UNDEF) {
1632 unsigned NElts = VT.getVectorNumElements();
1633 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
1638 // Insert the element
1639 if (Elt < Ops.size()) {
1640 // All the operands of BUILD_VECTOR must have the same type;
1641 // we enforce that here.
1642 EVT OpVT = Ops[0].getValueType();
1643 if (InVal.getValueType() != OpVT)
1644 InVal = OpVT.bitsGT(InVal.getValueType()) ?
1645 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
1646 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
1650 // Return the new vector
1651 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
1654 // Extract_vec (Build_vector) generated by custom lowering
1655 // also needs to be customly combined
1656 case ISD::EXTRACT_VECTOR_ELT: {
1657 SDValue Arg = N->getOperand(0);
1658 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1659 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1660 unsigned Element = Const->getZExtValue();
1661 return Arg->getOperand(Element);
1664 if (Arg.getOpcode() == ISD::BITCAST &&
1665 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1666 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1667 unsigned Element = Const->getZExtValue();
1668 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getVTList(),
1669 Arg->getOperand(0).getOperand(Element));
1674 case ISD::SELECT_CC: {
1675 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1676 // selectcc x, y, a, b, inv(cc)
1678 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
1679 // selectcc x, y, a, b, cc
1680 SDValue LHS = N->getOperand(0);
1681 if (LHS.getOpcode() != ISD::SELECT_CC) {
1685 SDValue RHS = N->getOperand(1);
1686 SDValue True = N->getOperand(2);
1687 SDValue False = N->getOperand(3);
1688 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1690 if (LHS.getOperand(2).getNode() != True.getNode() ||
1691 LHS.getOperand(3).getNode() != False.getNode() ||
1692 RHS.getNode() != False.getNode()) {
1697 default: return SDValue();
1698 case ISD::SETNE: return LHS;
1700 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
1701 LHSCC = ISD::getSetCCInverse(LHSCC,
1702 LHS.getOperand(0).getValueType().isInteger());
1703 if (DCI.isBeforeLegalizeOps() ||
1704 isCondCodeLegal(LHSCC, LHS.getOperand(0).getSimpleValueType()))
1705 return DAG.getSelectCC(SDLoc(N),
1717 case AMDGPUISD::EXPORT: {
1718 SDValue Arg = N->getOperand(1);
1719 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1722 SDValue NewArgs[8] = {
1723 N->getOperand(0), // Chain
1725 N->getOperand(2), // ArrayBase
1726 N->getOperand(3), // Type
1727 N->getOperand(4), // SWZ_X
1728 N->getOperand(5), // SWZ_Y
1729 N->getOperand(6), // SWZ_Z
1730 N->getOperand(7) // SWZ_W
1733 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG);
1734 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs);
1736 case AMDGPUISD::TEXTURE_FETCH: {
1737 SDValue Arg = N->getOperand(1);
1738 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1741 SDValue NewArgs[19] = {
1762 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG);
1763 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, SDLoc(N), N->getVTList(),
1771 FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src, SDValue &Neg,
1772 SDValue &Abs, SDValue &Sel, SDValue &Imm, SelectionDAG &DAG) {
1773 const R600InstrInfo *TII =
1774 static_cast<const R600InstrInfo *>(DAG.getTarget().getInstrInfo());
1775 if (!Src.isMachineOpcode())
1777 switch (Src.getMachineOpcode()) {
1778 case AMDGPU::FNEG_R600:
1781 Src = Src.getOperand(0);
1782 Neg = DAG.getTargetConstant(1, MVT::i32);
1784 case AMDGPU::FABS_R600:
1787 Src = Src.getOperand(0);
1788 Abs = DAG.getTargetConstant(1, MVT::i32);
1790 case AMDGPU::CONST_COPY: {
1791 unsigned Opcode = ParentNode->getMachineOpcode();
1792 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
1797 SDValue CstOffset = Src.getOperand(0);
1798 if (ParentNode->getValueType(0).isVector())
1801 // Gather constants values
1802 int SrcIndices[] = {
1803 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
1804 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
1805 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2),
1806 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
1807 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
1808 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
1809 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
1810 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
1811 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
1812 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
1813 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
1815 std::vector<unsigned> Consts;
1816 for (unsigned i = 0; i < sizeof(SrcIndices) / sizeof(int); i++) {
1817 int OtherSrcIdx = SrcIndices[i];
1818 int OtherSelIdx = TII->getSelIdx(Opcode, OtherSrcIdx);
1819 if (OtherSrcIdx < 0 || OtherSelIdx < 0)
1825 if (RegisterSDNode *Reg =
1826 dyn_cast<RegisterSDNode>(ParentNode->getOperand(OtherSrcIdx))) {
1827 if (Reg->getReg() == AMDGPU::ALU_CONST) {
1828 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(
1829 ParentNode->getOperand(OtherSelIdx));
1830 Consts.push_back(Cst->getZExtValue());
1835 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(CstOffset);
1836 Consts.push_back(Cst->getZExtValue());
1837 if (!TII->fitsConstReadLimitations(Consts)) {
1842 Src = DAG.getRegister(AMDGPU::ALU_CONST, MVT::f32);
1845 case AMDGPU::MOV_IMM_I32:
1846 case AMDGPU::MOV_IMM_F32: {
1847 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
1848 uint64_t ImmValue = 0;
1851 if (Src.getMachineOpcode() == AMDGPU::MOV_IMM_F32) {
1852 ConstantFPSDNode *FPC = dyn_cast<ConstantFPSDNode>(Src.getOperand(0));
1853 float FloatValue = FPC->getValueAPF().convertToFloat();
1854 if (FloatValue == 0.0) {
1855 ImmReg = AMDGPU::ZERO;
1856 } else if (FloatValue == 0.5) {
1857 ImmReg = AMDGPU::HALF;
1858 } else if (FloatValue == 1.0) {
1859 ImmReg = AMDGPU::ONE;
1861 ImmValue = FPC->getValueAPF().bitcastToAPInt().getZExtValue();
1864 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src.getOperand(0));
1865 uint64_t Value = C->getZExtValue();
1867 ImmReg = AMDGPU::ZERO;
1868 } else if (Value == 1) {
1869 ImmReg = AMDGPU::ONE_INT;
1875 // Check that we aren't already using an immediate.
1876 // XXX: It's possible for an instruction to have more than one
1877 // immediate operand, but this is not supported yet.
1878 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
1881 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Imm);
1883 if (C->getZExtValue())
1885 Imm = DAG.getTargetConstant(ImmValue, MVT::i32);
1887 Src = DAG.getRegister(ImmReg, MVT::i32);
1896 /// \brief Fold the instructions after selecting them
1897 SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node,
1898 SelectionDAG &DAG) const {
1899 const R600InstrInfo *TII =
1900 static_cast<const R600InstrInfo *>(DAG.getTarget().getInstrInfo());
1901 if (!Node->isMachineOpcode())
1903 unsigned Opcode = Node->getMachineOpcode();
1906 std::vector<SDValue> Ops;
1907 for(SDNode::op_iterator I = Node->op_begin(), E = Node->op_end();
1911 if (Opcode == AMDGPU::DOT_4) {
1912 int OperandIdx[] = {
1913 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
1914 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
1915 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
1916 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
1917 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
1918 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
1919 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
1920 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
1923 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_X),
1924 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Y),
1925 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Z),
1926 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_W),
1927 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_X),
1928 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Y),
1929 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Z),
1930 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_W)
1933 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_X),
1934 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Y),
1935 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Z),
1936 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_W),
1937 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_X),
1938 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Y),
1939 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Z),
1940 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_W)
1942 for (unsigned i = 0; i < 8; i++) {
1943 if (OperandIdx[i] < 0)
1945 SDValue &Src = Ops[OperandIdx[i] - 1];
1946 SDValue &Neg = Ops[NegIdx[i] - 1];
1947 SDValue &Abs = Ops[AbsIdx[i] - 1];
1948 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
1949 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
1952 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
1953 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, FakeOp, DAG))
1954 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
1956 } else if (Opcode == AMDGPU::REG_SEQUENCE) {
1957 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) {
1958 SDValue &Src = Ops[i];
1959 if (FoldOperand(Node, i, Src, FakeOp, FakeOp, FakeOp, FakeOp, DAG))
1960 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
1962 } else if (Opcode == AMDGPU::CLAMP_R600) {
1963 SDValue Src = Node->getOperand(0);
1964 if (!Src.isMachineOpcode() ||
1965 !TII->hasInstrModifiers(Src.getMachineOpcode()))
1967 int ClampIdx = TII->getOperandIdx(Src.getMachineOpcode(),
1968 AMDGPU::OpName::clamp);
1971 std::vector<SDValue> Ops;
1972 unsigned NumOp = Src.getNumOperands();
1973 for(unsigned i = 0; i < NumOp; ++i)
1974 Ops.push_back(Src.getOperand(i));
1975 Ops[ClampIdx - 1] = DAG.getTargetConstant(1, MVT::i32);
1976 return DAG.getMachineNode(Src.getMachineOpcode(), SDLoc(Node),
1977 Node->getVTList(), Ops);
1979 if (!TII->hasInstrModifiers(Opcode))
1981 int OperandIdx[] = {
1982 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
1983 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
1984 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2)
1987 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg),
1988 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg),
1989 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2_neg)
1992 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs),
1993 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs),
1996 for (unsigned i = 0; i < 3; i++) {
1997 if (OperandIdx[i] < 0)
1999 SDValue &Src = Ops[OperandIdx[i] - 1];
2000 SDValue &Neg = Ops[NegIdx[i] - 1];
2002 SDValue &Abs = (AbsIdx[i] > -1) ? Ops[AbsIdx[i] - 1] : FakeAbs;
2003 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2004 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
2005 int ImmIdx = TII->getOperandIdx(Opcode, AMDGPU::OpName::literal);
2010 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2011 SDValue &Imm = Ops[ImmIdx];
2012 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, Imm, DAG))
2013 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);