1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for R600
13 //===----------------------------------------------------------------------===//
15 #include "R600ISelLowering.h"
16 #include "AMDGPUFrameLowering.h"
17 #include "AMDGPUIntrinsicInfo.h"
18 #include "AMDGPUSubtarget.h"
19 #include "R600Defines.h"
20 #include "R600InstrInfo.h"
21 #include "R600MachineFunctionInfo.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/IR/Argument.h"
29 #include "llvm/IR/Function.h"
33 R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
34 AMDGPUTargetLowering(TM),
35 Gen(TM.getSubtarget<AMDGPUSubtarget>().getGeneration()) {
36 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
37 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
38 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
39 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
40 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
41 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
43 computeRegisterProperties();
45 // Set condition code actions
46 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
47 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
48 setCondCodeAction(ISD::SETLT, MVT::f32, Expand);
49 setCondCodeAction(ISD::SETLE, MVT::f32, Expand);
50 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
51 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
52 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
53 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
54 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
55 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
56 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
57 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
59 setCondCodeAction(ISD::SETLE, MVT::i32, Expand);
60 setCondCodeAction(ISD::SETLT, MVT::i32, Expand);
61 setCondCodeAction(ISD::SETULE, MVT::i32, Expand);
62 setCondCodeAction(ISD::SETULT, MVT::i32, Expand);
64 setOperationAction(ISD::FCOS, MVT::f32, Custom);
65 setOperationAction(ISD::FSIN, MVT::f32, Custom);
67 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
68 setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
70 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
71 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
72 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
74 setOperationAction(ISD::FSUB, MVT::f32, Expand);
76 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
77 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
78 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
80 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
81 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
83 setOperationAction(ISD::SETCC, MVT::i32, Expand);
84 setOperationAction(ISD::SETCC, MVT::f32, Expand);
85 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
86 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
87 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
89 setOperationAction(ISD::SELECT, MVT::i32, Expand);
90 setOperationAction(ISD::SELECT, MVT::f32, Expand);
91 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
92 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
94 // Expand sign extension of vectors
95 if (!Subtarget->hasBFE())
96 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
98 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand);
99 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand);
101 if (!Subtarget->hasBFE())
102 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
103 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand);
104 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand);
106 if (!Subtarget->hasBFE())
107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
108 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand);
109 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
111 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand);
113 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand);
115 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
118 // Legalize loads and stores to the private address space.
119 setOperationAction(ISD::LOAD, MVT::i32, Custom);
120 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
121 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
123 // EXTLOAD should be the same as ZEXTLOAD. It is legal for some address
124 // spaces, so it is custom lowered to handle those where it isn't.
125 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
126 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
127 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
129 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
130 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
131 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
133 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
134 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
135 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Custom);
137 setOperationAction(ISD::STORE, MVT::i8, Custom);
138 setOperationAction(ISD::STORE, MVT::i32, Custom);
139 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
140 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
141 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
142 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
144 setOperationAction(ISD::LOAD, MVT::i32, Custom);
145 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
146 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom);
149 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom);
150 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
151 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
153 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom);
154 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom);
155 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
156 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
158 setTargetDAGCombine(ISD::FP_ROUND);
159 setTargetDAGCombine(ISD::FP_TO_SINT);
160 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
161 setTargetDAGCombine(ISD::SELECT_CC);
162 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
164 setOperationAction(ISD::SUB, MVT::i64, Expand);
166 // These should be replaced by UDVIREM, but it does not happen automatically
167 // during Type Legalization
168 setOperationAction(ISD::UDIV, MVT::i64, Custom);
169 setOperationAction(ISD::UREM, MVT::i64, Custom);
170 setOperationAction(ISD::SDIV, MVT::i64, Custom);
171 setOperationAction(ISD::SREM, MVT::i64, Custom);
173 // We don't have 64-bit shifts. Thus we need either SHX i64 or SHX_PARTS i32
174 // to be Legal/Custom in order to avoid library calls.
175 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
176 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
177 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
179 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
181 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
182 for (MVT VT : ScalarIntVTs) {
183 setOperationAction(ISD::ADDC, VT, Expand);
184 setOperationAction(ISD::SUBC, VT, Expand);
185 setOperationAction(ISD::ADDE, VT, Expand);
186 setOperationAction(ISD::SUBE, VT, Expand);
189 setSchedulingPreference(Sched::Source);
192 MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
193 MachineInstr * MI, MachineBasicBlock * BB) const {
194 MachineFunction * MF = BB->getParent();
195 MachineRegisterInfo &MRI = MF->getRegInfo();
196 MachineBasicBlock::iterator I = *MI;
197 const R600InstrInfo *TII =
198 static_cast<const R600InstrInfo *>(MF->getSubtarget().getInstrInfo());
200 switch (MI->getOpcode()) {
202 // Replace LDS_*_RET instruction that don't have any uses with the
203 // equivalent LDS_*_NORET instruction.
204 if (TII->isLDSRetInstr(MI->getOpcode())) {
205 int DstIdx = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
206 assert(DstIdx != -1);
207 MachineInstrBuilder NewMI;
208 // FIXME: getLDSNoRetOp method only handles LDS_1A1D LDS ops. Add
209 // LDS_1A2D support and remove this special case.
210 if (!MRI.use_empty(MI->getOperand(DstIdx).getReg()) ||
211 MI->getOpcode() == AMDGPU::LDS_CMPST_RET)
214 NewMI = BuildMI(*BB, I, BB->findDebugLoc(I),
215 TII->get(AMDGPU::getLDSNoRetOp(MI->getOpcode())));
216 for (unsigned i = 1, e = MI->getNumOperands(); i < e; ++i) {
217 NewMI.addOperand(MI->getOperand(i));
220 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
223 case AMDGPU::CLAMP_R600: {
224 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
226 MI->getOperand(0).getReg(),
227 MI->getOperand(1).getReg());
228 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
232 case AMDGPU::FABS_R600: {
233 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
235 MI->getOperand(0).getReg(),
236 MI->getOperand(1).getReg());
237 TII->addFlag(NewMI, 0, MO_FLAG_ABS);
241 case AMDGPU::FNEG_R600: {
242 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
244 MI->getOperand(0).getReg(),
245 MI->getOperand(1).getReg());
246 TII->addFlag(NewMI, 0, MO_FLAG_NEG);
250 case AMDGPU::MASK_WRITE: {
251 unsigned maskedRegister = MI->getOperand(0).getReg();
252 assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
253 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
254 TII->addFlag(defInstr, 0, MO_FLAG_MASK);
258 case AMDGPU::MOV_IMM_F32:
259 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
260 MI->getOperand(1).getFPImm()->getValueAPF()
261 .bitcastToAPInt().getZExtValue());
263 case AMDGPU::MOV_IMM_I32:
264 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
265 MI->getOperand(1).getImm());
267 case AMDGPU::CONST_COPY: {
268 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
269 MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
270 TII->setImmOperand(NewMI, AMDGPU::OpName::src0_sel,
271 MI->getOperand(1).getImm());
275 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
276 case AMDGPU::RAT_WRITE_CACHELESS_64_eg:
277 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
278 unsigned EOP = (std::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
280 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
281 .addOperand(MI->getOperand(0))
282 .addOperand(MI->getOperand(1))
283 .addImm(EOP); // Set End of program bit
288 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
289 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
290 MachineOperand &RID = MI->getOperand(4);
291 MachineOperand &SID = MI->getOperand(5);
292 unsigned TextureId = MI->getOperand(6).getImm();
293 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
294 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
306 case 8: // ShadowRect
317 case 11: // Shadow1DArray
321 case 12: // Shadow2DArray
325 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
326 .addOperand(MI->getOperand(3))
344 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
345 .addOperand(MI->getOperand(2))
363 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
364 .addOperand(MI->getOperand(0))
365 .addOperand(MI->getOperand(1))
383 .addReg(T0, RegState::Implicit)
384 .addReg(T1, RegState::Implicit);
388 case AMDGPU::TXD_SHADOW: {
389 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
390 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
391 MachineOperand &RID = MI->getOperand(4);
392 MachineOperand &SID = MI->getOperand(5);
393 unsigned TextureId = MI->getOperand(6).getImm();
394 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
395 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
407 case 8: // ShadowRect
418 case 11: // Shadow1DArray
422 case 12: // Shadow2DArray
427 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
428 .addOperand(MI->getOperand(3))
446 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
447 .addOperand(MI->getOperand(2))
465 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
466 .addOperand(MI->getOperand(0))
467 .addOperand(MI->getOperand(1))
485 .addReg(T0, RegState::Implicit)
486 .addReg(T1, RegState::Implicit);
491 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
492 .addOperand(MI->getOperand(0));
495 case AMDGPU::BRANCH_COND_f32: {
496 MachineInstr *NewMI =
497 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
498 AMDGPU::PREDICATE_BIT)
499 .addOperand(MI->getOperand(1))
500 .addImm(OPCODE_IS_NOT_ZERO)
502 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
503 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
504 .addOperand(MI->getOperand(0))
505 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
509 case AMDGPU::BRANCH_COND_i32: {
510 MachineInstr *NewMI =
511 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
512 AMDGPU::PREDICATE_BIT)
513 .addOperand(MI->getOperand(1))
514 .addImm(OPCODE_IS_NOT_ZERO_INT)
516 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
517 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
518 .addOperand(MI->getOperand(0))
519 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
523 case AMDGPU::EG_ExportSwz:
524 case AMDGPU::R600_ExportSwz: {
525 // Instruction is left unmodified if its not the last one of its type
526 bool isLastInstructionOfItsType = true;
527 unsigned InstExportType = MI->getOperand(1).getImm();
528 for (MachineBasicBlock::iterator NextExportInst = std::next(I),
529 EndBlock = BB->end(); NextExportInst != EndBlock;
530 NextExportInst = std::next(NextExportInst)) {
531 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
532 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
533 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
535 if (CurrentInstExportType == InstExportType) {
536 isLastInstructionOfItsType = false;
541 bool EOP = (std::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
542 if (!EOP && !isLastInstructionOfItsType)
544 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
545 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
546 .addOperand(MI->getOperand(0))
547 .addOperand(MI->getOperand(1))
548 .addOperand(MI->getOperand(2))
549 .addOperand(MI->getOperand(3))
550 .addOperand(MI->getOperand(4))
551 .addOperand(MI->getOperand(5))
552 .addOperand(MI->getOperand(6))
557 case AMDGPU::RETURN: {
558 // RETURN instructions must have the live-out registers as implicit uses,
559 // otherwise they appear dead.
560 R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
561 MachineInstrBuilder MIB(*MF, MI);
562 for (unsigned i = 0, e = MFI->LiveOuts.size(); i != e; ++i)
563 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
568 MI->eraseFromParent();
572 //===----------------------------------------------------------------------===//
573 // Custom DAG Lowering Operations
574 //===----------------------------------------------------------------------===//
576 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
577 MachineFunction &MF = DAG.getMachineFunction();
578 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
579 switch (Op.getOpcode()) {
580 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
581 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
582 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
583 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
585 case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG);
587 case ISD::FSIN: return LowerTrig(Op, DAG);
588 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
589 case ISD::STORE: return LowerSTORE(Op, DAG);
591 SDValue Result = LowerLOAD(Op, DAG);
592 assert((!Result.getNode() ||
593 Result.getNode()->getNumValues() == 2) &&
594 "Load should return a value and a chain");
598 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
599 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
600 case ISD::INTRINSIC_VOID: {
601 SDValue Chain = Op.getOperand(0);
602 unsigned IntrinsicID =
603 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
604 switch (IntrinsicID) {
605 case AMDGPUIntrinsic::AMDGPU_store_output: {
606 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
607 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
608 MFI->LiveOuts.push_back(Reg);
609 return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2));
611 case AMDGPUIntrinsic::R600_store_swizzle: {
612 const SDValue Args[8] = {
614 Op.getOperand(2), // Export Value
615 Op.getOperand(3), // ArrayBase
616 Op.getOperand(4), // Type
617 DAG.getConstant(0, MVT::i32), // SWZ_X
618 DAG.getConstant(1, MVT::i32), // SWZ_Y
619 DAG.getConstant(2, MVT::i32), // SWZ_Z
620 DAG.getConstant(3, MVT::i32) // SWZ_W
622 return DAG.getNode(AMDGPUISD::EXPORT, SDLoc(Op), Op.getValueType(), Args);
625 // default for switch(IntrinsicID)
628 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
631 case ISD::INTRINSIC_WO_CHAIN: {
632 unsigned IntrinsicID =
633 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
634 EVT VT = Op.getValueType();
636 switch(IntrinsicID) {
637 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
638 case AMDGPUIntrinsic::R600_load_input: {
639 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
640 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
641 MachineFunction &MF = DAG.getMachineFunction();
642 MachineRegisterInfo &MRI = MF.getRegInfo();
644 return DAG.getCopyFromReg(DAG.getEntryNode(),
645 SDLoc(DAG.getEntryNode()), Reg, VT);
648 case AMDGPUIntrinsic::R600_interp_input: {
649 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
650 int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
651 MachineSDNode *interp;
653 const MachineFunction &MF = DAG.getMachineFunction();
654 const R600InstrInfo *TII = static_cast<const R600InstrInfo *>(
655 MF.getSubtarget().getInstrInfo());
656 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
657 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
658 return DAG.getTargetExtractSubreg(
659 TII->getRegisterInfo().getSubRegFromChannel(slot % 4),
660 DL, MVT::f32, SDValue(interp, 0));
662 MachineFunction &MF = DAG.getMachineFunction();
663 MachineRegisterInfo &MRI = MF.getRegInfo();
664 unsigned RegisterI = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb);
665 unsigned RegisterJ = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1);
666 MRI.addLiveIn(RegisterI);
667 MRI.addLiveIn(RegisterJ);
668 SDValue RegisterINode = DAG.getCopyFromReg(DAG.getEntryNode(),
669 SDLoc(DAG.getEntryNode()), RegisterI, MVT::f32);
670 SDValue RegisterJNode = DAG.getCopyFromReg(DAG.getEntryNode(),
671 SDLoc(DAG.getEntryNode()), RegisterJ, MVT::f32);
674 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
675 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
676 RegisterJNode, RegisterINode);
678 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
679 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
680 RegisterJNode, RegisterINode);
681 return SDValue(interp, slot % 2);
683 case AMDGPUIntrinsic::R600_interp_xy:
684 case AMDGPUIntrinsic::R600_interp_zw: {
685 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
686 MachineSDNode *interp;
687 SDValue RegisterINode = Op.getOperand(2);
688 SDValue RegisterJNode = Op.getOperand(3);
690 if (IntrinsicID == AMDGPUIntrinsic::R600_interp_xy)
691 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
692 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, MVT::i32),
693 RegisterJNode, RegisterINode);
695 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
696 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, MVT::i32),
697 RegisterJNode, RegisterINode);
698 return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32,
699 SDValue(interp, 0), SDValue(interp, 1));
701 case AMDGPUIntrinsic::R600_tex:
702 case AMDGPUIntrinsic::R600_texc:
703 case AMDGPUIntrinsic::R600_txl:
704 case AMDGPUIntrinsic::R600_txlc:
705 case AMDGPUIntrinsic::R600_txb:
706 case AMDGPUIntrinsic::R600_txbc:
707 case AMDGPUIntrinsic::R600_txf:
708 case AMDGPUIntrinsic::R600_txq:
709 case AMDGPUIntrinsic::R600_ddx:
710 case AMDGPUIntrinsic::R600_ddy:
711 case AMDGPUIntrinsic::R600_ldptr: {
713 switch (IntrinsicID) {
714 case AMDGPUIntrinsic::R600_tex:
717 case AMDGPUIntrinsic::R600_texc:
720 case AMDGPUIntrinsic::R600_txl:
723 case AMDGPUIntrinsic::R600_txlc:
726 case AMDGPUIntrinsic::R600_txb:
729 case AMDGPUIntrinsic::R600_txbc:
732 case AMDGPUIntrinsic::R600_txf:
735 case AMDGPUIntrinsic::R600_txq:
738 case AMDGPUIntrinsic::R600_ddx:
741 case AMDGPUIntrinsic::R600_ddy:
744 case AMDGPUIntrinsic::R600_ldptr:
748 llvm_unreachable("Unknow Texture Operation");
751 SDValue TexArgs[19] = {
752 DAG.getConstant(TextureOp, MVT::i32),
754 DAG.getConstant(0, MVT::i32),
755 DAG.getConstant(1, MVT::i32),
756 DAG.getConstant(2, MVT::i32),
757 DAG.getConstant(3, MVT::i32),
761 DAG.getConstant(0, MVT::i32),
762 DAG.getConstant(1, MVT::i32),
763 DAG.getConstant(2, MVT::i32),
764 DAG.getConstant(3, MVT::i32),
772 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs);
774 case AMDGPUIntrinsic::AMDGPU_dp4: {
776 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
777 DAG.getConstant(0, MVT::i32)),
778 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
779 DAG.getConstant(0, MVT::i32)),
780 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
781 DAG.getConstant(1, MVT::i32)),
782 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
783 DAG.getConstant(1, MVT::i32)),
784 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
785 DAG.getConstant(2, MVT::i32)),
786 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
787 DAG.getConstant(2, MVT::i32)),
788 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
789 DAG.getConstant(3, MVT::i32)),
790 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
791 DAG.getConstant(3, MVT::i32))
793 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args);
796 case Intrinsic::r600_read_ngroups_x:
797 return LowerImplicitParameter(DAG, VT, DL, 0);
798 case Intrinsic::r600_read_ngroups_y:
799 return LowerImplicitParameter(DAG, VT, DL, 1);
800 case Intrinsic::r600_read_ngroups_z:
801 return LowerImplicitParameter(DAG, VT, DL, 2);
802 case Intrinsic::r600_read_global_size_x:
803 return LowerImplicitParameter(DAG, VT, DL, 3);
804 case Intrinsic::r600_read_global_size_y:
805 return LowerImplicitParameter(DAG, VT, DL, 4);
806 case Intrinsic::r600_read_global_size_z:
807 return LowerImplicitParameter(DAG, VT, DL, 5);
808 case Intrinsic::r600_read_local_size_x:
809 return LowerImplicitParameter(DAG, VT, DL, 6);
810 case Intrinsic::r600_read_local_size_y:
811 return LowerImplicitParameter(DAG, VT, DL, 7);
812 case Intrinsic::r600_read_local_size_z:
813 return LowerImplicitParameter(DAG, VT, DL, 8);
815 case Intrinsic::AMDGPU_read_workdim:
816 return LowerImplicitParameter(DAG, VT, DL, MFI->ABIArgOffset / 4);
818 case Intrinsic::r600_read_tgid_x:
819 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
821 case Intrinsic::r600_read_tgid_y:
822 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
824 case Intrinsic::r600_read_tgid_z:
825 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
827 case Intrinsic::r600_read_tidig_x:
828 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
830 case Intrinsic::r600_read_tidig_y:
831 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
833 case Intrinsic::r600_read_tidig_z:
834 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
836 case Intrinsic::AMDGPU_rsq:
837 // XXX - I'm assuming SI's RSQ_LEGACY matches R600's behavior.
838 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
840 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
843 } // end switch(Op.getOpcode())
847 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
848 SmallVectorImpl<SDValue> &Results,
849 SelectionDAG &DAG) const {
850 switch (N->getOpcode()) {
852 AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG);
854 case ISD::FP_TO_UINT:
855 if (N->getValueType(0) == MVT::i1) {
856 Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
859 // Fall-through. Since we don't care about out of bounds values
860 // we can use FP_TO_SINT for uints too. The DAGLegalizer code for uint
861 // considers some extra cases which are not necessary here.
862 case ISD::FP_TO_SINT: {
864 if (expandFP_TO_SINT(N, Result, DAG))
865 Results.push_back(Result);
869 SDValue Op = SDValue(N, 0);
871 EVT VT = Op.getValueType();
872 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
873 N->getOperand(0), N->getOperand(1));
874 Results.push_back(UDIVREM);
878 SDValue Op = SDValue(N, 0);
880 EVT VT = Op.getValueType();
881 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
882 N->getOperand(0), N->getOperand(1));
883 Results.push_back(UDIVREM.getValue(1));
887 SDValue Op = SDValue(N, 0);
889 EVT VT = Op.getValueType();
890 SDValue SDIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(VT, VT),
891 N->getOperand(0), N->getOperand(1));
892 Results.push_back(SDIVREM);
896 SDValue Op = SDValue(N, 0);
898 EVT VT = Op.getValueType();
899 SDValue SDIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(VT, VT),
900 N->getOperand(0), N->getOperand(1));
901 Results.push_back(SDIVREM.getValue(1));
905 SDValue Op = SDValue(N, 1);
906 SDValue RES = LowerSDIVREM(Op, DAG);
907 Results.push_back(RES);
908 Results.push_back(RES.getValue(1));
912 SDValue Op = SDValue(N, 0);
913 LowerUDIVREM64(Op, DAG, Results);
919 SDValue R600TargetLowering::vectorToVerticalVector(SelectionDAG &DAG,
920 SDValue Vector) const {
923 EVT VecVT = Vector.getValueType();
924 EVT EltVT = VecVT.getVectorElementType();
925 SmallVector<SDValue, 8> Args;
927 for (unsigned i = 0, e = VecVT.getVectorNumElements();
929 Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
930 Vector, DAG.getConstant(i, getVectorIdxTy())));
933 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args);
936 SDValue R600TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
937 SelectionDAG &DAG) const {
940 SDValue Vector = Op.getOperand(0);
941 SDValue Index = Op.getOperand(1);
943 if (isa<ConstantSDNode>(Index) ||
944 Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
947 Vector = vectorToVerticalVector(DAG, Vector);
948 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(),
952 SDValue R600TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
953 SelectionDAG &DAG) const {
955 SDValue Vector = Op.getOperand(0);
956 SDValue Value = Op.getOperand(1);
957 SDValue Index = Op.getOperand(2);
959 if (isa<ConstantSDNode>(Index) ||
960 Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
963 Vector = vectorToVerticalVector(DAG, Vector);
964 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(),
965 Vector, Value, Index);
966 return vectorToVerticalVector(DAG, Insert);
969 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
970 // On hw >= R700, COS/SIN input must be between -1. and 1.
971 // Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5)
972 EVT VT = Op.getValueType();
973 SDValue Arg = Op.getOperand(0);
974 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
975 DAG.getNode(ISD::FADD, SDLoc(Op), VT,
976 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
977 DAG.getConstantFP(0.15915494309, MVT::f32)),
978 DAG.getConstantFP(0.5, MVT::f32)));
980 switch (Op.getOpcode()) {
982 TrigNode = AMDGPUISD::COS_HW;
985 TrigNode = AMDGPUISD::SIN_HW;
988 llvm_unreachable("Wrong trig opcode");
990 SDValue TrigVal = DAG.getNode(TrigNode, SDLoc(Op), VT,
991 DAG.getNode(ISD::FADD, SDLoc(Op), VT, FractPart,
992 DAG.getConstantFP(-0.5, MVT::f32)));
993 if (Gen >= AMDGPUSubtarget::R700)
995 // On R600 hw, COS/SIN input must be between -Pi and Pi.
996 return DAG.getNode(ISD::FMUL, SDLoc(Op), VT, TrigVal,
997 DAG.getConstantFP(3.14159265359, MVT::f32));
1000 SDValue R600TargetLowering::LowerSHLParts(SDValue Op, SelectionDAG &DAG) const {
1002 EVT VT = Op.getValueType();
1004 SDValue Lo = Op.getOperand(0);
1005 SDValue Hi = Op.getOperand(1);
1006 SDValue Shift = Op.getOperand(2);
1007 SDValue Zero = DAG.getConstant(0, VT);
1008 SDValue One = DAG.getConstant(1, VT);
1010 SDValue Width = DAG.getConstant(VT.getSizeInBits(), VT);
1011 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, VT);
1012 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
1013 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
1015 // The dance around Width1 is necessary for 0 special case.
1016 // Without it the CompShift might be 32, producing incorrect results in
1017 // Overflow. So we do the shift in two steps, the alternative is to
1018 // add a conditional to filter the special case.
1020 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift);
1021 Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One);
1023 SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift);
1024 HiSmall = DAG.getNode(ISD::OR, DL, VT, HiSmall, Overflow);
1025 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift);
1027 SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift);
1028 SDValue LoBig = Zero;
1030 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
1031 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
1033 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
1036 SDValue R600TargetLowering::LowerSRXParts(SDValue Op, SelectionDAG &DAG) const {
1038 EVT VT = Op.getValueType();
1040 SDValue Lo = Op.getOperand(0);
1041 SDValue Hi = Op.getOperand(1);
1042 SDValue Shift = Op.getOperand(2);
1043 SDValue Zero = DAG.getConstant(0, VT);
1044 SDValue One = DAG.getConstant(1, VT);
1046 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS;
1048 SDValue Width = DAG.getConstant(VT.getSizeInBits(), VT);
1049 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, VT);
1050 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
1051 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
1053 // The dance around Width1 is necessary for 0 special case.
1054 // Without it the CompShift might be 32, producing incorrect results in
1055 // Overflow. So we do the shift in two steps, the alternative is to
1056 // add a conditional to filter the special case.
1058 SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift);
1059 Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One);
1061 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift);
1062 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift);
1063 LoSmall = DAG.getNode(ISD::OR, DL, VT, LoSmall, Overflow);
1065 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift);
1066 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero;
1068 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
1069 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
1071 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
1074 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
1079 Op, DAG.getConstantFP(0.0f, MVT::f32),
1080 DAG.getCondCode(ISD::SETNE)
1084 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
1086 unsigned DwordOffset) const {
1087 unsigned ByteOffset = DwordOffset * 4;
1088 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1089 AMDGPUAS::CONSTANT_BUFFER_0);
1091 // We shouldn't be using an offset wider than 16-bits for implicit parameters.
1092 assert(isInt<16>(ByteOffset));
1094 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
1095 DAG.getConstant(ByteOffset, MVT::i32), // PTR
1096 MachinePointerInfo(ConstantPointerNull::get(PtrType)),
1097 false, false, false, 0);
1100 bool R600TargetLowering::isZero(SDValue Op) const {
1101 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
1102 return Cst->isNullValue();
1103 } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
1104 return CstFP->isZero();
1110 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
1112 EVT VT = Op.getValueType();
1114 SDValue LHS = Op.getOperand(0);
1115 SDValue RHS = Op.getOperand(1);
1116 SDValue True = Op.getOperand(2);
1117 SDValue False = Op.getOperand(3);
1118 SDValue CC = Op.getOperand(4);
1121 if (VT == MVT::f32) {
1122 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr);
1123 SDValue MinMax = CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
1128 // LHS and RHS are guaranteed to be the same value type
1129 EVT CompareVT = LHS.getValueType();
1131 // Check if we can lower this to a native operation.
1133 // Try to lower to a SET* instruction:
1135 // SET* can match the following patterns:
1137 // select_cc f32, f32, -1, 0, cc_supported
1138 // select_cc f32, f32, 1.0f, 0.0f, cc_supported
1139 // select_cc i32, i32, -1, 0, cc_supported
1142 // Move hardware True/False values to the correct operand.
1143 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1144 ISD::CondCode InverseCC =
1145 ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
1146 if (isHWTrueValue(False) && isHWFalseValue(True)) {
1147 if (isCondCodeLegal(InverseCC, CompareVT.getSimpleVT())) {
1148 std::swap(False, True);
1149 CC = DAG.getCondCode(InverseCC);
1151 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InverseCC);
1152 if (isCondCodeLegal(SwapInvCC, CompareVT.getSimpleVT())) {
1153 std::swap(False, True);
1154 std::swap(LHS, RHS);
1155 CC = DAG.getCondCode(SwapInvCC);
1160 if (isHWTrueValue(True) && isHWFalseValue(False) &&
1161 (CompareVT == VT || VT == MVT::i32)) {
1162 // This can be matched by a SET* instruction.
1163 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
1166 // Try to lower to a CND* instruction:
1168 // CND* can match the following patterns:
1170 // select_cc f32, 0.0, f32, f32, cc_supported
1171 // select_cc f32, 0.0, i32, i32, cc_supported
1172 // select_cc i32, 0, f32, f32, cc_supported
1173 // select_cc i32, 0, i32, i32, cc_supported
1176 // Try to move the zero value to the RHS
1178 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1179 // Try swapping the operands
1180 ISD::CondCode CCSwapped = ISD::getSetCCSwappedOperands(CCOpcode);
1181 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
1182 std::swap(LHS, RHS);
1183 CC = DAG.getCondCode(CCSwapped);
1185 // Try inverting the conditon and then swapping the operands
1186 ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT.isInteger());
1187 CCSwapped = ISD::getSetCCSwappedOperands(CCInv);
1188 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
1189 std::swap(True, False);
1190 std::swap(LHS, RHS);
1191 CC = DAG.getCondCode(CCSwapped);
1198 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1199 if (CompareVT != VT) {
1200 // Bitcast True / False to the correct types. This will end up being
1201 // a nop, but it allows us to define only a single pattern in the
1202 // .TD files for each CND* instruction rather than having to have
1203 // one pattern for integer True/False and one for fp True/False
1204 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
1205 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
1212 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
1220 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
1223 DAG.getCondCode(CCOpcode));
1224 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
1227 // If we make it this for it means we have no native instructions to handle
1228 // this SELECT_CC, so we must lower it.
1229 SDValue HWTrue, HWFalse;
1231 if (CompareVT == MVT::f32) {
1232 HWTrue = DAG.getConstantFP(1.0f, CompareVT);
1233 HWFalse = DAG.getConstantFP(0.0f, CompareVT);
1234 } else if (CompareVT == MVT::i32) {
1235 HWTrue = DAG.getConstant(-1, CompareVT);
1236 HWFalse = DAG.getConstant(0, CompareVT);
1239 llvm_unreachable("Unhandled value type in LowerSELECT_CC");
1242 // Lower this unsupported SELECT_CC into a combination of two supported
1243 // SELECT_CC operations.
1244 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
1246 return DAG.getNode(ISD::SELECT_CC, DL, VT,
1249 DAG.getCondCode(ISD::SETNE));
1252 /// LLVM generates byte-addressed pointers. For indirect addressing, we need to
1253 /// convert these pointers to a register index. Each register holds
1254 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
1255 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
1256 /// for indirect addressing.
1257 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
1258 unsigned StackWidth,
1259 SelectionDAG &DAG) const {
1261 switch(StackWidth) {
1271 default: llvm_unreachable("Invalid stack width");
1274 return DAG.getNode(ISD::SRL, SDLoc(Ptr), Ptr.getValueType(), Ptr,
1275 DAG.getConstant(SRLPad, MVT::i32));
1278 void R600TargetLowering::getStackAddress(unsigned StackWidth,
1281 unsigned &PtrIncr) const {
1282 switch (StackWidth) {
1293 Channel = ElemIdx % 2;
1307 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1309 StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
1310 SDValue Chain = Op.getOperand(0);
1311 SDValue Value = Op.getOperand(1);
1312 SDValue Ptr = Op.getOperand(2);
1314 SDValue Result = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1315 if (Result.getNode()) {
1319 if (StoreNode->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS) {
1320 if (StoreNode->isTruncatingStore()) {
1321 EVT VT = Value.getValueType();
1322 assert(VT.bitsLE(MVT::i32));
1323 EVT MemVT = StoreNode->getMemoryVT();
1324 SDValue MaskConstant;
1325 if (MemVT == MVT::i8) {
1326 MaskConstant = DAG.getConstant(0xFF, MVT::i32);
1328 assert(MemVT == MVT::i16);
1329 MaskConstant = DAG.getConstant(0xFFFF, MVT::i32);
1331 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, VT, Ptr,
1332 DAG.getConstant(2, MVT::i32));
1333 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, Ptr.getValueType(), Ptr,
1334 DAG.getConstant(0x00000003, VT));
1335 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant);
1336 SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex,
1337 DAG.getConstant(3, VT));
1338 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, Shift);
1339 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, Shift);
1340 // XXX: If we add a 64-bit ZW register class, then we could use a 2 x i32
1344 DAG.getConstant(0, MVT::i32),
1345 DAG.getConstant(0, MVT::i32),
1348 SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src);
1349 SDValue Args[3] = { Chain, Input, DWordAddr };
1350 return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL,
1351 Op->getVTList(), Args, MemVT,
1352 StoreNode->getMemOperand());
1353 } else if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR &&
1354 Value.getValueType().bitsGE(MVT::i32)) {
1355 // Convert pointer from byte address to dword address.
1356 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(),
1357 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
1358 Ptr, DAG.getConstant(2, MVT::i32)));
1360 if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
1361 llvm_unreachable("Truncated and indexed stores not supported yet");
1363 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
1369 EVT ValueVT = Value.getValueType();
1371 if (StoreNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1375 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1376 if (Ret.getNode()) {
1379 // Lowering for indirect addressing
1381 const MachineFunction &MF = DAG.getMachineFunction();
1382 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>(
1383 getTargetMachine().getSubtargetImpl()->getFrameLowering());
1384 unsigned StackWidth = TFL->getStackWidth(MF);
1386 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1388 if (ValueVT.isVector()) {
1389 unsigned NumElemVT = ValueVT.getVectorNumElements();
1390 EVT ElemVT = ValueVT.getVectorElementType();
1391 SmallVector<SDValue, 4> Stores(NumElemVT);
1393 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1394 "vector width in load");
1396 for (unsigned i = 0; i < NumElemVT; ++i) {
1397 unsigned Channel, PtrIncr;
1398 getStackAddress(StackWidth, i, Channel, PtrIncr);
1399 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1400 DAG.getConstant(PtrIncr, MVT::i32));
1401 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
1402 Value, DAG.getConstant(i, MVT::i32));
1404 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1406 DAG.getTargetConstant(Channel, MVT::i32));
1408 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores);
1410 if (ValueVT == MVT::i8) {
1411 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
1413 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
1414 DAG.getTargetConstant(0, MVT::i32)); // Channel
1420 // return (512 + (kc_bank << 12)
1422 ConstantAddressBlock(unsigned AddressSpace) {
1423 switch (AddressSpace) {
1424 case AMDGPUAS::CONSTANT_BUFFER_0:
1426 case AMDGPUAS::CONSTANT_BUFFER_1:
1428 case AMDGPUAS::CONSTANT_BUFFER_2:
1429 return 512 + 4096 * 2;
1430 case AMDGPUAS::CONSTANT_BUFFER_3:
1431 return 512 + 4096 * 3;
1432 case AMDGPUAS::CONSTANT_BUFFER_4:
1433 return 512 + 4096 * 4;
1434 case AMDGPUAS::CONSTANT_BUFFER_5:
1435 return 512 + 4096 * 5;
1436 case AMDGPUAS::CONSTANT_BUFFER_6:
1437 return 512 + 4096 * 6;
1438 case AMDGPUAS::CONSTANT_BUFFER_7:
1439 return 512 + 4096 * 7;
1440 case AMDGPUAS::CONSTANT_BUFFER_8:
1441 return 512 + 4096 * 8;
1442 case AMDGPUAS::CONSTANT_BUFFER_9:
1443 return 512 + 4096 * 9;
1444 case AMDGPUAS::CONSTANT_BUFFER_10:
1445 return 512 + 4096 * 10;
1446 case AMDGPUAS::CONSTANT_BUFFER_11:
1447 return 512 + 4096 * 11;
1448 case AMDGPUAS::CONSTANT_BUFFER_12:
1449 return 512 + 4096 * 12;
1450 case AMDGPUAS::CONSTANT_BUFFER_13:
1451 return 512 + 4096 * 13;
1452 case AMDGPUAS::CONSTANT_BUFFER_14:
1453 return 512 + 4096 * 14;
1454 case AMDGPUAS::CONSTANT_BUFFER_15:
1455 return 512 + 4096 * 15;
1461 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
1463 EVT VT = Op.getValueType();
1465 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1466 SDValue Chain = Op.getOperand(0);
1467 SDValue Ptr = Op.getOperand(1);
1468 SDValue LoweredLoad;
1470 SDValue Ret = AMDGPUTargetLowering::LowerLOAD(Op, DAG);
1471 if (Ret.getNode()) {
1476 return DAG.getMergeValues(Ops, DL);
1479 // Lower loads constant address space global variable loads
1480 if (LoadNode->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
1481 isa<GlobalVariable>(
1482 GetUnderlyingObject(LoadNode->getMemOperand()->getValue()))) {
1484 SDValue Ptr = DAG.getZExtOrTrunc(LoadNode->getBasePtr(), DL,
1485 getPointerTy(AMDGPUAS::PRIVATE_ADDRESS));
1486 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
1487 DAG.getConstant(2, MVT::i32));
1488 return DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op->getVTList(),
1489 LoadNode->getChain(), Ptr,
1490 DAG.getTargetConstant(0, MVT::i32), Op.getOperand(2));
1493 if (LoadNode->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS && VT.isVector()) {
1494 SDValue MergedValues[2] = {
1495 ScalarizeVectorLoad(Op, DAG),
1498 return DAG.getMergeValues(MergedValues, DL);
1501 int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
1502 if (ConstantBlock > -1 &&
1503 ((LoadNode->getExtensionType() == ISD::NON_EXTLOAD) ||
1504 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) {
1506 if (isa<ConstantExpr>(LoadNode->getMemOperand()->getValue()) ||
1507 isa<Constant>(LoadNode->getMemOperand()->getValue()) ||
1508 isa<ConstantSDNode>(Ptr)) {
1510 for (unsigned i = 0; i < 4; i++) {
1511 // We want Const position encoded with the following formula :
1512 // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
1513 // const_index is Ptr computed by llvm using an alignment of 16.
1514 // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
1515 // then div by 4 at the ISel step
1516 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1517 DAG.getConstant(4 * i + ConstantBlock * 16, MVT::i32));
1518 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1520 EVT NewVT = MVT::v4i32;
1521 unsigned NumElements = 4;
1522 if (VT.isVector()) {
1524 NumElements = VT.getVectorNumElements();
1526 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT,
1527 makeArrayRef(Slots, NumElements));
1529 // non-constant ptr can't be folded, keeps it as a v4f32 load
1530 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
1531 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
1532 DAG.getConstant(LoadNode->getAddressSpace() -
1533 AMDGPUAS::CONSTANT_BUFFER_0, MVT::i32)
1537 if (!VT.isVector()) {
1538 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1539 DAG.getConstant(0, MVT::i32));
1542 SDValue MergedValues[2] = {
1546 return DAG.getMergeValues(MergedValues, DL);
1549 // For most operations returning SDValue() will result in the node being
1550 // expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so we
1551 // need to manually expand loads that may be legal in some address spaces and
1552 // illegal in others. SEXT loads from CONSTANT_BUFFER_0 are supported for
1553 // compute shaders, since the data is sign extended when it is uploaded to the
1554 // buffer. However SEXT loads from other address spaces are not supported, so
1555 // we need to expand them here.
1556 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
1557 EVT MemVT = LoadNode->getMemoryVT();
1558 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
1559 SDValue ShiftAmount =
1560 DAG.getConstant(VT.getSizeInBits() - MemVT.getSizeInBits(), MVT::i32);
1561 SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr,
1562 LoadNode->getPointerInfo(), MemVT,
1563 LoadNode->isVolatile(),
1564 LoadNode->isNonTemporal(),
1565 LoadNode->isInvariant(),
1566 LoadNode->getAlignment());
1567 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, NewLoad, ShiftAmount);
1568 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Shl, ShiftAmount);
1570 SDValue MergedValues[2] = { Sra, Chain };
1571 return DAG.getMergeValues(MergedValues, DL);
1574 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1578 // Lowering for indirect addressing
1579 const MachineFunction &MF = DAG.getMachineFunction();
1580 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>(
1581 getTargetMachine().getSubtargetImpl()->getFrameLowering());
1582 unsigned StackWidth = TFL->getStackWidth(MF);
1584 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1586 if (VT.isVector()) {
1587 unsigned NumElemVT = VT.getVectorNumElements();
1588 EVT ElemVT = VT.getVectorElementType();
1591 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1592 "vector width in load");
1594 for (unsigned i = 0; i < NumElemVT; ++i) {
1595 unsigned Channel, PtrIncr;
1596 getStackAddress(StackWidth, i, Channel, PtrIncr);
1597 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1598 DAG.getConstant(PtrIncr, MVT::i32));
1599 Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT,
1601 DAG.getTargetConstant(Channel, MVT::i32),
1604 for (unsigned i = NumElemVT; i < 4; ++i) {
1605 Loads[i] = DAG.getUNDEF(ElemVT);
1607 EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4);
1608 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads);
1610 LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
1612 DAG.getTargetConstant(0, MVT::i32), // Channel
1621 return DAG.getMergeValues(Ops, DL);
1624 SDValue R600TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1625 SDValue Chain = Op.getOperand(0);
1626 SDValue Cond = Op.getOperand(1);
1627 SDValue Jump = Op.getOperand(2);
1629 return DAG.getNode(AMDGPUISD::BRANCH_COND, SDLoc(Op), Op.getValueType(),
1633 /// XXX Only kernel functions are supported, so we can assume for now that
1634 /// every function is a kernel function, but in the future we should use
1635 /// separate calling conventions for kernel and non-kernel functions.
1636 SDValue R600TargetLowering::LowerFormalArguments(
1638 CallingConv::ID CallConv,
1640 const SmallVectorImpl<ISD::InputArg> &Ins,
1641 SDLoc DL, SelectionDAG &DAG,
1642 SmallVectorImpl<SDValue> &InVals) const {
1643 SmallVector<CCValAssign, 16> ArgLocs;
1644 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1646 MachineFunction &MF = DAG.getMachineFunction();
1647 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
1649 SmallVector<ISD::InputArg, 8> LocalIns;
1651 getOriginalFunctionArgs(DAG, MF.getFunction(), Ins, LocalIns);
1653 AnalyzeFormalArguments(CCInfo, LocalIns);
1655 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1656 CCValAssign &VA = ArgLocs[i];
1657 const ISD::InputArg &In = Ins[i];
1659 EVT MemVT = VA.getLocVT();
1660 if (!VT.isVector() && MemVT.isVector()) {
1661 // Get load source type if scalarized.
1662 MemVT = MemVT.getVectorElementType();
1665 if (MFI->getShaderType() != ShaderType::COMPUTE) {
1666 unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass);
1667 SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT);
1668 InVals.push_back(Register);
1672 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1673 AMDGPUAS::CONSTANT_BUFFER_0);
1675 // i64 isn't a legal type, so the register type used ends up as i32, which
1676 // isn't expected here. It attempts to create this sextload, but it ends up
1677 // being invalid. Somehow this seems to work with i64 arguments, but breaks
1680 // The first 36 bytes of the input buffer contains information about
1681 // thread group and global sizes.
1682 ISD::LoadExtType Ext = ISD::NON_EXTLOAD;
1683 if (MemVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) {
1684 // FIXME: This should really check the extload type, but the handling of
1685 // extload vector parameters seems to be broken.
1687 // Ext = In.Flags.isSExt() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
1688 Ext = ISD::SEXTLOAD;
1691 // Compute the offset from the value.
1692 // XXX - I think PartOffset should give you this, but it seems to give the
1693 // size of the register which isn't useful.
1695 unsigned ValBase = ArgLocs[In.OrigArgIndex].getLocMemOffset();
1696 unsigned PartOffset = VA.getLocMemOffset();
1697 unsigned Offset = 36 + VA.getLocMemOffset();
1699 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy), PartOffset - ValBase);
1700 SDValue Arg = DAG.getLoad(ISD::UNINDEXED, Ext, VT, DL, Chain,
1701 DAG.getConstant(Offset, MVT::i32),
1702 DAG.getUNDEF(MVT::i32),
1704 MemVT, false, true, true, 4);
1706 // 4 is the preferred alignment for the CONSTANT memory space.
1707 InVals.push_back(Arg);
1708 MFI->ABIArgOffset = Offset + MemVT.getStoreSize();
1713 EVT R600TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1716 return VT.changeVectorElementTypeToInteger();
1719 static SDValue CompactSwizzlableVector(
1720 SelectionDAG &DAG, SDValue VectorEntry,
1721 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1722 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1723 assert(RemapSwizzle.empty());
1724 SDValue NewBldVec[4] = {
1725 VectorEntry.getOperand(0),
1726 VectorEntry.getOperand(1),
1727 VectorEntry.getOperand(2),
1728 VectorEntry.getOperand(3)
1731 for (unsigned i = 0; i < 4; i++) {
1732 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1733 // We mask write here to teach later passes that the ith element of this
1734 // vector is undef. Thus we can use it to reduce 128 bits reg usage,
1735 // break false dependencies and additionnaly make assembly easier to read.
1736 RemapSwizzle[i] = 7; // SEL_MASK_WRITE
1737 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(NewBldVec[i])) {
1739 RemapSwizzle[i] = 4; // SEL_0
1740 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1741 } else if (C->isExactlyValue(1.0)) {
1742 RemapSwizzle[i] = 5; // SEL_1
1743 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1747 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1749 for (unsigned j = 0; j < i; j++) {
1750 if (NewBldVec[i] == NewBldVec[j]) {
1751 NewBldVec[i] = DAG.getUNDEF(NewBldVec[i].getValueType());
1752 RemapSwizzle[i] = j;
1758 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1759 VectorEntry.getValueType(), NewBldVec);
1762 static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
1763 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1764 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1765 assert(RemapSwizzle.empty());
1766 SDValue NewBldVec[4] = {
1767 VectorEntry.getOperand(0),
1768 VectorEntry.getOperand(1),
1769 VectorEntry.getOperand(2),
1770 VectorEntry.getOperand(3)
1772 bool isUnmovable[4] = { false, false, false, false };
1773 for (unsigned i = 0; i < 4; i++) {
1774 RemapSwizzle[i] = i;
1775 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1776 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1779 isUnmovable[Idx] = true;
1783 for (unsigned i = 0; i < 4; i++) {
1784 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1785 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1787 if (isUnmovable[Idx])
1790 std::swap(NewBldVec[Idx], NewBldVec[i]);
1791 std::swap(RemapSwizzle[i], RemapSwizzle[Idx]);
1796 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1797 VectorEntry.getValueType(), NewBldVec);
1801 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector,
1802 SDValue Swz[4], SelectionDAG &DAG) const {
1803 assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR);
1804 // Old -> New swizzle values
1805 DenseMap<unsigned, unsigned> SwizzleRemap;
1807 BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap);
1808 for (unsigned i = 0; i < 4; i++) {
1809 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1810 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1811 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1814 SwizzleRemap.clear();
1815 BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap);
1816 for (unsigned i = 0; i < 4; i++) {
1817 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1818 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1819 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1826 //===----------------------------------------------------------------------===//
1827 // Custom DAG Optimizations
1828 //===----------------------------------------------------------------------===//
1830 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1831 DAGCombinerInfo &DCI) const {
1832 SelectionDAG &DAG = DCI.DAG;
1834 switch (N->getOpcode()) {
1835 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1836 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1837 case ISD::FP_ROUND: {
1838 SDValue Arg = N->getOperand(0);
1839 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1840 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), N->getValueType(0),
1846 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1847 // (i32 select_cc f32, f32, -1, 0 cc)
1849 // Mesa's GLSL frontend generates the above pattern a lot and we can lower
1850 // this to one of the SET*_DX10 instructions.
1851 case ISD::FP_TO_SINT: {
1852 SDValue FNeg = N->getOperand(0);
1853 if (FNeg.getOpcode() != ISD::FNEG) {
1856 SDValue SelectCC = FNeg.getOperand(0);
1857 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1858 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1859 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1860 !isHWTrueValue(SelectCC.getOperand(2)) ||
1861 !isHWFalseValue(SelectCC.getOperand(3))) {
1865 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
1866 SelectCC.getOperand(0), // LHS
1867 SelectCC.getOperand(1), // RHS
1868 DAG.getConstant(-1, MVT::i32), // True
1869 DAG.getConstant(0, MVT::i32), // Flase
1870 SelectCC.getOperand(4)); // CC
1875 // insert_vector_elt (build_vector elt0, ... , eltN), NewEltIdx, idx
1876 // => build_vector elt0, ... , NewEltIdx, ... , eltN
1877 case ISD::INSERT_VECTOR_ELT: {
1878 SDValue InVec = N->getOperand(0);
1879 SDValue InVal = N->getOperand(1);
1880 SDValue EltNo = N->getOperand(2);
1883 // If the inserted element is an UNDEF, just use the input vector.
1884 if (InVal.getOpcode() == ISD::UNDEF)
1887 EVT VT = InVec.getValueType();
1889 // If we can't generate a legal BUILD_VECTOR, exit
1890 if (!isOperationLegal(ISD::BUILD_VECTOR, VT))
1893 // Check that we know which element is being inserted
1894 if (!isa<ConstantSDNode>(EltNo))
1896 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
1898 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
1899 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
1901 SmallVector<SDValue, 8> Ops;
1902 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
1903 Ops.append(InVec.getNode()->op_begin(),
1904 InVec.getNode()->op_end());
1905 } else if (InVec.getOpcode() == ISD::UNDEF) {
1906 unsigned NElts = VT.getVectorNumElements();
1907 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
1912 // Insert the element
1913 if (Elt < Ops.size()) {
1914 // All the operands of BUILD_VECTOR must have the same type;
1915 // we enforce that here.
1916 EVT OpVT = Ops[0].getValueType();
1917 if (InVal.getValueType() != OpVT)
1918 InVal = OpVT.bitsGT(InVal.getValueType()) ?
1919 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
1920 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
1924 // Return the new vector
1925 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
1928 // Extract_vec (Build_vector) generated by custom lowering
1929 // also needs to be customly combined
1930 case ISD::EXTRACT_VECTOR_ELT: {
1931 SDValue Arg = N->getOperand(0);
1932 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1933 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1934 unsigned Element = Const->getZExtValue();
1935 return Arg->getOperand(Element);
1938 if (Arg.getOpcode() == ISD::BITCAST &&
1939 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1940 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1941 unsigned Element = Const->getZExtValue();
1942 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getVTList(),
1943 Arg->getOperand(0).getOperand(Element));
1948 case ISD::SELECT_CC: {
1949 // Try common optimizations
1950 SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1954 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1955 // selectcc x, y, a, b, inv(cc)
1957 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
1958 // selectcc x, y, a, b, cc
1959 SDValue LHS = N->getOperand(0);
1960 if (LHS.getOpcode() != ISD::SELECT_CC) {
1964 SDValue RHS = N->getOperand(1);
1965 SDValue True = N->getOperand(2);
1966 SDValue False = N->getOperand(3);
1967 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1969 if (LHS.getOperand(2).getNode() != True.getNode() ||
1970 LHS.getOperand(3).getNode() != False.getNode() ||
1971 RHS.getNode() != False.getNode()) {
1976 default: return SDValue();
1977 case ISD::SETNE: return LHS;
1979 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
1980 LHSCC = ISD::getSetCCInverse(LHSCC,
1981 LHS.getOperand(0).getValueType().isInteger());
1982 if (DCI.isBeforeLegalizeOps() ||
1983 isCondCodeLegal(LHSCC, LHS.getOperand(0).getSimpleValueType()))
1984 return DAG.getSelectCC(SDLoc(N),
1996 case AMDGPUISD::EXPORT: {
1997 SDValue Arg = N->getOperand(1);
1998 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
2001 SDValue NewArgs[8] = {
2002 N->getOperand(0), // Chain
2004 N->getOperand(2), // ArrayBase
2005 N->getOperand(3), // Type
2006 N->getOperand(4), // SWZ_X
2007 N->getOperand(5), // SWZ_Y
2008 N->getOperand(6), // SWZ_Z
2009 N->getOperand(7) // SWZ_W
2012 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG);
2013 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs);
2015 case AMDGPUISD::TEXTURE_FETCH: {
2016 SDValue Arg = N->getOperand(1);
2017 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
2020 SDValue NewArgs[19] = {
2041 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG);
2042 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, SDLoc(N), N->getVTList(),
2047 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
2051 FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src, SDValue &Neg,
2052 SDValue &Abs, SDValue &Sel, SDValue &Imm, SelectionDAG &DAG) {
2053 const R600InstrInfo *TII =
2054 static_cast<const R600InstrInfo *>(DAG.getSubtarget().getInstrInfo());
2055 if (!Src.isMachineOpcode())
2057 switch (Src.getMachineOpcode()) {
2058 case AMDGPU::FNEG_R600:
2061 Src = Src.getOperand(0);
2062 Neg = DAG.getTargetConstant(1, MVT::i32);
2064 case AMDGPU::FABS_R600:
2067 Src = Src.getOperand(0);
2068 Abs = DAG.getTargetConstant(1, MVT::i32);
2070 case AMDGPU::CONST_COPY: {
2071 unsigned Opcode = ParentNode->getMachineOpcode();
2072 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2077 SDValue CstOffset = Src.getOperand(0);
2078 if (ParentNode->getValueType(0).isVector())
2081 // Gather constants values
2082 int SrcIndices[] = {
2083 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
2084 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
2085 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2),
2086 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
2087 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
2088 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
2089 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
2090 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
2091 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
2092 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
2093 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
2095 std::vector<unsigned> Consts;
2096 for (int OtherSrcIdx : SrcIndices) {
2097 int OtherSelIdx = TII->getSelIdx(Opcode, OtherSrcIdx);
2098 if (OtherSrcIdx < 0 || OtherSelIdx < 0)
2104 if (RegisterSDNode *Reg =
2105 dyn_cast<RegisterSDNode>(ParentNode->getOperand(OtherSrcIdx))) {
2106 if (Reg->getReg() == AMDGPU::ALU_CONST) {
2108 = cast<ConstantSDNode>(ParentNode->getOperand(OtherSelIdx));
2109 Consts.push_back(Cst->getZExtValue());
2114 ConstantSDNode *Cst = cast<ConstantSDNode>(CstOffset);
2115 Consts.push_back(Cst->getZExtValue());
2116 if (!TII->fitsConstReadLimitations(Consts)) {
2121 Src = DAG.getRegister(AMDGPU::ALU_CONST, MVT::f32);
2124 case AMDGPU::MOV_IMM_I32:
2125 case AMDGPU::MOV_IMM_F32: {
2126 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
2127 uint64_t ImmValue = 0;
2130 if (Src.getMachineOpcode() == AMDGPU::MOV_IMM_F32) {
2131 ConstantFPSDNode *FPC = dyn_cast<ConstantFPSDNode>(Src.getOperand(0));
2132 float FloatValue = FPC->getValueAPF().convertToFloat();
2133 if (FloatValue == 0.0) {
2134 ImmReg = AMDGPU::ZERO;
2135 } else if (FloatValue == 0.5) {
2136 ImmReg = AMDGPU::HALF;
2137 } else if (FloatValue == 1.0) {
2138 ImmReg = AMDGPU::ONE;
2140 ImmValue = FPC->getValueAPF().bitcastToAPInt().getZExtValue();
2143 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src.getOperand(0));
2144 uint64_t Value = C->getZExtValue();
2146 ImmReg = AMDGPU::ZERO;
2147 } else if (Value == 1) {
2148 ImmReg = AMDGPU::ONE_INT;
2154 // Check that we aren't already using an immediate.
2155 // XXX: It's possible for an instruction to have more than one
2156 // immediate operand, but this is not supported yet.
2157 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
2160 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Imm);
2162 if (C->getZExtValue())
2164 Imm = DAG.getTargetConstant(ImmValue, MVT::i32);
2166 Src = DAG.getRegister(ImmReg, MVT::i32);
2175 /// \brief Fold the instructions after selecting them
2176 SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node,
2177 SelectionDAG &DAG) const {
2178 const R600InstrInfo *TII =
2179 static_cast<const R600InstrInfo *>(DAG.getSubtarget().getInstrInfo());
2180 if (!Node->isMachineOpcode())
2182 unsigned Opcode = Node->getMachineOpcode();
2185 std::vector<SDValue> Ops;
2186 for (const SDUse &I : Node->ops())
2189 if (Opcode == AMDGPU::DOT_4) {
2190 int OperandIdx[] = {
2191 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
2192 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
2193 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
2194 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
2195 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
2196 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
2197 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
2198 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
2201 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_X),
2202 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Y),
2203 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Z),
2204 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_W),
2205 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_X),
2206 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Y),
2207 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Z),
2208 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_W)
2211 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_X),
2212 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Y),
2213 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Z),
2214 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_W),
2215 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_X),
2216 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Y),
2217 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Z),
2218 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_W)
2220 for (unsigned i = 0; i < 8; i++) {
2221 if (OperandIdx[i] < 0)
2223 SDValue &Src = Ops[OperandIdx[i] - 1];
2224 SDValue &Neg = Ops[NegIdx[i] - 1];
2225 SDValue &Abs = Ops[AbsIdx[i] - 1];
2226 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2227 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
2230 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2231 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, FakeOp, DAG))
2232 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2234 } else if (Opcode == AMDGPU::REG_SEQUENCE) {
2235 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) {
2236 SDValue &Src = Ops[i];
2237 if (FoldOperand(Node, i, Src, FakeOp, FakeOp, FakeOp, FakeOp, DAG))
2238 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2240 } else if (Opcode == AMDGPU::CLAMP_R600) {
2241 SDValue Src = Node->getOperand(0);
2242 if (!Src.isMachineOpcode() ||
2243 !TII->hasInstrModifiers(Src.getMachineOpcode()))
2245 int ClampIdx = TII->getOperandIdx(Src.getMachineOpcode(),
2246 AMDGPU::OpName::clamp);
2249 std::vector<SDValue> Ops;
2250 unsigned NumOp = Src.getNumOperands();
2251 for(unsigned i = 0; i < NumOp; ++i)
2252 Ops.push_back(Src.getOperand(i));
2253 Ops[ClampIdx - 1] = DAG.getTargetConstant(1, MVT::i32);
2254 return DAG.getMachineNode(Src.getMachineOpcode(), SDLoc(Node),
2255 Node->getVTList(), Ops);
2257 if (!TII->hasInstrModifiers(Opcode))
2259 int OperandIdx[] = {
2260 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
2261 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
2262 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2)
2265 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg),
2266 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg),
2267 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2_neg)
2270 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs),
2271 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs),
2274 for (unsigned i = 0; i < 3; i++) {
2275 if (OperandIdx[i] < 0)
2277 SDValue &Src = Ops[OperandIdx[i] - 1];
2278 SDValue &Neg = Ops[NegIdx[i] - 1];
2280 SDValue &Abs = (AbsIdx[i] > -1) ? Ops[AbsIdx[i] - 1] : FakeAbs;
2281 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2282 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
2283 int ImmIdx = TII->getOperandIdx(Opcode, AMDGPU::OpName::literal);
2288 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2289 SDValue &Imm = Ops[ImmIdx];
2290 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, Imm, DAG))
2291 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);