1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for R600
13 //===----------------------------------------------------------------------===//
15 #include "R600ISelLowering.h"
16 #include "R600Defines.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineFunctionInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/IR/Argument.h"
25 #include "llvm/IR/Function.h"
29 R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
30 AMDGPUTargetLowering(TM),
31 Gen(TM.getSubtarget<AMDGPUSubtarget>().getGeneration()) {
32 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
34 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
35 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
36 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
37 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
39 computeRegisterProperties();
41 setOperationAction(ISD::FCOS, MVT::f32, Custom);
42 setOperationAction(ISD::FSIN, MVT::f32, Custom);
44 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
45 setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
47 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
48 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
50 setOperationAction(ISD::FSUB, MVT::f32, Expand);
52 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
53 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
54 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
56 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
57 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
59 setOperationAction(ISD::SETCC, MVT::i32, Expand);
60 setOperationAction(ISD::SETCC, MVT::f32, Expand);
61 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
63 setOperationAction(ISD::SELECT, MVT::i32, Custom);
64 setOperationAction(ISD::SELECT, MVT::f32, Custom);
66 // Legalize loads and stores to the private address space.
67 setOperationAction(ISD::LOAD, MVT::i32, Custom);
68 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
69 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
70 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
71 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
72 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
73 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
74 setOperationAction(ISD::STORE, MVT::i8, Custom);
75 setOperationAction(ISD::STORE, MVT::i32, Custom);
76 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
77 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
78 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
79 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
81 setOperationAction(ISD::LOAD, MVT::i32, Custom);
82 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
83 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
85 setTargetDAGCombine(ISD::FP_ROUND);
86 setTargetDAGCombine(ISD::FP_TO_SINT);
87 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
88 setTargetDAGCombine(ISD::SELECT_CC);
89 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
91 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
93 setBooleanContents(ZeroOrNegativeOneBooleanContent);
94 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
95 setSchedulingPreference(Sched::Source);
98 MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
99 MachineInstr * MI, MachineBasicBlock * BB) const {
100 MachineFunction * MF = BB->getParent();
101 MachineRegisterInfo &MRI = MF->getRegInfo();
102 MachineBasicBlock::iterator I = *MI;
103 const R600InstrInfo *TII =
104 static_cast<const R600InstrInfo*>(MF->getTarget().getInstrInfo());
106 switch (MI->getOpcode()) {
107 default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
108 case AMDGPU::CLAMP_R600: {
109 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
111 MI->getOperand(0).getReg(),
112 MI->getOperand(1).getReg());
113 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
117 case AMDGPU::FABS_R600: {
118 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
120 MI->getOperand(0).getReg(),
121 MI->getOperand(1).getReg());
122 TII->addFlag(NewMI, 0, MO_FLAG_ABS);
126 case AMDGPU::FNEG_R600: {
127 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
129 MI->getOperand(0).getReg(),
130 MI->getOperand(1).getReg());
131 TII->addFlag(NewMI, 0, MO_FLAG_NEG);
135 case AMDGPU::MASK_WRITE: {
136 unsigned maskedRegister = MI->getOperand(0).getReg();
137 assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
138 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
139 TII->addFlag(defInstr, 0, MO_FLAG_MASK);
143 case AMDGPU::LDS_READ_RET: {
144 MachineInstrBuilder NewMI = BuildMI(*BB, I, BB->findDebugLoc(I),
145 TII->get(MI->getOpcode()),
147 for (unsigned i = 1, e = MI->getNumOperands(); i < e; ++i) {
148 NewMI.addOperand(MI->getOperand(i));
150 TII->buildDefaultInstruction(*BB, I, AMDGPU::MOV,
151 MI->getOperand(0).getReg(),
156 case AMDGPU::MOV_IMM_F32:
157 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
158 MI->getOperand(1).getFPImm()->getValueAPF()
159 .bitcastToAPInt().getZExtValue());
161 case AMDGPU::MOV_IMM_I32:
162 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
163 MI->getOperand(1).getImm());
165 case AMDGPU::CONST_COPY: {
166 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
167 MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
168 TII->setImmOperand(NewMI, AMDGPU::OpName::src0_sel,
169 MI->getOperand(1).getImm());
173 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
174 case AMDGPU::RAT_WRITE_CACHELESS_64_eg:
175 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
176 unsigned EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
178 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
179 .addOperand(MI->getOperand(0))
180 .addOperand(MI->getOperand(1))
181 .addImm(EOP); // Set End of program bit
186 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
187 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
188 MachineOperand &RID = MI->getOperand(4);
189 MachineOperand &SID = MI->getOperand(5);
190 unsigned TextureId = MI->getOperand(6).getImm();
191 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
192 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
204 case 8: // ShadowRect
215 case 11: // Shadow1DArray
219 case 12: // Shadow2DArray
223 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
224 .addOperand(MI->getOperand(3))
242 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
243 .addOperand(MI->getOperand(2))
261 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
262 .addOperand(MI->getOperand(0))
263 .addOperand(MI->getOperand(1))
281 .addReg(T0, RegState::Implicit)
282 .addReg(T1, RegState::Implicit);
286 case AMDGPU::TXD_SHADOW: {
287 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
288 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
289 MachineOperand &RID = MI->getOperand(4);
290 MachineOperand &SID = MI->getOperand(5);
291 unsigned TextureId = MI->getOperand(6).getImm();
292 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
293 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
305 case 8: // ShadowRect
316 case 11: // Shadow1DArray
320 case 12: // Shadow2DArray
325 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
326 .addOperand(MI->getOperand(3))
344 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
345 .addOperand(MI->getOperand(2))
363 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
364 .addOperand(MI->getOperand(0))
365 .addOperand(MI->getOperand(1))
383 .addReg(T0, RegState::Implicit)
384 .addReg(T1, RegState::Implicit);
389 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
390 .addOperand(MI->getOperand(0));
393 case AMDGPU::BRANCH_COND_f32: {
394 MachineInstr *NewMI =
395 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
396 AMDGPU::PREDICATE_BIT)
397 .addOperand(MI->getOperand(1))
398 .addImm(OPCODE_IS_NOT_ZERO)
400 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
401 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
402 .addOperand(MI->getOperand(0))
403 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
407 case AMDGPU::BRANCH_COND_i32: {
408 MachineInstr *NewMI =
409 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
410 AMDGPU::PREDICATE_BIT)
411 .addOperand(MI->getOperand(1))
412 .addImm(OPCODE_IS_NOT_ZERO_INT)
414 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
415 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
416 .addOperand(MI->getOperand(0))
417 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
421 case AMDGPU::EG_ExportSwz:
422 case AMDGPU::R600_ExportSwz: {
423 // Instruction is left unmodified if its not the last one of its type
424 bool isLastInstructionOfItsType = true;
425 unsigned InstExportType = MI->getOperand(1).getImm();
426 for (MachineBasicBlock::iterator NextExportInst = llvm::next(I),
427 EndBlock = BB->end(); NextExportInst != EndBlock;
428 NextExportInst = llvm::next(NextExportInst)) {
429 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
430 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
431 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
433 if (CurrentInstExportType == InstExportType) {
434 isLastInstructionOfItsType = false;
439 bool EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN)? 1 : 0;
440 if (!EOP && !isLastInstructionOfItsType)
442 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
443 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
444 .addOperand(MI->getOperand(0))
445 .addOperand(MI->getOperand(1))
446 .addOperand(MI->getOperand(2))
447 .addOperand(MI->getOperand(3))
448 .addOperand(MI->getOperand(4))
449 .addOperand(MI->getOperand(5))
450 .addOperand(MI->getOperand(6))
455 case AMDGPU::RETURN: {
456 // RETURN instructions must have the live-out registers as implicit uses,
457 // otherwise they appear dead.
458 R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
459 MachineInstrBuilder MIB(*MF, MI);
460 for (unsigned i = 0, e = MFI->LiveOuts.size(); i != e; ++i)
461 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
466 MI->eraseFromParent();
470 //===----------------------------------------------------------------------===//
471 // Custom DAG Lowering Operations
472 //===----------------------------------------------------------------------===//
474 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
475 MachineFunction &MF = DAG.getMachineFunction();
476 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
477 switch (Op.getOpcode()) {
478 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
480 case ISD::FSIN: return LowerTrig(Op, DAG);
481 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
482 case ISD::SELECT: return LowerSELECT(Op, DAG);
483 case ISD::STORE: return LowerSTORE(Op, DAG);
484 case ISD::LOAD: return LowerLOAD(Op, DAG);
485 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
486 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
487 case ISD::INTRINSIC_VOID: {
488 SDValue Chain = Op.getOperand(0);
489 unsigned IntrinsicID =
490 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
491 switch (IntrinsicID) {
492 case AMDGPUIntrinsic::AMDGPU_store_output: {
493 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
494 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
495 MFI->LiveOuts.push_back(Reg);
496 return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2));
498 case AMDGPUIntrinsic::R600_store_swizzle: {
499 const SDValue Args[8] = {
501 Op.getOperand(2), // Export Value
502 Op.getOperand(3), // ArrayBase
503 Op.getOperand(4), // Type
504 DAG.getConstant(0, MVT::i32), // SWZ_X
505 DAG.getConstant(1, MVT::i32), // SWZ_Y
506 DAG.getConstant(2, MVT::i32), // SWZ_Z
507 DAG.getConstant(3, MVT::i32) // SWZ_W
509 return DAG.getNode(AMDGPUISD::EXPORT, SDLoc(Op), Op.getValueType(),
513 // default for switch(IntrinsicID)
516 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
519 case ISD::INTRINSIC_WO_CHAIN: {
520 unsigned IntrinsicID =
521 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
522 EVT VT = Op.getValueType();
524 switch(IntrinsicID) {
525 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
526 case AMDGPUIntrinsic::R600_load_input: {
527 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
528 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
529 MachineFunction &MF = DAG.getMachineFunction();
530 MachineRegisterInfo &MRI = MF.getRegInfo();
532 return DAG.getCopyFromReg(DAG.getEntryNode(),
533 SDLoc(DAG.getEntryNode()), Reg, VT);
536 case AMDGPUIntrinsic::R600_interp_input: {
537 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
538 int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
539 MachineSDNode *interp;
541 const MachineFunction &MF = DAG.getMachineFunction();
542 const R600InstrInfo *TII =
543 static_cast<const R600InstrInfo*>(MF.getTarget().getInstrInfo());
544 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
545 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
546 return DAG.getTargetExtractSubreg(
547 TII->getRegisterInfo().getSubRegFromChannel(slot % 4),
548 DL, MVT::f32, SDValue(interp, 0));
551 MachineFunction &MF = DAG.getMachineFunction();
552 MachineRegisterInfo &MRI = MF.getRegInfo();
553 unsigned RegisterI = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb);
554 unsigned RegisterJ = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1);
555 MRI.addLiveIn(RegisterI);
556 MRI.addLiveIn(RegisterJ);
557 SDValue RegisterINode = DAG.getCopyFromReg(DAG.getEntryNode(),
558 SDLoc(DAG.getEntryNode()), RegisterI, MVT::f32);
559 SDValue RegisterJNode = DAG.getCopyFromReg(DAG.getEntryNode(),
560 SDLoc(DAG.getEntryNode()), RegisterJ, MVT::f32);
563 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
564 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
565 RegisterJNode, RegisterINode);
567 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
568 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
569 RegisterJNode, RegisterINode);
570 return SDValue(interp, slot % 2);
572 case AMDGPUIntrinsic::R600_tex:
573 case AMDGPUIntrinsic::R600_texc:
574 case AMDGPUIntrinsic::R600_txl:
575 case AMDGPUIntrinsic::R600_txlc:
576 case AMDGPUIntrinsic::R600_txb:
577 case AMDGPUIntrinsic::R600_txbc:
578 case AMDGPUIntrinsic::R600_txf:
579 case AMDGPUIntrinsic::R600_txq:
580 case AMDGPUIntrinsic::R600_ddx:
581 case AMDGPUIntrinsic::R600_ddy: {
583 switch (IntrinsicID) {
584 case AMDGPUIntrinsic::R600_tex:
587 case AMDGPUIntrinsic::R600_texc:
590 case AMDGPUIntrinsic::R600_txl:
593 case AMDGPUIntrinsic::R600_txlc:
596 case AMDGPUIntrinsic::R600_txb:
599 case AMDGPUIntrinsic::R600_txbc:
602 case AMDGPUIntrinsic::R600_txf:
605 case AMDGPUIntrinsic::R600_txq:
608 case AMDGPUIntrinsic::R600_ddx:
611 case AMDGPUIntrinsic::R600_ddy:
615 llvm_unreachable("Unknow Texture Operation");
618 SDValue TexArgs[19] = {
619 DAG.getConstant(TextureOp, MVT::i32),
621 DAG.getConstant(0, MVT::i32),
622 DAG.getConstant(1, MVT::i32),
623 DAG.getConstant(2, MVT::i32),
624 DAG.getConstant(3, MVT::i32),
628 DAG.getConstant(0, MVT::i32),
629 DAG.getConstant(1, MVT::i32),
630 DAG.getConstant(2, MVT::i32),
631 DAG.getConstant(3, MVT::i32),
639 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs, 19);
641 case AMDGPUIntrinsic::AMDGPU_dp4: {
643 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
644 DAG.getConstant(0, MVT::i32)),
645 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
646 DAG.getConstant(0, MVT::i32)),
647 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
648 DAG.getConstant(1, MVT::i32)),
649 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
650 DAG.getConstant(1, MVT::i32)),
651 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
652 DAG.getConstant(2, MVT::i32)),
653 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
654 DAG.getConstant(2, MVT::i32)),
655 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
656 DAG.getConstant(3, MVT::i32)),
657 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
658 DAG.getConstant(3, MVT::i32))
660 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args, 8);
663 case Intrinsic::r600_read_ngroups_x:
664 return LowerImplicitParameter(DAG, VT, DL, 0);
665 case Intrinsic::r600_read_ngroups_y:
666 return LowerImplicitParameter(DAG, VT, DL, 1);
667 case Intrinsic::r600_read_ngroups_z:
668 return LowerImplicitParameter(DAG, VT, DL, 2);
669 case Intrinsic::r600_read_global_size_x:
670 return LowerImplicitParameter(DAG, VT, DL, 3);
671 case Intrinsic::r600_read_global_size_y:
672 return LowerImplicitParameter(DAG, VT, DL, 4);
673 case Intrinsic::r600_read_global_size_z:
674 return LowerImplicitParameter(DAG, VT, DL, 5);
675 case Intrinsic::r600_read_local_size_x:
676 return LowerImplicitParameter(DAG, VT, DL, 6);
677 case Intrinsic::r600_read_local_size_y:
678 return LowerImplicitParameter(DAG, VT, DL, 7);
679 case Intrinsic::r600_read_local_size_z:
680 return LowerImplicitParameter(DAG, VT, DL, 8);
682 case Intrinsic::r600_read_tgid_x:
683 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
685 case Intrinsic::r600_read_tgid_y:
686 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
688 case Intrinsic::r600_read_tgid_z:
689 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
691 case Intrinsic::r600_read_tidig_x:
692 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
694 case Intrinsic::r600_read_tidig_y:
695 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
697 case Intrinsic::r600_read_tidig_z:
698 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
701 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
704 } // end switch(Op.getOpcode())
708 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
709 SmallVectorImpl<SDValue> &Results,
710 SelectionDAG &DAG) const {
711 switch (N->getOpcode()) {
713 case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
716 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
717 Results.push_back(SDValue(Node, 0));
718 Results.push_back(SDValue(Node, 1));
719 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
721 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
725 SDNode *Node = LowerSTORE(SDValue(N, 0), DAG).getNode();
726 Results.push_back(SDValue(Node, 0));
731 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
732 // On hw >= R700, COS/SIN input must be between -1. and 1.
733 // Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5)
734 EVT VT = Op.getValueType();
735 SDValue Arg = Op.getOperand(0);
736 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
737 DAG.getNode(ISD::FADD, SDLoc(Op), VT,
738 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
739 DAG.getConstantFP(0.15915494309, MVT::f32)),
740 DAG.getConstantFP(0.5, MVT::f32)));
742 switch (Op.getOpcode()) {
744 TrigNode = AMDGPUISD::COS_HW;
747 TrigNode = AMDGPUISD::SIN_HW;
750 llvm_unreachable("Wrong trig opcode");
752 SDValue TrigVal = DAG.getNode(TrigNode, SDLoc(Op), VT,
753 DAG.getNode(ISD::FADD, SDLoc(Op), VT, FractPart,
754 DAG.getConstantFP(-0.5, MVT::f32)));
755 if (Gen >= AMDGPUSubtarget::R700)
757 // On R600 hw, COS/SIN input must be between -Pi and Pi.
758 return DAG.getNode(ISD::FMUL, SDLoc(Op), VT, TrigVal,
759 DAG.getConstantFP(3.14159265359, MVT::f32));
762 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
767 Op, DAG.getConstantFP(0.0f, MVT::f32),
768 DAG.getCondCode(ISD::SETNE)
772 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
774 unsigned DwordOffset) const {
775 unsigned ByteOffset = DwordOffset * 4;
776 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
777 AMDGPUAS::CONSTANT_BUFFER_0);
779 // We shouldn't be using an offset wider than 16-bits for implicit parameters.
780 assert(isInt<16>(ByteOffset));
782 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
783 DAG.getConstant(ByteOffset, MVT::i32), // PTR
784 MachinePointerInfo(ConstantPointerNull::get(PtrType)),
785 false, false, false, 0);
788 SDValue R600TargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
790 MachineFunction &MF = DAG.getMachineFunction();
791 const AMDGPUFrameLowering *TFL =
792 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
794 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op);
797 unsigned FrameIndex = FIN->getIndex();
798 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
799 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), MVT::i32);
802 bool R600TargetLowering::isZero(SDValue Op) const {
803 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
804 return Cst->isNullValue();
805 } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
806 return CstFP->isZero();
812 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
814 EVT VT = Op.getValueType();
816 SDValue LHS = Op.getOperand(0);
817 SDValue RHS = Op.getOperand(1);
818 SDValue True = Op.getOperand(2);
819 SDValue False = Op.getOperand(3);
820 SDValue CC = Op.getOperand(4);
823 // LHS and RHS are guaranteed to be the same value type
824 EVT CompareVT = LHS.getValueType();
826 // Check if we can lower this to a native operation.
828 // Try to lower to a SET* instruction:
830 // SET* can match the following patterns:
832 // select_cc f32, f32, -1, 0, cc_any
833 // select_cc f32, f32, 1.0f, 0.0f, cc_any
834 // select_cc i32, i32, -1, 0, cc_any
837 // Move hardware True/False values to the correct operand.
838 if (isHWTrueValue(False) && isHWFalseValue(True)) {
839 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
840 std::swap(False, True);
841 CC = DAG.getCondCode(ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32));
844 if (isHWTrueValue(True) && isHWFalseValue(False) &&
845 (CompareVT == VT || VT == MVT::i32)) {
846 // This can be matched by a SET* instruction.
847 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
850 // Try to lower to a CND* instruction:
852 // CND* can match the following patterns:
854 // select_cc f32, 0.0, f32, f32, cc_any
855 // select_cc f32, 0.0, i32, i32, cc_any
856 // select_cc i32, 0, f32, f32, cc_any
857 // select_cc i32, 0, i32, i32, cc_any
859 if (isZero(LHS) || isZero(RHS)) {
860 SDValue Cond = (isZero(LHS) ? RHS : LHS);
861 SDValue Zero = (isZero(LHS) ? LHS : RHS);
862 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
863 if (CompareVT != VT) {
864 // Bitcast True / False to the correct types. This will end up being
865 // a nop, but it allows us to define only a single pattern in the
866 // .TD files for each CND* instruction rather than having to have
867 // one pattern for integer True/False and one for fp True/False
868 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
869 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
872 CCOpcode = ISD::getSetCCSwappedOperands(CCOpcode);
885 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
893 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
896 DAG.getCondCode(CCOpcode));
897 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
901 // Possible Min/Max pattern
902 SDValue MinMax = LowerMinMax(Op, DAG);
903 if (MinMax.getNode()) {
907 // If we make it this for it means we have no native instructions to handle
908 // this SELECT_CC, so we must lower it.
909 SDValue HWTrue, HWFalse;
911 if (CompareVT == MVT::f32) {
912 HWTrue = DAG.getConstantFP(1.0f, CompareVT);
913 HWFalse = DAG.getConstantFP(0.0f, CompareVT);
914 } else if (CompareVT == MVT::i32) {
915 HWTrue = DAG.getConstant(-1, CompareVT);
916 HWFalse = DAG.getConstant(0, CompareVT);
919 assert(!"Unhandled value type in LowerSELECT_CC");
922 // Lower this unsupported SELECT_CC into a combination of two supported
923 // SELECT_CC operations.
924 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
926 return DAG.getNode(ISD::SELECT_CC, DL, VT,
929 DAG.getCondCode(ISD::SETNE));
932 SDValue R600TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
933 return DAG.getNode(ISD::SELECT_CC,
937 DAG.getConstant(0, MVT::i32),
940 DAG.getCondCode(ISD::SETNE));
943 /// LLVM generates byte-addresed pointers. For indirect addressing, we need to
944 /// convert these pointers to a register index. Each register holds
945 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
946 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
947 /// for indirect addressing.
948 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
950 SelectionDAG &DAG) const {
962 default: llvm_unreachable("Invalid stack width");
965 return DAG.getNode(ISD::SRL, SDLoc(Ptr), Ptr.getValueType(), Ptr,
966 DAG.getConstant(SRLPad, MVT::i32));
969 void R600TargetLowering::getStackAddress(unsigned StackWidth,
972 unsigned &PtrIncr) const {
973 switch (StackWidth) {
984 Channel = ElemIdx % 2;
998 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1000 StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
1001 SDValue Chain = Op.getOperand(0);
1002 SDValue Value = Op.getOperand(1);
1003 SDValue Ptr = Op.getOperand(2);
1005 SDValue Result = AMDGPUTargetLowering::LowerVectorStore(Op, DAG);
1006 if (Result.getNode()) {
1010 if (StoreNode->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS) {
1011 if (StoreNode->isTruncatingStore()) {
1012 EVT VT = Value.getValueType();
1013 assert(VT.bitsLE(MVT::i32));
1014 EVT MemVT = StoreNode->getMemoryVT();
1015 SDValue MaskConstant;
1016 if (MemVT == MVT::i8) {
1017 MaskConstant = DAG.getConstant(0xFF, MVT::i32);
1019 assert(MemVT == MVT::i16);
1020 MaskConstant = DAG.getConstant(0xFFFF, MVT::i32);
1022 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, VT, Ptr,
1023 DAG.getConstant(2, MVT::i32));
1024 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, Ptr.getValueType(), Ptr,
1025 DAG.getConstant(0x00000003, VT));
1026 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant);
1027 SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex,
1028 DAG.getConstant(3, VT));
1029 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, Shift);
1030 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, Shift);
1031 // XXX: If we add a 64-bit ZW register class, then we could use a 2 x i32
1035 DAG.getConstant(0, MVT::i32),
1036 DAG.getConstant(0, MVT::i32),
1039 SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src, 4);
1040 SDValue Args[3] = { Chain, Input, DWordAddr };
1041 return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL,
1042 Op->getVTList(), Args, 3, MemVT,
1043 StoreNode->getMemOperand());
1044 } else if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR &&
1045 Value.getValueType().bitsGE(MVT::i32)) {
1046 // Convert pointer from byte address to dword address.
1047 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(),
1048 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
1049 Ptr, DAG.getConstant(2, MVT::i32)));
1051 if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
1052 assert(!"Truncated and indexed stores not supported yet");
1054 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
1060 EVT ValueVT = Value.getValueType();
1062 if (StoreNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1066 // Lowering for indirect addressing
1068 const MachineFunction &MF = DAG.getMachineFunction();
1069 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
1070 getTargetMachine().getFrameLowering());
1071 unsigned StackWidth = TFL->getStackWidth(MF);
1073 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1075 if (ValueVT.isVector()) {
1076 unsigned NumElemVT = ValueVT.getVectorNumElements();
1077 EVT ElemVT = ValueVT.getVectorElementType();
1080 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1081 "vector width in load");
1083 for (unsigned i = 0; i < NumElemVT; ++i) {
1084 unsigned Channel, PtrIncr;
1085 getStackAddress(StackWidth, i, Channel, PtrIncr);
1086 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1087 DAG.getConstant(PtrIncr, MVT::i32));
1088 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
1089 Value, DAG.getConstant(i, MVT::i32));
1091 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1093 DAG.getTargetConstant(Channel, MVT::i32));
1095 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores, NumElemVT);
1097 if (ValueVT == MVT::i8) {
1098 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
1100 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
1101 DAG.getTargetConstant(0, MVT::i32)); // Channel
1107 // return (512 + (kc_bank << 12)
1109 ConstantAddressBlock(unsigned AddressSpace) {
1110 switch (AddressSpace) {
1111 case AMDGPUAS::CONSTANT_BUFFER_0:
1113 case AMDGPUAS::CONSTANT_BUFFER_1:
1115 case AMDGPUAS::CONSTANT_BUFFER_2:
1116 return 512 + 4096 * 2;
1117 case AMDGPUAS::CONSTANT_BUFFER_3:
1118 return 512 + 4096 * 3;
1119 case AMDGPUAS::CONSTANT_BUFFER_4:
1120 return 512 + 4096 * 4;
1121 case AMDGPUAS::CONSTANT_BUFFER_5:
1122 return 512 + 4096 * 5;
1123 case AMDGPUAS::CONSTANT_BUFFER_6:
1124 return 512 + 4096 * 6;
1125 case AMDGPUAS::CONSTANT_BUFFER_7:
1126 return 512 + 4096 * 7;
1127 case AMDGPUAS::CONSTANT_BUFFER_8:
1128 return 512 + 4096 * 8;
1129 case AMDGPUAS::CONSTANT_BUFFER_9:
1130 return 512 + 4096 * 9;
1131 case AMDGPUAS::CONSTANT_BUFFER_10:
1132 return 512 + 4096 * 10;
1133 case AMDGPUAS::CONSTANT_BUFFER_11:
1134 return 512 + 4096 * 11;
1135 case AMDGPUAS::CONSTANT_BUFFER_12:
1136 return 512 + 4096 * 12;
1137 case AMDGPUAS::CONSTANT_BUFFER_13:
1138 return 512 + 4096 * 13;
1139 case AMDGPUAS::CONSTANT_BUFFER_14:
1140 return 512 + 4096 * 14;
1141 case AMDGPUAS::CONSTANT_BUFFER_15:
1142 return 512 + 4096 * 15;
1148 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
1150 EVT VT = Op.getValueType();
1152 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1153 SDValue Chain = Op.getOperand(0);
1154 SDValue Ptr = Op.getOperand(1);
1155 SDValue LoweredLoad;
1157 int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
1158 if (ConstantBlock > -1) {
1160 if (dyn_cast<ConstantExpr>(LoadNode->getSrcValue()) ||
1161 dyn_cast<Constant>(LoadNode->getSrcValue()) ||
1162 dyn_cast<ConstantSDNode>(Ptr)) {
1164 for (unsigned i = 0; i < 4; i++) {
1165 // We want Const position encoded with the following formula :
1166 // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
1167 // const_index is Ptr computed by llvm using an alignment of 16.
1168 // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
1169 // then div by 4 at the ISel step
1170 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1171 DAG.getConstant(4 * i + ConstantBlock * 16, MVT::i32));
1172 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1174 EVT NewVT = MVT::v4i32;
1175 unsigned NumElements = 4;
1176 if (VT.isVector()) {
1178 NumElements = VT.getVectorNumElements();
1180 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT, Slots, NumElements);
1182 // non constant ptr cant be folded, keeps it as a v4f32 load
1183 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
1184 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
1185 DAG.getConstant(LoadNode->getAddressSpace() -
1186 AMDGPUAS::CONSTANT_BUFFER_0, MVT::i32)
1190 if (!VT.isVector()) {
1191 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1192 DAG.getConstant(0, MVT::i32));
1195 SDValue MergedValues[2] = {
1199 return DAG.getMergeValues(MergedValues, 2, DL);
1202 // For most operations returning SDValue() will result int he node being
1203 // expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so
1204 // we need to manually expand loads that may be legal in some address spaces
1205 // and illegal in others. SEXT loads from CONSTANT_BUFFER_0 are supported
1206 // for compute shaders, since the data is sign extended when it is uploaded
1207 // to the buffer. Howerver SEXT loads from other addresspaces are not
1208 // supported, so we need to expand them here.
1209 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
1210 EVT MemVT = LoadNode->getMemoryVT();
1211 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
1212 SDValue ShiftAmount =
1213 DAG.getConstant(VT.getSizeInBits() - MemVT.getSizeInBits(), MVT::i32);
1214 SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr,
1215 LoadNode->getPointerInfo(), MemVT,
1216 LoadNode->isVolatile(),
1217 LoadNode->isNonTemporal(),
1218 LoadNode->getAlignment());
1219 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, NewLoad, ShiftAmount);
1220 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Shl, ShiftAmount);
1222 SDValue MergedValues[2] = { Sra, Chain };
1223 return DAG.getMergeValues(MergedValues, 2, DL);
1226 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1230 // Lowering for indirect addressing
1231 const MachineFunction &MF = DAG.getMachineFunction();
1232 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
1233 getTargetMachine().getFrameLowering());
1234 unsigned StackWidth = TFL->getStackWidth(MF);
1236 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1238 if (VT.isVector()) {
1239 unsigned NumElemVT = VT.getVectorNumElements();
1240 EVT ElemVT = VT.getVectorElementType();
1243 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1244 "vector width in load");
1246 for (unsigned i = 0; i < NumElemVT; ++i) {
1247 unsigned Channel, PtrIncr;
1248 getStackAddress(StackWidth, i, Channel, PtrIncr);
1249 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1250 DAG.getConstant(PtrIncr, MVT::i32));
1251 Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT,
1253 DAG.getTargetConstant(Channel, MVT::i32),
1256 for (unsigned i = NumElemVT; i < 4; ++i) {
1257 Loads[i] = DAG.getUNDEF(ElemVT);
1259 EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4);
1260 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads, 4);
1262 LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
1264 DAG.getTargetConstant(0, MVT::i32), // Channel
1269 Ops[0] = LoweredLoad;
1272 return DAG.getMergeValues(Ops, 2, DL);
1275 /// XXX Only kernel functions are supported, so we can assume for now that
1276 /// every function is a kernel function, but in the future we should use
1277 /// separate calling conventions for kernel and non-kernel functions.
1278 SDValue R600TargetLowering::LowerFormalArguments(
1280 CallingConv::ID CallConv,
1282 const SmallVectorImpl<ISD::InputArg> &Ins,
1283 SDLoc DL, SelectionDAG &DAG,
1284 SmallVectorImpl<SDValue> &InVals) const {
1285 SmallVector<CCValAssign, 16> ArgLocs;
1286 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1287 getTargetMachine(), ArgLocs, *DAG.getContext());
1289 AnalyzeFormalArguments(CCInfo, Ins);
1291 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1292 CCValAssign &VA = ArgLocs[i];
1293 EVT VT = VA.getLocVT();
1295 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1296 AMDGPUAS::CONSTANT_BUFFER_0);
1298 // The first 36 bytes of the input buffer contains information about
1299 // thread group and global sizes.
1300 SDValue Arg = DAG.getLoad(VT, DL, Chain,
1301 DAG.getConstant(36 + VA.getLocMemOffset(), MVT::i32),
1302 MachinePointerInfo(UndefValue::get(PtrTy)), false,
1303 false, false, 4); // 4 is the prefered alignment for
1304 // the CONSTANT memory space.
1305 InVals.push_back(Arg);
1310 EVT R600TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1311 if (!VT.isVector()) return MVT::i32;
1312 return VT.changeVectorElementTypeToInteger();
1316 CompactSwizzlableVector(SelectionDAG &DAG, SDValue VectorEntry,
1317 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1318 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1319 assert(RemapSwizzle.empty());
1320 SDValue NewBldVec[4] = {
1321 VectorEntry.getOperand(0),
1322 VectorEntry.getOperand(1),
1323 VectorEntry.getOperand(2),
1324 VectorEntry.getOperand(3)
1327 for (unsigned i = 0; i < 4; i++) {
1328 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(NewBldVec[i])) {
1330 RemapSwizzle[i] = 4; // SEL_0
1331 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1332 } else if (C->isExactlyValue(1.0)) {
1333 RemapSwizzle[i] = 5; // SEL_1
1334 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1338 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1340 for (unsigned j = 0; j < i; j++) {
1341 if (NewBldVec[i] == NewBldVec[j]) {
1342 NewBldVec[i] = DAG.getUNDEF(NewBldVec[i].getValueType());
1343 RemapSwizzle[i] = j;
1349 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1350 VectorEntry.getValueType(), NewBldVec, 4);
1353 static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
1354 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1355 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1356 assert(RemapSwizzle.empty());
1357 SDValue NewBldVec[4] = {
1358 VectorEntry.getOperand(0),
1359 VectorEntry.getOperand(1),
1360 VectorEntry.getOperand(2),
1361 VectorEntry.getOperand(3)
1363 bool isUnmovable[4] = { false, false, false, false };
1364 for (unsigned i = 0; i < 4; i++)
1365 RemapSwizzle[i] = i;
1367 for (unsigned i = 0; i < 4; i++) {
1368 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1369 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1371 if (!isUnmovable[Idx]) {
1373 std::swap(NewBldVec[Idx], NewBldVec[i]);
1374 std::swap(RemapSwizzle[RemapSwizzle[Idx]], RemapSwizzle[RemapSwizzle[i]]);
1376 isUnmovable[Idx] = true;
1380 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1381 VectorEntry.getValueType(), NewBldVec, 4);
1385 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector,
1386 SDValue Swz[4], SelectionDAG &DAG) const {
1387 assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR);
1388 // Old -> New swizzle values
1389 DenseMap<unsigned, unsigned> SwizzleRemap;
1391 BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap);
1392 for (unsigned i = 0; i < 4; i++) {
1393 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1394 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1395 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1398 SwizzleRemap.clear();
1399 BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap);
1400 for (unsigned i = 0; i < 4; i++) {
1401 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1402 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1403 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1410 //===----------------------------------------------------------------------===//
1411 // Custom DAG Optimizations
1412 //===----------------------------------------------------------------------===//
1414 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1415 DAGCombinerInfo &DCI) const {
1416 SelectionDAG &DAG = DCI.DAG;
1418 switch (N->getOpcode()) {
1419 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1420 case ISD::FP_ROUND: {
1421 SDValue Arg = N->getOperand(0);
1422 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1423 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), N->getValueType(0),
1429 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1430 // (i32 select_cc f32, f32, -1, 0 cc)
1432 // Mesa's GLSL frontend generates the above pattern a lot and we can lower
1433 // this to one of the SET*_DX10 instructions.
1434 case ISD::FP_TO_SINT: {
1435 SDValue FNeg = N->getOperand(0);
1436 if (FNeg.getOpcode() != ISD::FNEG) {
1439 SDValue SelectCC = FNeg.getOperand(0);
1440 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1441 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1442 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1443 !isHWTrueValue(SelectCC.getOperand(2)) ||
1444 !isHWFalseValue(SelectCC.getOperand(3))) {
1448 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
1449 SelectCC.getOperand(0), // LHS
1450 SelectCC.getOperand(1), // RHS
1451 DAG.getConstant(-1, MVT::i32), // True
1452 DAG.getConstant(0, MVT::i32), // Flase
1453 SelectCC.getOperand(4)); // CC
1458 // insert_vector_elt (build_vector elt0, …, eltN), NewEltIdx, idx
1459 // => build_vector elt0, …, NewEltIdx, …, eltN
1460 case ISD::INSERT_VECTOR_ELT: {
1461 SDValue InVec = N->getOperand(0);
1462 SDValue InVal = N->getOperand(1);
1463 SDValue EltNo = N->getOperand(2);
1466 // If the inserted element is an UNDEF, just use the input vector.
1467 if (InVal.getOpcode() == ISD::UNDEF)
1470 EVT VT = InVec.getValueType();
1472 // If we can't generate a legal BUILD_VECTOR, exit
1473 if (!isOperationLegal(ISD::BUILD_VECTOR, VT))
1476 // Check that we know which element is being inserted
1477 if (!isa<ConstantSDNode>(EltNo))
1479 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
1481 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
1482 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
1484 SmallVector<SDValue, 8> Ops;
1485 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
1486 Ops.append(InVec.getNode()->op_begin(),
1487 InVec.getNode()->op_end());
1488 } else if (InVec.getOpcode() == ISD::UNDEF) {
1489 unsigned NElts = VT.getVectorNumElements();
1490 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
1495 // Insert the element
1496 if (Elt < Ops.size()) {
1497 // All the operands of BUILD_VECTOR must have the same type;
1498 // we enforce that here.
1499 EVT OpVT = Ops[0].getValueType();
1500 if (InVal.getValueType() != OpVT)
1501 InVal = OpVT.bitsGT(InVal.getValueType()) ?
1502 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
1503 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
1507 // Return the new vector
1508 return DAG.getNode(ISD::BUILD_VECTOR, dl,
1509 VT, &Ops[0], Ops.size());
1512 // Extract_vec (Build_vector) generated by custom lowering
1513 // also needs to be customly combined
1514 case ISD::EXTRACT_VECTOR_ELT: {
1515 SDValue Arg = N->getOperand(0);
1516 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1517 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1518 unsigned Element = Const->getZExtValue();
1519 return Arg->getOperand(Element);
1522 if (Arg.getOpcode() == ISD::BITCAST &&
1523 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1524 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1525 unsigned Element = Const->getZExtValue();
1526 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getVTList(),
1527 Arg->getOperand(0).getOperand(Element));
1532 case ISD::SELECT_CC: {
1533 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1534 // selectcc x, y, a, b, inv(cc)
1536 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
1537 // selectcc x, y, a, b, cc
1538 SDValue LHS = N->getOperand(0);
1539 if (LHS.getOpcode() != ISD::SELECT_CC) {
1543 SDValue RHS = N->getOperand(1);
1544 SDValue True = N->getOperand(2);
1545 SDValue False = N->getOperand(3);
1546 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1548 if (LHS.getOperand(2).getNode() != True.getNode() ||
1549 LHS.getOperand(3).getNode() != False.getNode() ||
1550 RHS.getNode() != False.getNode()) {
1555 default: return SDValue();
1556 case ISD::SETNE: return LHS;
1558 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
1559 LHSCC = ISD::getSetCCInverse(LHSCC,
1560 LHS.getOperand(0).getValueType().isInteger());
1561 return DAG.getSelectCC(SDLoc(N),
1571 case AMDGPUISD::EXPORT: {
1572 SDValue Arg = N->getOperand(1);
1573 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1576 SDValue NewArgs[8] = {
1577 N->getOperand(0), // Chain
1579 N->getOperand(2), // ArrayBase
1580 N->getOperand(3), // Type
1581 N->getOperand(4), // SWZ_X
1582 N->getOperand(5), // SWZ_Y
1583 N->getOperand(6), // SWZ_Z
1584 N->getOperand(7) // SWZ_W
1587 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG);
1588 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs, 8);
1590 case AMDGPUISD::TEXTURE_FETCH: {
1591 SDValue Arg = N->getOperand(1);
1592 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1595 SDValue NewArgs[19] = {
1616 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG);
1617 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, SDLoc(N), N->getVTList(),