1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for R600
13 //===----------------------------------------------------------------------===//
15 #include "R600ISelLowering.h"
16 #include "R600Defines.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineFunctionInfo.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/IR/Argument.h"
24 #include "llvm/IR/Function.h"
28 R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
29 AMDGPUTargetLowering(TM),
30 TII(static_cast<const R600InstrInfo*>(TM.getInstrInfo())) {
31 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
32 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
33 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
34 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
35 computeRegisterProperties();
37 setOperationAction(ISD::FADD, MVT::v4f32, Expand);
38 setOperationAction(ISD::FMUL, MVT::v4f32, Expand);
39 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
40 setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
42 setOperationAction(ISD::ADD, MVT::v4i32, Expand);
43 setOperationAction(ISD::AND, MVT::v4i32, Expand);
44 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Expand);
45 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Expand);
46 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Expand);
47 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand);
48 setOperationAction(ISD::UDIV, MVT::v4i32, Expand);
49 setOperationAction(ISD::UREM, MVT::v4i32, Expand);
50 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
52 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
53 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
55 setOperationAction(ISD::FSUB, MVT::f32, Expand);
57 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
58 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
59 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
61 setOperationAction(ISD::ROTL, MVT::i32, Custom);
63 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
64 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
66 setOperationAction(ISD::SETCC, MVT::i32, Expand);
67 setOperationAction(ISD::SETCC, MVT::f32, Expand);
68 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
70 setOperationAction(ISD::SELECT, MVT::i32, Custom);
71 setOperationAction(ISD::SELECT, MVT::f32, Custom);
73 // Legalize loads and stores to the private address space.
74 setOperationAction(ISD::LOAD, MVT::i32, Custom);
75 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
76 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
77 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
78 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
79 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
80 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Custom);
81 setOperationAction(ISD::STORE, MVT::i8, Custom);
82 setOperationAction(ISD::STORE, MVT::i32, Custom);
83 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
84 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
86 setOperationAction(ISD::LOAD, MVT::i32, Custom);
87 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
88 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
90 setTargetDAGCombine(ISD::FP_ROUND);
91 setTargetDAGCombine(ISD::FP_TO_SINT);
92 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
93 setTargetDAGCombine(ISD::SELECT_CC);
95 setBooleanContents(ZeroOrNegativeOneBooleanContent);
96 setSchedulingPreference(Sched::VLIW);
99 MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
100 MachineInstr * MI, MachineBasicBlock * BB) const {
101 MachineFunction * MF = BB->getParent();
102 MachineRegisterInfo &MRI = MF->getRegInfo();
103 MachineBasicBlock::iterator I = *MI;
105 switch (MI->getOpcode()) {
106 default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
107 case AMDGPU::CLAMP_R600: {
108 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
110 MI->getOperand(0).getReg(),
111 MI->getOperand(1).getReg());
112 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
116 case AMDGPU::FABS_R600: {
117 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
119 MI->getOperand(0).getReg(),
120 MI->getOperand(1).getReg());
121 TII->addFlag(NewMI, 0, MO_FLAG_ABS);
125 case AMDGPU::FNEG_R600: {
126 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
128 MI->getOperand(0).getReg(),
129 MI->getOperand(1).getReg());
130 TII->addFlag(NewMI, 0, MO_FLAG_NEG);
134 case AMDGPU::MASK_WRITE: {
135 unsigned maskedRegister = MI->getOperand(0).getReg();
136 assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
137 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
138 TII->addFlag(defInstr, 0, MO_FLAG_MASK);
142 case AMDGPU::MOV_IMM_F32:
143 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
144 MI->getOperand(1).getFPImm()->getValueAPF()
145 .bitcastToAPInt().getZExtValue());
147 case AMDGPU::MOV_IMM_I32:
148 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
149 MI->getOperand(1).getImm());
151 case AMDGPU::CONST_COPY: {
152 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
153 MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
154 TII->setImmOperand(NewMI, R600Operands::SRC0_SEL,
155 MI->getOperand(1).getImm());
159 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
160 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
161 unsigned EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
163 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
164 .addOperand(MI->getOperand(0))
165 .addOperand(MI->getOperand(1))
166 .addImm(EOP); // Set End of program bit
171 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
172 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
174 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
175 .addOperand(MI->getOperand(3))
176 .addOperand(MI->getOperand(4))
177 .addOperand(MI->getOperand(5))
178 .addOperand(MI->getOperand(6));
179 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
180 .addOperand(MI->getOperand(2))
181 .addOperand(MI->getOperand(4))
182 .addOperand(MI->getOperand(5))
183 .addOperand(MI->getOperand(6));
184 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
185 .addOperand(MI->getOperand(0))
186 .addOperand(MI->getOperand(1))
187 .addOperand(MI->getOperand(4))
188 .addOperand(MI->getOperand(5))
189 .addOperand(MI->getOperand(6))
190 .addReg(T0, RegState::Implicit)
191 .addReg(T1, RegState::Implicit);
195 case AMDGPU::TXD_SHADOW: {
196 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
197 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
199 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
200 .addOperand(MI->getOperand(3))
201 .addOperand(MI->getOperand(4))
202 .addOperand(MI->getOperand(5))
203 .addOperand(MI->getOperand(6));
204 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
205 .addOperand(MI->getOperand(2))
206 .addOperand(MI->getOperand(4))
207 .addOperand(MI->getOperand(5))
208 .addOperand(MI->getOperand(6));
209 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
210 .addOperand(MI->getOperand(0))
211 .addOperand(MI->getOperand(1))
212 .addOperand(MI->getOperand(4))
213 .addOperand(MI->getOperand(5))
214 .addOperand(MI->getOperand(6))
215 .addReg(T0, RegState::Implicit)
216 .addReg(T1, RegState::Implicit);
221 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
222 .addOperand(MI->getOperand(0));
225 case AMDGPU::BRANCH_COND_f32: {
226 MachineInstr *NewMI =
227 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
228 AMDGPU::PREDICATE_BIT)
229 .addOperand(MI->getOperand(1))
230 .addImm(OPCODE_IS_NOT_ZERO)
232 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
233 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
234 .addOperand(MI->getOperand(0))
235 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
239 case AMDGPU::BRANCH_COND_i32: {
240 MachineInstr *NewMI =
241 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
242 AMDGPU::PREDICATE_BIT)
243 .addOperand(MI->getOperand(1))
244 .addImm(OPCODE_IS_NOT_ZERO_INT)
246 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
247 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
248 .addOperand(MI->getOperand(0))
249 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
253 case AMDGPU::EG_ExportSwz:
254 case AMDGPU::R600_ExportSwz: {
255 // Instruction is left unmodified if its not the last one of its type
256 bool isLastInstructionOfItsType = true;
257 unsigned InstExportType = MI->getOperand(1).getImm();
258 for (MachineBasicBlock::iterator NextExportInst = llvm::next(I),
259 EndBlock = BB->end(); NextExportInst != EndBlock;
260 NextExportInst = llvm::next(NextExportInst)) {
261 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
262 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
263 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
265 if (CurrentInstExportType == InstExportType) {
266 isLastInstructionOfItsType = false;
271 bool EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN)? 1 : 0;
272 if (!EOP && !isLastInstructionOfItsType)
274 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
275 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
276 .addOperand(MI->getOperand(0))
277 .addOperand(MI->getOperand(1))
278 .addOperand(MI->getOperand(2))
279 .addOperand(MI->getOperand(3))
280 .addOperand(MI->getOperand(4))
281 .addOperand(MI->getOperand(5))
282 .addOperand(MI->getOperand(6))
287 case AMDGPU::RETURN: {
288 // RETURN instructions must have the live-out registers as implicit uses,
289 // otherwise they appear dead.
290 R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
291 MachineInstrBuilder MIB(*MF, MI);
292 for (unsigned i = 0, e = MFI->LiveOuts.size(); i != e; ++i)
293 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
298 MI->eraseFromParent();
302 //===----------------------------------------------------------------------===//
303 // Custom DAG Lowering Operations
304 //===----------------------------------------------------------------------===//
306 using namespace llvm::Intrinsic;
307 using namespace llvm::AMDGPUIntrinsic;
309 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
310 switch (Op.getOpcode()) {
311 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
312 case ISD::ROTL: return LowerROTL(Op, DAG);
313 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
314 case ISD::SELECT: return LowerSELECT(Op, DAG);
315 case ISD::STORE: return LowerSTORE(Op, DAG);
316 case ISD::LOAD: return LowerLOAD(Op, DAG);
317 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
318 case ISD::INTRINSIC_VOID: {
319 SDValue Chain = Op.getOperand(0);
320 unsigned IntrinsicID =
321 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
322 switch (IntrinsicID) {
323 case AMDGPUIntrinsic::AMDGPU_store_output: {
324 MachineFunction &MF = DAG.getMachineFunction();
325 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
326 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
327 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
328 MFI->LiveOuts.push_back(Reg);
329 return DAG.getCopyToReg(Chain, Op.getDebugLoc(), Reg, Op.getOperand(2));
331 case AMDGPUIntrinsic::R600_store_swizzle: {
332 const SDValue Args[8] = {
334 Op.getOperand(2), // Export Value
335 Op.getOperand(3), // ArrayBase
336 Op.getOperand(4), // Type
337 DAG.getConstant(0, MVT::i32), // SWZ_X
338 DAG.getConstant(1, MVT::i32), // SWZ_Y
339 DAG.getConstant(2, MVT::i32), // SWZ_Z
340 DAG.getConstant(3, MVT::i32) // SWZ_W
342 return DAG.getNode(AMDGPUISD::EXPORT, Op.getDebugLoc(), Op.getValueType(),
346 // default for switch(IntrinsicID)
349 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
352 case ISD::INTRINSIC_WO_CHAIN: {
353 unsigned IntrinsicID =
354 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
355 EVT VT = Op.getValueType();
356 DebugLoc DL = Op.getDebugLoc();
357 switch(IntrinsicID) {
358 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
359 case AMDGPUIntrinsic::R600_load_input: {
360 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
361 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
362 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
365 case AMDGPUIntrinsic::R600_interp_input: {
366 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
367 int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
368 MachineSDNode *interp;
370 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
371 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
372 return DAG.getTargetExtractSubreg(
373 TII->getRegisterInfo().getSubRegFromChannel(slot % 4),
374 DL, MVT::f32, SDValue(interp, 0));
378 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
379 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
380 CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
381 AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1), MVT::f32),
382 CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
383 AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb), MVT::f32));
385 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
386 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
387 CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
388 AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1), MVT::f32),
389 CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
390 AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb), MVT::f32));
392 return SDValue(interp, slot % 2);
395 case r600_read_ngroups_x:
396 return LowerImplicitParameter(DAG, VT, DL, 0);
397 case r600_read_ngroups_y:
398 return LowerImplicitParameter(DAG, VT, DL, 1);
399 case r600_read_ngroups_z:
400 return LowerImplicitParameter(DAG, VT, DL, 2);
401 case r600_read_global_size_x:
402 return LowerImplicitParameter(DAG, VT, DL, 3);
403 case r600_read_global_size_y:
404 return LowerImplicitParameter(DAG, VT, DL, 4);
405 case r600_read_global_size_z:
406 return LowerImplicitParameter(DAG, VT, DL, 5);
407 case r600_read_local_size_x:
408 return LowerImplicitParameter(DAG, VT, DL, 6);
409 case r600_read_local_size_y:
410 return LowerImplicitParameter(DAG, VT, DL, 7);
411 case r600_read_local_size_z:
412 return LowerImplicitParameter(DAG, VT, DL, 8);
414 case r600_read_tgid_x:
415 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
417 case r600_read_tgid_y:
418 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
420 case r600_read_tgid_z:
421 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
423 case r600_read_tidig_x:
424 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
426 case r600_read_tidig_y:
427 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
429 case r600_read_tidig_z:
430 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
433 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
436 } // end switch(Op.getOpcode())
440 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
441 SmallVectorImpl<SDValue> &Results,
442 SelectionDAG &DAG) const {
443 switch (N->getOpcode()) {
445 case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
448 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
449 Results.push_back(SDValue(Node, 0));
450 Results.push_back(SDValue(Node, 1));
451 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
453 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
457 SDNode *Node = LowerSTORE(SDValue(N, 0), DAG).getNode();
458 Results.push_back(SDValue(Node, 0));
463 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
468 Op, DAG.getConstantFP(0.0f, MVT::f32),
469 DAG.getCondCode(ISD::SETNE)
473 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
475 unsigned DwordOffset) const {
476 unsigned ByteOffset = DwordOffset * 4;
477 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
478 AMDGPUAS::PARAM_I_ADDRESS);
480 // We shouldn't be using an offset wider than 16-bits for implicit parameters.
481 assert(isInt<16>(ByteOffset));
483 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
484 DAG.getConstant(ByteOffset, MVT::i32), // PTR
485 MachinePointerInfo(ConstantPointerNull::get(PtrType)),
486 false, false, false, 0);
489 SDValue R600TargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
491 MachineFunction &MF = DAG.getMachineFunction();
492 const AMDGPUFrameLowering *TFL =
493 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
495 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op);
498 unsigned FrameIndex = FIN->getIndex();
499 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
500 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), MVT::i32);
503 SDValue R600TargetLowering::LowerROTL(SDValue Op, SelectionDAG &DAG) const {
504 DebugLoc DL = Op.getDebugLoc();
505 EVT VT = Op.getValueType();
507 return DAG.getNode(AMDGPUISD::BITALIGN, DL, VT,
510 DAG.getNode(ISD::SUB, DL, VT,
511 DAG.getConstant(32, MVT::i32),
515 bool R600TargetLowering::isZero(SDValue Op) const {
516 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
517 return Cst->isNullValue();
518 } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
519 return CstFP->isZero();
525 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
526 DebugLoc DL = Op.getDebugLoc();
527 EVT VT = Op.getValueType();
529 SDValue LHS = Op.getOperand(0);
530 SDValue RHS = Op.getOperand(1);
531 SDValue True = Op.getOperand(2);
532 SDValue False = Op.getOperand(3);
533 SDValue CC = Op.getOperand(4);
536 // LHS and RHS are guaranteed to be the same value type
537 EVT CompareVT = LHS.getValueType();
539 // Check if we can lower this to a native operation.
541 // Try to lower to a SET* instruction:
543 // SET* can match the following patterns:
545 // select_cc f32, f32, -1, 0, cc_any
546 // select_cc f32, f32, 1.0f, 0.0f, cc_any
547 // select_cc i32, i32, -1, 0, cc_any
550 // Move hardware True/False values to the correct operand.
551 if (isHWTrueValue(False) && isHWFalseValue(True)) {
552 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
553 std::swap(False, True);
554 CC = DAG.getCondCode(ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32));
557 if (isHWTrueValue(True) && isHWFalseValue(False) &&
558 (CompareVT == VT || VT == MVT::i32)) {
559 // This can be matched by a SET* instruction.
560 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
563 // Try to lower to a CND* instruction:
565 // CND* can match the following patterns:
567 // select_cc f32, 0.0, f32, f32, cc_any
568 // select_cc f32, 0.0, i32, i32, cc_any
569 // select_cc i32, 0, f32, f32, cc_any
570 // select_cc i32, 0, i32, i32, cc_any
572 if (isZero(LHS) || isZero(RHS)) {
573 SDValue Cond = (isZero(LHS) ? RHS : LHS);
574 SDValue Zero = (isZero(LHS) ? LHS : RHS);
575 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
576 if (CompareVT != VT) {
577 // Bitcast True / False to the correct types. This will end up being
578 // a nop, but it allows us to define only a single pattern in the
579 // .TD files for each CND* instruction rather than having to have
580 // one pattern for integer True/False and one for fp True/False
581 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
582 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
585 CCOpcode = ISD::getSetCCSwappedOperands(CCOpcode);
598 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
606 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
609 DAG.getCondCode(CCOpcode));
610 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
614 // Possible Min/Max pattern
615 SDValue MinMax = LowerMinMax(Op, DAG);
616 if (MinMax.getNode()) {
620 // If we make it this for it means we have no native instructions to handle
621 // this SELECT_CC, so we must lower it.
622 SDValue HWTrue, HWFalse;
624 if (CompareVT == MVT::f32) {
625 HWTrue = DAG.getConstantFP(1.0f, CompareVT);
626 HWFalse = DAG.getConstantFP(0.0f, CompareVT);
627 } else if (CompareVT == MVT::i32) {
628 HWTrue = DAG.getConstant(-1, CompareVT);
629 HWFalse = DAG.getConstant(0, CompareVT);
632 assert(!"Unhandled value type in LowerSELECT_CC");
635 // Lower this unsupported SELECT_CC into a combination of two supported
636 // SELECT_CC operations.
637 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
639 return DAG.getNode(ISD::SELECT_CC, DL, VT,
642 DAG.getCondCode(ISD::SETNE));
645 SDValue R600TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
646 return DAG.getNode(ISD::SELECT_CC,
650 DAG.getConstant(0, MVT::i32),
653 DAG.getCondCode(ISD::SETNE));
656 /// LLVM generates byte-addresed pointers. For indirect addressing, we need to
657 /// convert these pointers to a register index. Each register holds
658 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
659 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
660 /// for indirect addressing.
661 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
663 SelectionDAG &DAG) const {
675 default: llvm_unreachable("Invalid stack width");
678 return DAG.getNode(ISD::SRL, Ptr.getDebugLoc(), Ptr.getValueType(), Ptr,
679 DAG.getConstant(SRLPad, MVT::i32));
682 void R600TargetLowering::getStackAddress(unsigned StackWidth,
685 unsigned &PtrIncr) const {
686 switch (StackWidth) {
697 Channel = ElemIdx % 2;
711 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
712 DebugLoc DL = Op.getDebugLoc();
713 StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
714 SDValue Chain = Op.getOperand(0);
715 SDValue Value = Op.getOperand(1);
716 SDValue Ptr = Op.getOperand(2);
718 if (StoreNode->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
719 Ptr->getOpcode() != AMDGPUISD::DWORDADDR) {
720 // Convert pointer from byte address to dword address.
721 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(),
722 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
723 Ptr, DAG.getConstant(2, MVT::i32)));
725 if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
726 assert(!"Truncated and indexed stores not supported yet");
728 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
733 EVT ValueVT = Value.getValueType();
735 if (StoreNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
739 // Lowering for indirect addressing
741 const MachineFunction &MF = DAG.getMachineFunction();
742 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
743 getTargetMachine().getFrameLowering());
744 unsigned StackWidth = TFL->getStackWidth(MF);
746 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
748 if (ValueVT.isVector()) {
749 unsigned NumElemVT = ValueVT.getVectorNumElements();
750 EVT ElemVT = ValueVT.getVectorElementType();
753 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
754 "vector width in load");
756 for (unsigned i = 0; i < NumElemVT; ++i) {
757 unsigned Channel, PtrIncr;
758 getStackAddress(StackWidth, i, Channel, PtrIncr);
759 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
760 DAG.getConstant(PtrIncr, MVT::i32));
761 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
762 Value, DAG.getConstant(i, MVT::i32));
764 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
766 DAG.getTargetConstant(Channel, MVT::i32));
768 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores, NumElemVT);
770 if (ValueVT == MVT::i8) {
771 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
773 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
774 DAG.getTargetConstant(0, MVT::i32)); // Channel
780 // return (512 + (kc_bank << 12)
782 ConstantAddressBlock(unsigned AddressSpace) {
783 switch (AddressSpace) {
784 case AMDGPUAS::CONSTANT_BUFFER_0:
786 case AMDGPUAS::CONSTANT_BUFFER_1:
788 case AMDGPUAS::CONSTANT_BUFFER_2:
789 return 512 + 4096 * 2;
790 case AMDGPUAS::CONSTANT_BUFFER_3:
791 return 512 + 4096 * 3;
792 case AMDGPUAS::CONSTANT_BUFFER_4:
793 return 512 + 4096 * 4;
794 case AMDGPUAS::CONSTANT_BUFFER_5:
795 return 512 + 4096 * 5;
796 case AMDGPUAS::CONSTANT_BUFFER_6:
797 return 512 + 4096 * 6;
798 case AMDGPUAS::CONSTANT_BUFFER_7:
799 return 512 + 4096 * 7;
800 case AMDGPUAS::CONSTANT_BUFFER_8:
801 return 512 + 4096 * 8;
802 case AMDGPUAS::CONSTANT_BUFFER_9:
803 return 512 + 4096 * 9;
804 case AMDGPUAS::CONSTANT_BUFFER_10:
805 return 512 + 4096 * 10;
806 case AMDGPUAS::CONSTANT_BUFFER_11:
807 return 512 + 4096 * 11;
808 case AMDGPUAS::CONSTANT_BUFFER_12:
809 return 512 + 4096 * 12;
810 case AMDGPUAS::CONSTANT_BUFFER_13:
811 return 512 + 4096 * 13;
812 case AMDGPUAS::CONSTANT_BUFFER_14:
813 return 512 + 4096 * 14;
814 case AMDGPUAS::CONSTANT_BUFFER_15:
815 return 512 + 4096 * 15;
821 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
823 EVT VT = Op.getValueType();
824 DebugLoc DL = Op.getDebugLoc();
825 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
826 SDValue Chain = Op.getOperand(0);
827 SDValue Ptr = Op.getOperand(1);
830 int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
831 if (ConstantBlock > -1) {
833 if (dyn_cast<ConstantExpr>(LoadNode->getSrcValue()) ||
834 dyn_cast<Constant>(LoadNode->getSrcValue()) ||
835 dyn_cast<ConstantSDNode>(Ptr)) {
837 for (unsigned i = 0; i < 4; i++) {
838 // We want Const position encoded with the following formula :
839 // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
840 // const_index is Ptr computed by llvm using an alignment of 16.
841 // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
842 // then div by 4 at the ISel step
843 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
844 DAG.getConstant(4 * i + ConstantBlock * 16, MVT::i32));
845 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
847 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Slots, 4);
849 // non constant ptr cant be folded, keeps it as a v4f32 load
850 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
851 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
852 DAG.getConstant(LoadNode->getAddressSpace() -
853 AMDGPUAS::CONSTANT_BUFFER_0, MVT::i32)
857 if (!VT.isVector()) {
858 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
859 DAG.getConstant(0, MVT::i32));
862 SDValue MergedValues[2] = {
866 return DAG.getMergeValues(MergedValues, 2, DL);
869 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
873 // Lowering for indirect addressing
874 const MachineFunction &MF = DAG.getMachineFunction();
875 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
876 getTargetMachine().getFrameLowering());
877 unsigned StackWidth = TFL->getStackWidth(MF);
879 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
882 unsigned NumElemVT = VT.getVectorNumElements();
883 EVT ElemVT = VT.getVectorElementType();
886 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
887 "vector width in load");
889 for (unsigned i = 0; i < NumElemVT; ++i) {
890 unsigned Channel, PtrIncr;
891 getStackAddress(StackWidth, i, Channel, PtrIncr);
892 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
893 DAG.getConstant(PtrIncr, MVT::i32));
894 Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT,
896 DAG.getTargetConstant(Channel, MVT::i32),
899 for (unsigned i = NumElemVT; i < 4; ++i) {
900 Loads[i] = DAG.getUNDEF(ElemVT);
902 EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4);
903 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads, 4);
905 LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
907 DAG.getTargetConstant(0, MVT::i32), // Channel
912 Ops[0] = LoweredLoad;
915 return DAG.getMergeValues(Ops, 2, DL);
918 /// XXX Only kernel functions are supported, so we can assume for now that
919 /// every function is a kernel function, but in the future we should use
920 /// separate calling conventions for kernel and non-kernel functions.
921 SDValue R600TargetLowering::LowerFormalArguments(
923 CallingConv::ID CallConv,
925 const SmallVectorImpl<ISD::InputArg> &Ins,
926 DebugLoc DL, SelectionDAG &DAG,
927 SmallVectorImpl<SDValue> &InVals) const {
928 unsigned ParamOffsetBytes = 36;
929 Function::const_arg_iterator FuncArg =
930 DAG.getMachineFunction().getFunction()->arg_begin();
931 for (unsigned i = 0, e = Ins.size(); i < e; ++i, ++FuncArg) {
933 Type *ArgType = FuncArg->getType();
934 unsigned ArgSizeInBits = ArgType->isPointerTy() ?
935 32 : ArgType->getPrimitiveSizeInBits();
936 unsigned ArgBytes = ArgSizeInBits >> 3;
938 if (ArgSizeInBits < VT.getSizeInBits()) {
939 assert(!ArgType->isFloatTy() &&
940 "Extending floating point arguments not supported yet");
941 ArgVT = MVT::getIntegerVT(ArgSizeInBits);
945 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
946 AMDGPUAS::PARAM_I_ADDRESS);
947 SDValue Arg = DAG.getExtLoad(ISD::ZEXTLOAD, DL, VT, DAG.getRoot(),
948 DAG.getConstant(ParamOffsetBytes, MVT::i32),
949 MachinePointerInfo(UndefValue::get(PtrTy)),
950 ArgVT, false, false, ArgBytes);
951 InVals.push_back(Arg);
952 ParamOffsetBytes += ArgBytes;
957 EVT R600TargetLowering::getSetCCResultType(EVT VT) const {
958 if (!VT.isVector()) return MVT::i32;
959 return VT.changeVectorElementTypeToInteger();
962 //===----------------------------------------------------------------------===//
963 // Custom DAG Optimizations
964 //===----------------------------------------------------------------------===//
966 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
967 DAGCombinerInfo &DCI) const {
968 SelectionDAG &DAG = DCI.DAG;
970 switch (N->getOpcode()) {
971 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
972 case ISD::FP_ROUND: {
973 SDValue Arg = N->getOperand(0);
974 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
975 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), N->getValueType(0),
981 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
982 // (i32 select_cc f32, f32, -1, 0 cc)
984 // Mesa's GLSL frontend generates the above pattern a lot and we can lower
985 // this to one of the SET*_DX10 instructions.
986 case ISD::FP_TO_SINT: {
987 SDValue FNeg = N->getOperand(0);
988 if (FNeg.getOpcode() != ISD::FNEG) {
991 SDValue SelectCC = FNeg.getOperand(0);
992 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
993 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
994 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
995 !isHWTrueValue(SelectCC.getOperand(2)) ||
996 !isHWFalseValue(SelectCC.getOperand(3))) {
1000 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N->getValueType(0),
1001 SelectCC.getOperand(0), // LHS
1002 SelectCC.getOperand(1), // RHS
1003 DAG.getConstant(-1, MVT::i32), // True
1004 DAG.getConstant(0, MVT::i32), // Flase
1005 SelectCC.getOperand(4)); // CC
1009 // Extract_vec (Build_vector) generated by custom lowering
1010 // also needs to be customly combined
1011 case ISD::EXTRACT_VECTOR_ELT: {
1012 SDValue Arg = N->getOperand(0);
1013 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1014 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1015 unsigned Element = Const->getZExtValue();
1016 return Arg->getOperand(Element);
1019 if (Arg.getOpcode() == ISD::BITCAST &&
1020 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1021 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1022 unsigned Element = Const->getZExtValue();
1023 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getVTList(),
1024 Arg->getOperand(0).getOperand(Element));
1029 case ISD::SELECT_CC: {
1030 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1031 // selectcc x, y, a, b, inv(cc)
1033 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
1034 // selectcc x, y, a, b, cc
1035 SDValue LHS = N->getOperand(0);
1036 if (LHS.getOpcode() != ISD::SELECT_CC) {
1040 SDValue RHS = N->getOperand(1);
1041 SDValue True = N->getOperand(2);
1042 SDValue False = N->getOperand(3);
1043 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1045 if (LHS.getOperand(2).getNode() != True.getNode() ||
1046 LHS.getOperand(3).getNode() != False.getNode() ||
1047 RHS.getNode() != False.getNode()) {
1052 default: return SDValue();
1053 case ISD::SETNE: return LHS;
1055 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
1056 LHSCC = ISD::getSetCCInverse(LHSCC,
1057 LHS.getOperand(0).getValueType().isInteger());
1058 return DAG.getSelectCC(N->getDebugLoc(),
1067 case AMDGPUISD::EXPORT: {
1068 SDValue Arg = N->getOperand(1);
1069 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1071 SDValue NewBldVec[4] = {
1072 DAG.getUNDEF(MVT::f32),
1073 DAG.getUNDEF(MVT::f32),
1074 DAG.getUNDEF(MVT::f32),
1075 DAG.getUNDEF(MVT::f32)
1077 SDValue NewArgs[8] = {
1078 N->getOperand(0), // Chain
1080 N->getOperand(2), // ArrayBase
1081 N->getOperand(3), // Type
1082 N->getOperand(4), // SWZ_X
1083 N->getOperand(5), // SWZ_Y
1084 N->getOperand(6), // SWZ_Z
1085 N->getOperand(7) // SWZ_W
1087 for (unsigned i = 0; i < Arg.getNumOperands(); i++) {
1088 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Arg.getOperand(i))) {
1090 NewArgs[4 + i] = DAG.getConstant(4, MVT::i32); // SEL_0
1091 } else if (C->isExactlyValue(1.0)) {
1092 NewArgs[4 + i] = DAG.getConstant(5, MVT::i32); // SEL_0
1094 NewBldVec[i] = Arg.getOperand(i);
1097 NewBldVec[i] = Arg.getOperand(i);
1100 DebugLoc DL = N->getDebugLoc();
1101 NewArgs[1] = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4f32, NewBldVec, 4);
1102 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs, 8);