1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for R600
13 //===----------------------------------------------------------------------===//
15 #include "R600ISelLowering.h"
16 #include "R600Defines.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineFunctionInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/IR/Argument.h"
25 #include "llvm/IR/Function.h"
29 R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
30 AMDGPUTargetLowering(TM),
31 Gen(TM.getSubtarget<AMDGPUSubtarget>().getGeneration()) {
32 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
34 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
35 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
36 computeRegisterProperties();
38 setOperationAction(ISD::FADD, MVT::v4f32, Expand);
39 setOperationAction(ISD::FMUL, MVT::v4f32, Expand);
40 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
41 setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
43 setOperationAction(ISD::FCOS, MVT::f32, Custom);
44 setOperationAction(ISD::FSIN, MVT::f32, Custom);
46 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
48 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
49 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
51 setOperationAction(ISD::FSUB, MVT::f32, Expand);
53 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
54 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
55 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
57 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
58 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
60 setOperationAction(ISD::SETCC, MVT::i32, Expand);
61 setOperationAction(ISD::SETCC, MVT::f32, Expand);
62 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
64 setOperationAction(ISD::SELECT, MVT::i32, Custom);
65 setOperationAction(ISD::SELECT, MVT::f32, Custom);
67 // Legalize loads and stores to the private address space.
68 setOperationAction(ISD::LOAD, MVT::i32, Custom);
69 setOperationAction(ISD::LOAD, MVT::v2i32, Expand);
70 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
71 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
72 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
73 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
74 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
75 setOperationAction(ISD::STORE, MVT::i8, Custom);
76 setOperationAction(ISD::STORE, MVT::i32, Custom);
77 setOperationAction(ISD::STORE, MVT::v2i32, Expand);
78 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
80 setOperationAction(ISD::LOAD, MVT::i32, Custom);
81 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
82 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
84 setTargetDAGCombine(ISD::FP_ROUND);
85 setTargetDAGCombine(ISD::FP_TO_SINT);
86 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
87 setTargetDAGCombine(ISD::SELECT_CC);
88 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
90 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
92 setBooleanContents(ZeroOrNegativeOneBooleanContent);
93 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
94 setSchedulingPreference(Sched::VLIW);
97 MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
98 MachineInstr * MI, MachineBasicBlock * BB) const {
99 MachineFunction * MF = BB->getParent();
100 MachineRegisterInfo &MRI = MF->getRegInfo();
101 MachineBasicBlock::iterator I = *MI;
102 const R600InstrInfo *TII =
103 static_cast<const R600InstrInfo*>(MF->getTarget().getInstrInfo());
105 switch (MI->getOpcode()) {
106 default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
107 case AMDGPU::CLAMP_R600: {
108 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
110 MI->getOperand(0).getReg(),
111 MI->getOperand(1).getReg());
112 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
116 case AMDGPU::FABS_R600: {
117 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
119 MI->getOperand(0).getReg(),
120 MI->getOperand(1).getReg());
121 TII->addFlag(NewMI, 0, MO_FLAG_ABS);
125 case AMDGPU::FNEG_R600: {
126 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
128 MI->getOperand(0).getReg(),
129 MI->getOperand(1).getReg());
130 TII->addFlag(NewMI, 0, MO_FLAG_NEG);
134 case AMDGPU::MASK_WRITE: {
135 unsigned maskedRegister = MI->getOperand(0).getReg();
136 assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
137 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
138 TII->addFlag(defInstr, 0, MO_FLAG_MASK);
142 case AMDGPU::LDS_READ_RET: {
143 MachineInstrBuilder NewMI = BuildMI(*BB, I, BB->findDebugLoc(I),
144 TII->get(MI->getOpcode()),
146 for (unsigned i = 1, e = MI->getNumOperands(); i < e; ++i) {
147 NewMI.addOperand(MI->getOperand(i));
149 TII->buildDefaultInstruction(*BB, I, AMDGPU::MOV,
150 MI->getOperand(0).getReg(),
155 case AMDGPU::MOV_IMM_F32:
156 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
157 MI->getOperand(1).getFPImm()->getValueAPF()
158 .bitcastToAPInt().getZExtValue());
160 case AMDGPU::MOV_IMM_I32:
161 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
162 MI->getOperand(1).getImm());
164 case AMDGPU::CONST_COPY: {
165 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
166 MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
167 TII->setImmOperand(NewMI, AMDGPU::OpName::src0_sel,
168 MI->getOperand(1).getImm());
172 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
173 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
174 unsigned EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
176 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
177 .addOperand(MI->getOperand(0))
178 .addOperand(MI->getOperand(1))
179 .addImm(EOP); // Set End of program bit
184 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
185 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
186 MachineOperand &RID = MI->getOperand(4);
187 MachineOperand &SID = MI->getOperand(5);
188 unsigned TextureId = MI->getOperand(6).getImm();
189 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
190 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
202 case 8: // ShadowRect
213 case 11: // Shadow1DArray
217 case 12: // Shadow2DArray
221 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
222 .addOperand(MI->getOperand(3))
240 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
241 .addOperand(MI->getOperand(2))
259 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
260 .addOperand(MI->getOperand(0))
261 .addOperand(MI->getOperand(1))
279 .addReg(T0, RegState::Implicit)
280 .addReg(T1, RegState::Implicit);
284 case AMDGPU::TXD_SHADOW: {
285 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
286 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
287 MachineOperand &RID = MI->getOperand(4);
288 MachineOperand &SID = MI->getOperand(5);
289 unsigned TextureId = MI->getOperand(6).getImm();
290 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
291 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
303 case 8: // ShadowRect
314 case 11: // Shadow1DArray
318 case 12: // Shadow2DArray
323 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
324 .addOperand(MI->getOperand(3))
342 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
343 .addOperand(MI->getOperand(2))
361 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
362 .addOperand(MI->getOperand(0))
363 .addOperand(MI->getOperand(1))
381 .addReg(T0, RegState::Implicit)
382 .addReg(T1, RegState::Implicit);
387 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
388 .addOperand(MI->getOperand(0));
391 case AMDGPU::BRANCH_COND_f32: {
392 MachineInstr *NewMI =
393 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
394 AMDGPU::PREDICATE_BIT)
395 .addOperand(MI->getOperand(1))
396 .addImm(OPCODE_IS_NOT_ZERO)
398 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
399 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
400 .addOperand(MI->getOperand(0))
401 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
405 case AMDGPU::BRANCH_COND_i32: {
406 MachineInstr *NewMI =
407 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
408 AMDGPU::PREDICATE_BIT)
409 .addOperand(MI->getOperand(1))
410 .addImm(OPCODE_IS_NOT_ZERO_INT)
412 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
413 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
414 .addOperand(MI->getOperand(0))
415 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
419 case AMDGPU::EG_ExportSwz:
420 case AMDGPU::R600_ExportSwz: {
421 // Instruction is left unmodified if its not the last one of its type
422 bool isLastInstructionOfItsType = true;
423 unsigned InstExportType = MI->getOperand(1).getImm();
424 for (MachineBasicBlock::iterator NextExportInst = llvm::next(I),
425 EndBlock = BB->end(); NextExportInst != EndBlock;
426 NextExportInst = llvm::next(NextExportInst)) {
427 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
428 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
429 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
431 if (CurrentInstExportType == InstExportType) {
432 isLastInstructionOfItsType = false;
437 bool EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN)? 1 : 0;
438 if (!EOP && !isLastInstructionOfItsType)
440 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
441 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
442 .addOperand(MI->getOperand(0))
443 .addOperand(MI->getOperand(1))
444 .addOperand(MI->getOperand(2))
445 .addOperand(MI->getOperand(3))
446 .addOperand(MI->getOperand(4))
447 .addOperand(MI->getOperand(5))
448 .addOperand(MI->getOperand(6))
453 case AMDGPU::RETURN: {
454 // RETURN instructions must have the live-out registers as implicit uses,
455 // otherwise they appear dead.
456 R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
457 MachineInstrBuilder MIB(*MF, MI);
458 for (unsigned i = 0, e = MFI->LiveOuts.size(); i != e; ++i)
459 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
464 MI->eraseFromParent();
468 //===----------------------------------------------------------------------===//
469 // Custom DAG Lowering Operations
470 //===----------------------------------------------------------------------===//
472 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
473 MachineFunction &MF = DAG.getMachineFunction();
474 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
475 switch (Op.getOpcode()) {
476 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
478 case ISD::FSIN: return LowerTrig(Op, DAG);
479 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
480 case ISD::SELECT: return LowerSELECT(Op, DAG);
481 case ISD::STORE: return LowerSTORE(Op, DAG);
482 case ISD::LOAD: return LowerLOAD(Op, DAG);
483 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
484 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
485 case ISD::INTRINSIC_VOID: {
486 SDValue Chain = Op.getOperand(0);
487 unsigned IntrinsicID =
488 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
489 switch (IntrinsicID) {
490 case AMDGPUIntrinsic::AMDGPU_store_output: {
491 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
492 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
493 MFI->LiveOuts.push_back(Reg);
494 return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2));
496 case AMDGPUIntrinsic::R600_store_swizzle: {
497 const SDValue Args[8] = {
499 Op.getOperand(2), // Export Value
500 Op.getOperand(3), // ArrayBase
501 Op.getOperand(4), // Type
502 DAG.getConstant(0, MVT::i32), // SWZ_X
503 DAG.getConstant(1, MVT::i32), // SWZ_Y
504 DAG.getConstant(2, MVT::i32), // SWZ_Z
505 DAG.getConstant(3, MVT::i32) // SWZ_W
507 return DAG.getNode(AMDGPUISD::EXPORT, SDLoc(Op), Op.getValueType(),
511 // default for switch(IntrinsicID)
514 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
517 case ISD::INTRINSIC_WO_CHAIN: {
518 unsigned IntrinsicID =
519 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
520 EVT VT = Op.getValueType();
522 switch(IntrinsicID) {
523 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
524 case AMDGPUIntrinsic::R600_load_input: {
525 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
526 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
527 MachineFunction &MF = DAG.getMachineFunction();
528 MachineRegisterInfo &MRI = MF.getRegInfo();
530 return DAG.getCopyFromReg(DAG.getEntryNode(),
531 SDLoc(DAG.getEntryNode()), Reg, VT);
534 case AMDGPUIntrinsic::R600_interp_input: {
535 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
536 int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
537 MachineSDNode *interp;
539 const MachineFunction &MF = DAG.getMachineFunction();
540 const R600InstrInfo *TII =
541 static_cast<const R600InstrInfo*>(MF.getTarget().getInstrInfo());
542 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
543 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
544 return DAG.getTargetExtractSubreg(
545 TII->getRegisterInfo().getSubRegFromChannel(slot % 4),
546 DL, MVT::f32, SDValue(interp, 0));
549 MachineFunction &MF = DAG.getMachineFunction();
550 MachineRegisterInfo &MRI = MF.getRegInfo();
551 unsigned RegisterI = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb);
552 unsigned RegisterJ = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1);
553 MRI.addLiveIn(RegisterI);
554 MRI.addLiveIn(RegisterJ);
555 SDValue RegisterINode = DAG.getCopyFromReg(DAG.getEntryNode(),
556 SDLoc(DAG.getEntryNode()), RegisterI, MVT::f32);
557 SDValue RegisterJNode = DAG.getCopyFromReg(DAG.getEntryNode(),
558 SDLoc(DAG.getEntryNode()), RegisterJ, MVT::f32);
561 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
562 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
563 RegisterJNode, RegisterINode);
565 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
566 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
567 RegisterJNode, RegisterINode);
568 return SDValue(interp, slot % 2);
570 case AMDGPUIntrinsic::R600_tex:
571 case AMDGPUIntrinsic::R600_texc:
572 case AMDGPUIntrinsic::R600_txl:
573 case AMDGPUIntrinsic::R600_txlc:
574 case AMDGPUIntrinsic::R600_txb:
575 case AMDGPUIntrinsic::R600_txbc:
576 case AMDGPUIntrinsic::R600_txf:
577 case AMDGPUIntrinsic::R600_txq:
578 case AMDGPUIntrinsic::R600_ddx:
579 case AMDGPUIntrinsic::R600_ddy: {
581 switch (IntrinsicID) {
582 case AMDGPUIntrinsic::R600_tex:
585 case AMDGPUIntrinsic::R600_texc:
588 case AMDGPUIntrinsic::R600_txl:
591 case AMDGPUIntrinsic::R600_txlc:
594 case AMDGPUIntrinsic::R600_txb:
597 case AMDGPUIntrinsic::R600_txbc:
600 case AMDGPUIntrinsic::R600_txf:
603 case AMDGPUIntrinsic::R600_txq:
606 case AMDGPUIntrinsic::R600_ddx:
609 case AMDGPUIntrinsic::R600_ddy:
613 llvm_unreachable("Unknow Texture Operation");
616 SDValue TexArgs[19] = {
617 DAG.getConstant(TextureOp, MVT::i32),
619 DAG.getConstant(0, MVT::i32),
620 DAG.getConstant(1, MVT::i32),
621 DAG.getConstant(2, MVT::i32),
622 DAG.getConstant(3, MVT::i32),
626 DAG.getConstant(0, MVT::i32),
627 DAG.getConstant(1, MVT::i32),
628 DAG.getConstant(2, MVT::i32),
629 DAG.getConstant(3, MVT::i32),
637 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs, 19);
639 case AMDGPUIntrinsic::AMDGPU_dp4: {
641 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
642 DAG.getConstant(0, MVT::i32)),
643 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
644 DAG.getConstant(0, MVT::i32)),
645 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
646 DAG.getConstant(1, MVT::i32)),
647 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
648 DAG.getConstant(1, MVT::i32)),
649 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
650 DAG.getConstant(2, MVT::i32)),
651 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
652 DAG.getConstant(2, MVT::i32)),
653 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
654 DAG.getConstant(3, MVT::i32)),
655 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
656 DAG.getConstant(3, MVT::i32))
658 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args, 8);
661 case Intrinsic::r600_read_ngroups_x:
662 return LowerImplicitParameter(DAG, VT, DL, 0);
663 case Intrinsic::r600_read_ngroups_y:
664 return LowerImplicitParameter(DAG, VT, DL, 1);
665 case Intrinsic::r600_read_ngroups_z:
666 return LowerImplicitParameter(DAG, VT, DL, 2);
667 case Intrinsic::r600_read_global_size_x:
668 return LowerImplicitParameter(DAG, VT, DL, 3);
669 case Intrinsic::r600_read_global_size_y:
670 return LowerImplicitParameter(DAG, VT, DL, 4);
671 case Intrinsic::r600_read_global_size_z:
672 return LowerImplicitParameter(DAG, VT, DL, 5);
673 case Intrinsic::r600_read_local_size_x:
674 return LowerImplicitParameter(DAG, VT, DL, 6);
675 case Intrinsic::r600_read_local_size_y:
676 return LowerImplicitParameter(DAG, VT, DL, 7);
677 case Intrinsic::r600_read_local_size_z:
678 return LowerImplicitParameter(DAG, VT, DL, 8);
680 case Intrinsic::r600_read_tgid_x:
681 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
683 case Intrinsic::r600_read_tgid_y:
684 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
686 case Intrinsic::r600_read_tgid_z:
687 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
689 case Intrinsic::r600_read_tidig_x:
690 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
692 case Intrinsic::r600_read_tidig_y:
693 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
695 case Intrinsic::r600_read_tidig_z:
696 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
699 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
702 } // end switch(Op.getOpcode())
706 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
707 SmallVectorImpl<SDValue> &Results,
708 SelectionDAG &DAG) const {
709 switch (N->getOpcode()) {
711 case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
714 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
715 Results.push_back(SDValue(Node, 0));
716 Results.push_back(SDValue(Node, 1));
717 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
719 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
723 SDNode *Node = LowerSTORE(SDValue(N, 0), DAG).getNode();
724 Results.push_back(SDValue(Node, 0));
729 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
730 // On hw >= R700, COS/SIN input must be between -1. and 1.
731 // Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5)
732 EVT VT = Op.getValueType();
733 SDValue Arg = Op.getOperand(0);
734 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
735 DAG.getNode(ISD::FADD, SDLoc(Op), VT,
736 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
737 DAG.getConstantFP(0.15915494309, MVT::f32)),
738 DAG.getConstantFP(0.5, MVT::f32)));
740 switch (Op.getOpcode()) {
742 TrigNode = AMDGPUISD::COS_HW;
745 TrigNode = AMDGPUISD::SIN_HW;
748 llvm_unreachable("Wrong trig opcode");
750 SDValue TrigVal = DAG.getNode(TrigNode, SDLoc(Op), VT,
751 DAG.getNode(ISD::FADD, SDLoc(Op), VT, FractPart,
752 DAG.getConstantFP(-0.5, MVT::f32)));
753 if (Gen >= AMDGPUSubtarget::R700)
755 // On R600 hw, COS/SIN input must be between -Pi and Pi.
756 return DAG.getNode(ISD::FMUL, SDLoc(Op), VT, TrigVal,
757 DAG.getConstantFP(3.14159265359, MVT::f32));
760 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
765 Op, DAG.getConstantFP(0.0f, MVT::f32),
766 DAG.getCondCode(ISD::SETNE)
770 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
772 unsigned DwordOffset) const {
773 unsigned ByteOffset = DwordOffset * 4;
774 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
775 AMDGPUAS::CONSTANT_BUFFER_0);
777 // We shouldn't be using an offset wider than 16-bits for implicit parameters.
778 assert(isInt<16>(ByteOffset));
780 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
781 DAG.getConstant(ByteOffset, MVT::i32), // PTR
782 MachinePointerInfo(ConstantPointerNull::get(PtrType)),
783 false, false, false, 0);
786 SDValue R600TargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
788 MachineFunction &MF = DAG.getMachineFunction();
789 const AMDGPUFrameLowering *TFL =
790 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
792 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op);
795 unsigned FrameIndex = FIN->getIndex();
796 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
797 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), MVT::i32);
800 bool R600TargetLowering::isZero(SDValue Op) const {
801 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
802 return Cst->isNullValue();
803 } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
804 return CstFP->isZero();
810 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
812 EVT VT = Op.getValueType();
814 SDValue LHS = Op.getOperand(0);
815 SDValue RHS = Op.getOperand(1);
816 SDValue True = Op.getOperand(2);
817 SDValue False = Op.getOperand(3);
818 SDValue CC = Op.getOperand(4);
821 // LHS and RHS are guaranteed to be the same value type
822 EVT CompareVT = LHS.getValueType();
824 // Check if we can lower this to a native operation.
826 // Try to lower to a SET* instruction:
828 // SET* can match the following patterns:
830 // select_cc f32, f32, -1, 0, cc_any
831 // select_cc f32, f32, 1.0f, 0.0f, cc_any
832 // select_cc i32, i32, -1, 0, cc_any
835 // Move hardware True/False values to the correct operand.
836 if (isHWTrueValue(False) && isHWFalseValue(True)) {
837 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
838 std::swap(False, True);
839 CC = DAG.getCondCode(ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32));
842 if (isHWTrueValue(True) && isHWFalseValue(False) &&
843 (CompareVT == VT || VT == MVT::i32)) {
844 // This can be matched by a SET* instruction.
845 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
848 // Try to lower to a CND* instruction:
850 // CND* can match the following patterns:
852 // select_cc f32, 0.0, f32, f32, cc_any
853 // select_cc f32, 0.0, i32, i32, cc_any
854 // select_cc i32, 0, f32, f32, cc_any
855 // select_cc i32, 0, i32, i32, cc_any
857 if (isZero(LHS) || isZero(RHS)) {
858 SDValue Cond = (isZero(LHS) ? RHS : LHS);
859 SDValue Zero = (isZero(LHS) ? LHS : RHS);
860 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
861 if (CompareVT != VT) {
862 // Bitcast True / False to the correct types. This will end up being
863 // a nop, but it allows us to define only a single pattern in the
864 // .TD files for each CND* instruction rather than having to have
865 // one pattern for integer True/False and one for fp True/False
866 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
867 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
870 CCOpcode = ISD::getSetCCSwappedOperands(CCOpcode);
883 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
891 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
894 DAG.getCondCode(CCOpcode));
895 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
899 // Possible Min/Max pattern
900 SDValue MinMax = LowerMinMax(Op, DAG);
901 if (MinMax.getNode()) {
905 // If we make it this for it means we have no native instructions to handle
906 // this SELECT_CC, so we must lower it.
907 SDValue HWTrue, HWFalse;
909 if (CompareVT == MVT::f32) {
910 HWTrue = DAG.getConstantFP(1.0f, CompareVT);
911 HWFalse = DAG.getConstantFP(0.0f, CompareVT);
912 } else if (CompareVT == MVT::i32) {
913 HWTrue = DAG.getConstant(-1, CompareVT);
914 HWFalse = DAG.getConstant(0, CompareVT);
917 assert(!"Unhandled value type in LowerSELECT_CC");
920 // Lower this unsupported SELECT_CC into a combination of two supported
921 // SELECT_CC operations.
922 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
924 return DAG.getNode(ISD::SELECT_CC, DL, VT,
927 DAG.getCondCode(ISD::SETNE));
930 SDValue R600TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
931 return DAG.getNode(ISD::SELECT_CC,
935 DAG.getConstant(0, MVT::i32),
938 DAG.getCondCode(ISD::SETNE));
941 /// LLVM generates byte-addresed pointers. For indirect addressing, we need to
942 /// convert these pointers to a register index. Each register holds
943 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
944 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
945 /// for indirect addressing.
946 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
948 SelectionDAG &DAG) const {
960 default: llvm_unreachable("Invalid stack width");
963 return DAG.getNode(ISD::SRL, SDLoc(Ptr), Ptr.getValueType(), Ptr,
964 DAG.getConstant(SRLPad, MVT::i32));
967 void R600TargetLowering::getStackAddress(unsigned StackWidth,
970 unsigned &PtrIncr) const {
971 switch (StackWidth) {
982 Channel = ElemIdx % 2;
996 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
998 StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
999 SDValue Chain = Op.getOperand(0);
1000 SDValue Value = Op.getOperand(1);
1001 SDValue Ptr = Op.getOperand(2);
1003 if (StoreNode->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
1004 Ptr->getOpcode() != AMDGPUISD::DWORDADDR) {
1005 // Convert pointer from byte address to dword address.
1006 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(),
1007 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
1008 Ptr, DAG.getConstant(2, MVT::i32)));
1010 if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
1011 assert(!"Truncated and indexed stores not supported yet");
1013 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
1018 EVT ValueVT = Value.getValueType();
1020 if (StoreNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1024 // Lowering for indirect addressing
1026 const MachineFunction &MF = DAG.getMachineFunction();
1027 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
1028 getTargetMachine().getFrameLowering());
1029 unsigned StackWidth = TFL->getStackWidth(MF);
1031 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1033 if (ValueVT.isVector()) {
1034 unsigned NumElemVT = ValueVT.getVectorNumElements();
1035 EVT ElemVT = ValueVT.getVectorElementType();
1038 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1039 "vector width in load");
1041 for (unsigned i = 0; i < NumElemVT; ++i) {
1042 unsigned Channel, PtrIncr;
1043 getStackAddress(StackWidth, i, Channel, PtrIncr);
1044 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1045 DAG.getConstant(PtrIncr, MVT::i32));
1046 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
1047 Value, DAG.getConstant(i, MVT::i32));
1049 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1051 DAG.getTargetConstant(Channel, MVT::i32));
1053 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores, NumElemVT);
1055 if (ValueVT == MVT::i8) {
1056 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
1058 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
1059 DAG.getTargetConstant(0, MVT::i32)); // Channel
1065 // return (512 + (kc_bank << 12)
1067 ConstantAddressBlock(unsigned AddressSpace) {
1068 switch (AddressSpace) {
1069 case AMDGPUAS::CONSTANT_BUFFER_0:
1071 case AMDGPUAS::CONSTANT_BUFFER_1:
1073 case AMDGPUAS::CONSTANT_BUFFER_2:
1074 return 512 + 4096 * 2;
1075 case AMDGPUAS::CONSTANT_BUFFER_3:
1076 return 512 + 4096 * 3;
1077 case AMDGPUAS::CONSTANT_BUFFER_4:
1078 return 512 + 4096 * 4;
1079 case AMDGPUAS::CONSTANT_BUFFER_5:
1080 return 512 + 4096 * 5;
1081 case AMDGPUAS::CONSTANT_BUFFER_6:
1082 return 512 + 4096 * 6;
1083 case AMDGPUAS::CONSTANT_BUFFER_7:
1084 return 512 + 4096 * 7;
1085 case AMDGPUAS::CONSTANT_BUFFER_8:
1086 return 512 + 4096 * 8;
1087 case AMDGPUAS::CONSTANT_BUFFER_9:
1088 return 512 + 4096 * 9;
1089 case AMDGPUAS::CONSTANT_BUFFER_10:
1090 return 512 + 4096 * 10;
1091 case AMDGPUAS::CONSTANT_BUFFER_11:
1092 return 512 + 4096 * 11;
1093 case AMDGPUAS::CONSTANT_BUFFER_12:
1094 return 512 + 4096 * 12;
1095 case AMDGPUAS::CONSTANT_BUFFER_13:
1096 return 512 + 4096 * 13;
1097 case AMDGPUAS::CONSTANT_BUFFER_14:
1098 return 512 + 4096 * 14;
1099 case AMDGPUAS::CONSTANT_BUFFER_15:
1100 return 512 + 4096 * 15;
1106 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
1108 EVT VT = Op.getValueType();
1110 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1111 SDValue Chain = Op.getOperand(0);
1112 SDValue Ptr = Op.getOperand(1);
1113 SDValue LoweredLoad;
1115 int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
1116 if (ConstantBlock > -1) {
1118 if (dyn_cast<ConstantExpr>(LoadNode->getSrcValue()) ||
1119 dyn_cast<Constant>(LoadNode->getSrcValue()) ||
1120 dyn_cast<ConstantSDNode>(Ptr)) {
1122 for (unsigned i = 0; i < 4; i++) {
1123 // We want Const position encoded with the following formula :
1124 // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
1125 // const_index is Ptr computed by llvm using an alignment of 16.
1126 // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
1127 // then div by 4 at the ISel step
1128 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1129 DAG.getConstant(4 * i + ConstantBlock * 16, MVT::i32));
1130 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1132 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Slots, 4);
1134 // non constant ptr cant be folded, keeps it as a v4f32 load
1135 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
1136 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
1137 DAG.getConstant(LoadNode->getAddressSpace() -
1138 AMDGPUAS::CONSTANT_BUFFER_0, MVT::i32)
1142 if (!VT.isVector()) {
1143 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1144 DAG.getConstant(0, MVT::i32));
1147 SDValue MergedValues[2] = {
1151 return DAG.getMergeValues(MergedValues, 2, DL);
1154 // For most operations returning SDValue() will result int he node being
1155 // expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so
1156 // we need to manually expand loads that may be legal in some address spaces
1157 // and illegal in others. SEXT loads from CONSTANT_BUFFER_0 are supported
1158 // for compute shaders, since the data is sign extended when it is uploaded
1159 // to the buffer. Howerver SEXT loads from other addresspaces are not
1160 // supported, so we need to expand them here.
1161 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
1162 EVT MemVT = LoadNode->getMemoryVT();
1163 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
1164 SDValue ShiftAmount =
1165 DAG.getConstant(VT.getSizeInBits() - MemVT.getSizeInBits(), MVT::i32);
1166 SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr,
1167 LoadNode->getPointerInfo(), MemVT,
1168 LoadNode->isVolatile(),
1169 LoadNode->isNonTemporal(),
1170 LoadNode->getAlignment());
1171 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, NewLoad, ShiftAmount);
1172 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Shl, ShiftAmount);
1174 SDValue MergedValues[2] = { Sra, Chain };
1175 return DAG.getMergeValues(MergedValues, 2, DL);
1178 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1182 // Lowering for indirect addressing
1183 const MachineFunction &MF = DAG.getMachineFunction();
1184 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
1185 getTargetMachine().getFrameLowering());
1186 unsigned StackWidth = TFL->getStackWidth(MF);
1188 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1190 if (VT.isVector()) {
1191 unsigned NumElemVT = VT.getVectorNumElements();
1192 EVT ElemVT = VT.getVectorElementType();
1195 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1196 "vector width in load");
1198 for (unsigned i = 0; i < NumElemVT; ++i) {
1199 unsigned Channel, PtrIncr;
1200 getStackAddress(StackWidth, i, Channel, PtrIncr);
1201 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1202 DAG.getConstant(PtrIncr, MVT::i32));
1203 Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT,
1205 DAG.getTargetConstant(Channel, MVT::i32),
1208 for (unsigned i = NumElemVT; i < 4; ++i) {
1209 Loads[i] = DAG.getUNDEF(ElemVT);
1211 EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4);
1212 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads, 4);
1214 LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
1216 DAG.getTargetConstant(0, MVT::i32), // Channel
1221 Ops[0] = LoweredLoad;
1224 return DAG.getMergeValues(Ops, 2, DL);
1227 /// XXX Only kernel functions are supported, so we can assume for now that
1228 /// every function is a kernel function, but in the future we should use
1229 /// separate calling conventions for kernel and non-kernel functions.
1230 SDValue R600TargetLowering::LowerFormalArguments(
1232 CallingConv::ID CallConv,
1234 const SmallVectorImpl<ISD::InputArg> &Ins,
1235 SDLoc DL, SelectionDAG &DAG,
1236 SmallVectorImpl<SDValue> &InVals) const {
1237 SmallVector<CCValAssign, 16> ArgLocs;
1238 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1239 getTargetMachine(), ArgLocs, *DAG.getContext());
1241 AnalyzeFormalArguments(CCInfo, Ins);
1243 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1244 CCValAssign &VA = ArgLocs[i];
1245 EVT VT = VA.getLocVT();
1247 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1248 AMDGPUAS::CONSTANT_BUFFER_0);
1250 // The first 36 bytes of the input buffer contains information about
1251 // thread group and global sizes.
1252 SDValue Arg = DAG.getLoad(VT, DL, Chain,
1253 DAG.getConstant(36 + VA.getLocMemOffset(), MVT::i32),
1254 MachinePointerInfo(UndefValue::get(PtrTy)), false,
1255 false, false, 4); // 4 is the prefered alignment for
1256 // the CONSTANT memory space.
1257 InVals.push_back(Arg);
1262 EVT R600TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1263 if (!VT.isVector()) return MVT::i32;
1264 return VT.changeVectorElementTypeToInteger();
1268 CompactSwizzlableVector(SelectionDAG &DAG, SDValue VectorEntry,
1269 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1270 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1271 assert(RemapSwizzle.empty());
1272 SDValue NewBldVec[4] = {
1273 VectorEntry.getOperand(0),
1274 VectorEntry.getOperand(1),
1275 VectorEntry.getOperand(2),
1276 VectorEntry.getOperand(3)
1279 for (unsigned i = 0; i < 4; i++) {
1280 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(NewBldVec[i])) {
1282 RemapSwizzle[i] = 4; // SEL_0
1283 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1284 } else if (C->isExactlyValue(1.0)) {
1285 RemapSwizzle[i] = 5; // SEL_1
1286 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1290 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1292 for (unsigned j = 0; j < i; j++) {
1293 if (NewBldVec[i] == NewBldVec[j]) {
1294 NewBldVec[i] = DAG.getUNDEF(NewBldVec[i].getValueType());
1295 RemapSwizzle[i] = j;
1301 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1302 VectorEntry.getValueType(), NewBldVec, 4);
1305 static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
1306 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1307 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1308 assert(RemapSwizzle.empty());
1309 SDValue NewBldVec[4] = {
1310 VectorEntry.getOperand(0),
1311 VectorEntry.getOperand(1),
1312 VectorEntry.getOperand(2),
1313 VectorEntry.getOperand(3)
1315 bool isUnmovable[4] = { false, false, false, false };
1316 for (unsigned i = 0; i < 4; i++)
1317 RemapSwizzle[i] = i;
1319 for (unsigned i = 0; i < 4; i++) {
1320 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1321 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1323 if (!isUnmovable[Idx]) {
1325 std::swap(NewBldVec[Idx], NewBldVec[i]);
1326 std::swap(RemapSwizzle[RemapSwizzle[Idx]], RemapSwizzle[RemapSwizzle[i]]);
1328 isUnmovable[Idx] = true;
1332 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1333 VectorEntry.getValueType(), NewBldVec, 4);
1337 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector,
1338 SDValue Swz[4], SelectionDAG &DAG) const {
1339 assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR);
1340 // Old -> New swizzle values
1341 DenseMap<unsigned, unsigned> SwizzleRemap;
1343 BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap);
1344 for (unsigned i = 0; i < 4; i++) {
1345 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1346 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1347 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1350 SwizzleRemap.clear();
1351 BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap);
1352 for (unsigned i = 0; i < 4; i++) {
1353 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1354 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1355 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1362 //===----------------------------------------------------------------------===//
1363 // Custom DAG Optimizations
1364 //===----------------------------------------------------------------------===//
1366 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1367 DAGCombinerInfo &DCI) const {
1368 SelectionDAG &DAG = DCI.DAG;
1370 switch (N->getOpcode()) {
1371 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1372 case ISD::FP_ROUND: {
1373 SDValue Arg = N->getOperand(0);
1374 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1375 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), N->getValueType(0),
1381 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1382 // (i32 select_cc f32, f32, -1, 0 cc)
1384 // Mesa's GLSL frontend generates the above pattern a lot and we can lower
1385 // this to one of the SET*_DX10 instructions.
1386 case ISD::FP_TO_SINT: {
1387 SDValue FNeg = N->getOperand(0);
1388 if (FNeg.getOpcode() != ISD::FNEG) {
1391 SDValue SelectCC = FNeg.getOperand(0);
1392 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1393 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1394 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1395 !isHWTrueValue(SelectCC.getOperand(2)) ||
1396 !isHWFalseValue(SelectCC.getOperand(3))) {
1400 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
1401 SelectCC.getOperand(0), // LHS
1402 SelectCC.getOperand(1), // RHS
1403 DAG.getConstant(-1, MVT::i32), // True
1404 DAG.getConstant(0, MVT::i32), // Flase
1405 SelectCC.getOperand(4)); // CC
1410 // insert_vector_elt (build_vector elt0, …, eltN), NewEltIdx, idx
1411 // => build_vector elt0, …, NewEltIdx, …, eltN
1412 case ISD::INSERT_VECTOR_ELT: {
1413 SDValue InVec = N->getOperand(0);
1414 SDValue InVal = N->getOperand(1);
1415 SDValue EltNo = N->getOperand(2);
1418 // If the inserted element is an UNDEF, just use the input vector.
1419 if (InVal.getOpcode() == ISD::UNDEF)
1422 EVT VT = InVec.getValueType();
1424 // If we can't generate a legal BUILD_VECTOR, exit
1425 if (!isOperationLegal(ISD::BUILD_VECTOR, VT))
1428 // Check that we know which element is being inserted
1429 if (!isa<ConstantSDNode>(EltNo))
1431 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
1433 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
1434 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
1436 SmallVector<SDValue, 8> Ops;
1437 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
1438 Ops.append(InVec.getNode()->op_begin(),
1439 InVec.getNode()->op_end());
1440 } else if (InVec.getOpcode() == ISD::UNDEF) {
1441 unsigned NElts = VT.getVectorNumElements();
1442 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
1447 // Insert the element
1448 if (Elt < Ops.size()) {
1449 // All the operands of BUILD_VECTOR must have the same type;
1450 // we enforce that here.
1451 EVT OpVT = Ops[0].getValueType();
1452 if (InVal.getValueType() != OpVT)
1453 InVal = OpVT.bitsGT(InVal.getValueType()) ?
1454 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
1455 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
1459 // Return the new vector
1460 return DAG.getNode(ISD::BUILD_VECTOR, dl,
1461 VT, &Ops[0], Ops.size());
1464 // Extract_vec (Build_vector) generated by custom lowering
1465 // also needs to be customly combined
1466 case ISD::EXTRACT_VECTOR_ELT: {
1467 SDValue Arg = N->getOperand(0);
1468 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1469 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1470 unsigned Element = Const->getZExtValue();
1471 return Arg->getOperand(Element);
1474 if (Arg.getOpcode() == ISD::BITCAST &&
1475 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1476 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1477 unsigned Element = Const->getZExtValue();
1478 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getVTList(),
1479 Arg->getOperand(0).getOperand(Element));
1484 case ISD::SELECT_CC: {
1485 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1486 // selectcc x, y, a, b, inv(cc)
1488 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
1489 // selectcc x, y, a, b, cc
1490 SDValue LHS = N->getOperand(0);
1491 if (LHS.getOpcode() != ISD::SELECT_CC) {
1495 SDValue RHS = N->getOperand(1);
1496 SDValue True = N->getOperand(2);
1497 SDValue False = N->getOperand(3);
1498 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1500 if (LHS.getOperand(2).getNode() != True.getNode() ||
1501 LHS.getOperand(3).getNode() != False.getNode() ||
1502 RHS.getNode() != False.getNode()) {
1507 default: return SDValue();
1508 case ISD::SETNE: return LHS;
1510 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
1511 LHSCC = ISD::getSetCCInverse(LHSCC,
1512 LHS.getOperand(0).getValueType().isInteger());
1513 return DAG.getSelectCC(SDLoc(N),
1522 case AMDGPUISD::EXPORT: {
1523 SDValue Arg = N->getOperand(1);
1524 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1527 SDValue NewArgs[8] = {
1528 N->getOperand(0), // Chain
1530 N->getOperand(2), // ArrayBase
1531 N->getOperand(3), // Type
1532 N->getOperand(4), // SWZ_X
1533 N->getOperand(5), // SWZ_Y
1534 N->getOperand(6), // SWZ_Z
1535 N->getOperand(7) // SWZ_W
1538 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG);
1539 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs, 8);
1541 case AMDGPUISD::TEXTURE_FETCH: {
1542 SDValue Arg = N->getOperand(1);
1543 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1546 SDValue NewArgs[19] = {
1567 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG);
1568 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, SDLoc(N), N->getVTList(),