1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for R600
13 //===----------------------------------------------------------------------===//
15 #include "R600ISelLowering.h"
16 #include "R600Defines.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineFunctionInfo.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/IR/Argument.h"
24 #include "llvm/IR/Function.h"
28 R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
29 AMDGPUTargetLowering(TM) {
30 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
31 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
32 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
34 computeRegisterProperties();
36 setOperationAction(ISD::FADD, MVT::v4f32, Expand);
37 setOperationAction(ISD::FMUL, MVT::v4f32, Expand);
38 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
39 setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
41 setOperationAction(ISD::ADD, MVT::v4i32, Expand);
42 setOperationAction(ISD::AND, MVT::v4i32, Expand);
43 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Expand);
44 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Expand);
45 setOperationAction(ISD::MUL, MVT::v2i32, Expand);
46 setOperationAction(ISD::MUL, MVT::v4i32, Expand);
47 setOperationAction(ISD::OR, MVT::v4i32, Expand);
48 setOperationAction(ISD::OR, MVT::v2i32, Expand);
49 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Expand);
50 setOperationAction(ISD::SHL, MVT::v4i32, Expand);
51 setOperationAction(ISD::SHL, MVT::v2i32, Expand);
52 setOperationAction(ISD::SRL, MVT::v4i32, Expand);
53 setOperationAction(ISD::SRL, MVT::v2i32, Expand);
54 setOperationAction(ISD::SRA, MVT::v4i32, Expand);
55 setOperationAction(ISD::SRA, MVT::v2i32, Expand);
56 setOperationAction(ISD::SUB, MVT::v4i32, Expand);
57 setOperationAction(ISD::SUB, MVT::v2i32, Expand);
58 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand);
59 setOperationAction(ISD::UDIV, MVT::v4i32, Expand);
60 setOperationAction(ISD::UREM, MVT::v4i32, Expand);
61 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
62 setOperationAction(ISD::XOR, MVT::v4i32, Expand);
63 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
65 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
66 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
68 setOperationAction(ISD::FSUB, MVT::f32, Expand);
70 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
71 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
72 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
74 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
75 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
77 setOperationAction(ISD::SETCC, MVT::i32, Expand);
78 setOperationAction(ISD::SETCC, MVT::f32, Expand);
79 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
81 setOperationAction(ISD::SELECT, MVT::i32, Custom);
82 setOperationAction(ISD::SELECT, MVT::f32, Custom);
84 setOperationAction(ISD::VSELECT, MVT::v4i32, Expand);
85 setOperationAction(ISD::VSELECT, MVT::v2i32, Expand);
87 // Legalize loads and stores to the private address space.
88 setOperationAction(ISD::LOAD, MVT::i32, Custom);
89 setOperationAction(ISD::LOAD, MVT::v2i32, Expand);
90 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
91 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
92 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
93 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
94 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Custom);
95 setOperationAction(ISD::STORE, MVT::i8, Custom);
96 setOperationAction(ISD::STORE, MVT::i32, Custom);
97 setOperationAction(ISD::STORE, MVT::v2i32, Expand);
98 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
100 setOperationAction(ISD::LOAD, MVT::i32, Custom);
101 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
102 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
104 setTargetDAGCombine(ISD::FP_ROUND);
105 setTargetDAGCombine(ISD::FP_TO_SINT);
106 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
107 setTargetDAGCombine(ISD::SELECT_CC);
109 setBooleanContents(ZeroOrNegativeOneBooleanContent);
110 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
111 setSchedulingPreference(Sched::VLIW);
114 MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
115 MachineInstr * MI, MachineBasicBlock * BB) const {
116 MachineFunction * MF = BB->getParent();
117 MachineRegisterInfo &MRI = MF->getRegInfo();
118 MachineBasicBlock::iterator I = *MI;
119 const R600InstrInfo *TII =
120 static_cast<const R600InstrInfo*>(MF->getTarget().getInstrInfo());
122 switch (MI->getOpcode()) {
123 default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
124 case AMDGPU::CLAMP_R600: {
125 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
127 MI->getOperand(0).getReg(),
128 MI->getOperand(1).getReg());
129 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
133 case AMDGPU::FABS_R600: {
134 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
136 MI->getOperand(0).getReg(),
137 MI->getOperand(1).getReg());
138 TII->addFlag(NewMI, 0, MO_FLAG_ABS);
142 case AMDGPU::FNEG_R600: {
143 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
145 MI->getOperand(0).getReg(),
146 MI->getOperand(1).getReg());
147 TII->addFlag(NewMI, 0, MO_FLAG_NEG);
151 case AMDGPU::MASK_WRITE: {
152 unsigned maskedRegister = MI->getOperand(0).getReg();
153 assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
154 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
155 TII->addFlag(defInstr, 0, MO_FLAG_MASK);
159 case AMDGPU::MOV_IMM_F32:
160 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
161 MI->getOperand(1).getFPImm()->getValueAPF()
162 .bitcastToAPInt().getZExtValue());
164 case AMDGPU::MOV_IMM_I32:
165 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
166 MI->getOperand(1).getImm());
168 case AMDGPU::CONST_COPY: {
169 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
170 MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
171 TII->setImmOperand(NewMI, R600Operands::SRC0_SEL,
172 MI->getOperand(1).getImm());
176 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
177 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
178 unsigned EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
180 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
181 .addOperand(MI->getOperand(0))
182 .addOperand(MI->getOperand(1))
183 .addImm(EOP); // Set End of program bit
188 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
189 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
190 MachineOperand &RID = MI->getOperand(4);
191 MachineOperand &SID = MI->getOperand(5);
192 unsigned TextureId = MI->getOperand(6).getImm();
193 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
194 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
206 case 8: // ShadowRect
217 case 11: // Shadow1DArray
221 case 12: // Shadow2DArray
225 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
226 .addOperand(MI->getOperand(3))
244 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
245 .addOperand(MI->getOperand(2))
263 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
264 .addOperand(MI->getOperand(0))
265 .addOperand(MI->getOperand(1))
283 .addReg(T0, RegState::Implicit)
284 .addReg(T1, RegState::Implicit);
288 case AMDGPU::TXD_SHADOW: {
289 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
290 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
291 MachineOperand &RID = MI->getOperand(4);
292 MachineOperand &SID = MI->getOperand(5);
293 unsigned TextureId = MI->getOperand(6).getImm();
294 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
295 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
307 case 8: // ShadowRect
318 case 11: // Shadow1DArray
322 case 12: // Shadow2DArray
327 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
328 .addOperand(MI->getOperand(3))
346 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
347 .addOperand(MI->getOperand(2))
365 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
366 .addOperand(MI->getOperand(0))
367 .addOperand(MI->getOperand(1))
385 .addReg(T0, RegState::Implicit)
386 .addReg(T1, RegState::Implicit);
391 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
392 .addOperand(MI->getOperand(0));
395 case AMDGPU::BRANCH_COND_f32: {
396 MachineInstr *NewMI =
397 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
398 AMDGPU::PREDICATE_BIT)
399 .addOperand(MI->getOperand(1))
400 .addImm(OPCODE_IS_NOT_ZERO)
402 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
403 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
404 .addOperand(MI->getOperand(0))
405 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
409 case AMDGPU::BRANCH_COND_i32: {
410 MachineInstr *NewMI =
411 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
412 AMDGPU::PREDICATE_BIT)
413 .addOperand(MI->getOperand(1))
414 .addImm(OPCODE_IS_NOT_ZERO_INT)
416 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
417 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
418 .addOperand(MI->getOperand(0))
419 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
423 case AMDGPU::EG_ExportSwz:
424 case AMDGPU::R600_ExportSwz: {
425 // Instruction is left unmodified if its not the last one of its type
426 bool isLastInstructionOfItsType = true;
427 unsigned InstExportType = MI->getOperand(1).getImm();
428 for (MachineBasicBlock::iterator NextExportInst = llvm::next(I),
429 EndBlock = BB->end(); NextExportInst != EndBlock;
430 NextExportInst = llvm::next(NextExportInst)) {
431 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
432 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
433 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
435 if (CurrentInstExportType == InstExportType) {
436 isLastInstructionOfItsType = false;
441 bool EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN)? 1 : 0;
442 if (!EOP && !isLastInstructionOfItsType)
444 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
445 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
446 .addOperand(MI->getOperand(0))
447 .addOperand(MI->getOperand(1))
448 .addOperand(MI->getOperand(2))
449 .addOperand(MI->getOperand(3))
450 .addOperand(MI->getOperand(4))
451 .addOperand(MI->getOperand(5))
452 .addOperand(MI->getOperand(6))
457 case AMDGPU::RETURN: {
458 // RETURN instructions must have the live-out registers as implicit uses,
459 // otherwise they appear dead.
460 R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
461 MachineInstrBuilder MIB(*MF, MI);
462 for (unsigned i = 0, e = MFI->LiveOuts.size(); i != e; ++i)
463 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
468 MI->eraseFromParent();
472 //===----------------------------------------------------------------------===//
473 // Custom DAG Lowering Operations
474 //===----------------------------------------------------------------------===//
476 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
477 switch (Op.getOpcode()) {
478 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
479 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
480 case ISD::SELECT: return LowerSELECT(Op, DAG);
481 case ISD::STORE: return LowerSTORE(Op, DAG);
482 case ISD::LOAD: return LowerLOAD(Op, DAG);
483 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
484 case ISD::INTRINSIC_VOID: {
485 SDValue Chain = Op.getOperand(0);
486 unsigned IntrinsicID =
487 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
488 switch (IntrinsicID) {
489 case AMDGPUIntrinsic::AMDGPU_store_output: {
490 MachineFunction &MF = DAG.getMachineFunction();
491 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
492 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
493 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
494 MFI->LiveOuts.push_back(Reg);
495 return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2));
497 case AMDGPUIntrinsic::R600_store_swizzle: {
498 const SDValue Args[8] = {
500 Op.getOperand(2), // Export Value
501 Op.getOperand(3), // ArrayBase
502 Op.getOperand(4), // Type
503 DAG.getConstant(0, MVT::i32), // SWZ_X
504 DAG.getConstant(1, MVT::i32), // SWZ_Y
505 DAG.getConstant(2, MVT::i32), // SWZ_Z
506 DAG.getConstant(3, MVT::i32) // SWZ_W
508 return DAG.getNode(AMDGPUISD::EXPORT, SDLoc(Op), Op.getValueType(),
512 // default for switch(IntrinsicID)
515 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
518 case ISD::INTRINSIC_WO_CHAIN: {
519 unsigned IntrinsicID =
520 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
521 EVT VT = Op.getValueType();
523 switch(IntrinsicID) {
524 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
525 case AMDGPUIntrinsic::R600_load_input: {
526 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
527 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
528 MachineFunction &MF = DAG.getMachineFunction();
529 MachineRegisterInfo &MRI = MF.getRegInfo();
531 return DAG.getCopyFromReg(DAG.getEntryNode(),
532 SDLoc(DAG.getEntryNode()), Reg, VT);
535 case AMDGPUIntrinsic::R600_interp_input: {
536 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
537 int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
538 MachineSDNode *interp;
540 const MachineFunction &MF = DAG.getMachineFunction();
541 const R600InstrInfo *TII =
542 static_cast<const R600InstrInfo*>(MF.getTarget().getInstrInfo());
543 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
544 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
545 return DAG.getTargetExtractSubreg(
546 TII->getRegisterInfo().getSubRegFromChannel(slot % 4),
547 DL, MVT::f32, SDValue(interp, 0));
550 MachineFunction &MF = DAG.getMachineFunction();
551 MachineRegisterInfo &MRI = MF.getRegInfo();
552 unsigned RegisterI = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb);
553 unsigned RegisterJ = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1);
554 MRI.addLiveIn(RegisterI);
555 MRI.addLiveIn(RegisterJ);
556 SDValue RegisterINode = DAG.getCopyFromReg(DAG.getEntryNode(),
557 SDLoc(DAG.getEntryNode()), RegisterI, MVT::f32);
558 SDValue RegisterJNode = DAG.getCopyFromReg(DAG.getEntryNode(),
559 SDLoc(DAG.getEntryNode()), RegisterJ, MVT::f32);
562 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
563 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
564 RegisterJNode, RegisterINode);
566 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
567 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
568 RegisterJNode, RegisterINode);
569 return SDValue(interp, slot % 2);
571 case AMDGPUIntrinsic::R600_tex:
572 case AMDGPUIntrinsic::R600_texc:
573 case AMDGPUIntrinsic::R600_txl:
574 case AMDGPUIntrinsic::R600_txlc:
575 case AMDGPUIntrinsic::R600_txb:
576 case AMDGPUIntrinsic::R600_txbc:
577 case AMDGPUIntrinsic::R600_txf:
578 case AMDGPUIntrinsic::R600_txq:
579 case AMDGPUIntrinsic::R600_ddx:
580 case AMDGPUIntrinsic::R600_ddy: {
582 switch (IntrinsicID) {
583 case AMDGPUIntrinsic::R600_tex:
586 case AMDGPUIntrinsic::R600_texc:
589 case AMDGPUIntrinsic::R600_txl:
592 case AMDGPUIntrinsic::R600_txlc:
595 case AMDGPUIntrinsic::R600_txb:
598 case AMDGPUIntrinsic::R600_txbc:
601 case AMDGPUIntrinsic::R600_txf:
604 case AMDGPUIntrinsic::R600_txq:
607 case AMDGPUIntrinsic::R600_ddx:
610 case AMDGPUIntrinsic::R600_ddy:
614 llvm_unreachable("Unknow Texture Operation");
617 SDValue TexArgs[19] = {
618 DAG.getConstant(TextureOp, MVT::i32),
620 DAG.getConstant(0, MVT::i32),
621 DAG.getConstant(1, MVT::i32),
622 DAG.getConstant(2, MVT::i32),
623 DAG.getConstant(3, MVT::i32),
627 DAG.getConstant(0, MVT::i32),
628 DAG.getConstant(1, MVT::i32),
629 DAG.getConstant(2, MVT::i32),
630 DAG.getConstant(3, MVT::i32),
638 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs, 19);
640 case AMDGPUIntrinsic::AMDGPU_dp4: {
642 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
643 DAG.getConstant(0, MVT::i32)),
644 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
645 DAG.getConstant(0, MVT::i32)),
646 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
647 DAG.getConstant(1, MVT::i32)),
648 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
649 DAG.getConstant(1, MVT::i32)),
650 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
651 DAG.getConstant(2, MVT::i32)),
652 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
653 DAG.getConstant(2, MVT::i32)),
654 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
655 DAG.getConstant(3, MVT::i32)),
656 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
657 DAG.getConstant(3, MVT::i32))
659 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args, 8);
662 case Intrinsic::r600_read_ngroups_x:
663 return LowerImplicitParameter(DAG, VT, DL, 0);
664 case Intrinsic::r600_read_ngroups_y:
665 return LowerImplicitParameter(DAG, VT, DL, 1);
666 case Intrinsic::r600_read_ngroups_z:
667 return LowerImplicitParameter(DAG, VT, DL, 2);
668 case Intrinsic::r600_read_global_size_x:
669 return LowerImplicitParameter(DAG, VT, DL, 3);
670 case Intrinsic::r600_read_global_size_y:
671 return LowerImplicitParameter(DAG, VT, DL, 4);
672 case Intrinsic::r600_read_global_size_z:
673 return LowerImplicitParameter(DAG, VT, DL, 5);
674 case Intrinsic::r600_read_local_size_x:
675 return LowerImplicitParameter(DAG, VT, DL, 6);
676 case Intrinsic::r600_read_local_size_y:
677 return LowerImplicitParameter(DAG, VT, DL, 7);
678 case Intrinsic::r600_read_local_size_z:
679 return LowerImplicitParameter(DAG, VT, DL, 8);
681 case Intrinsic::r600_read_tgid_x:
682 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
684 case Intrinsic::r600_read_tgid_y:
685 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
687 case Intrinsic::r600_read_tgid_z:
688 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
690 case Intrinsic::r600_read_tidig_x:
691 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
693 case Intrinsic::r600_read_tidig_y:
694 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
696 case Intrinsic::r600_read_tidig_z:
697 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
700 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
703 } // end switch(Op.getOpcode())
707 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
708 SmallVectorImpl<SDValue> &Results,
709 SelectionDAG &DAG) const {
710 switch (N->getOpcode()) {
712 case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
715 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
716 Results.push_back(SDValue(Node, 0));
717 Results.push_back(SDValue(Node, 1));
718 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
720 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
724 SDNode *Node = LowerSTORE(SDValue(N, 0), DAG).getNode();
725 Results.push_back(SDValue(Node, 0));
730 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
735 Op, DAG.getConstantFP(0.0f, MVT::f32),
736 DAG.getCondCode(ISD::SETNE)
740 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
742 unsigned DwordOffset) const {
743 unsigned ByteOffset = DwordOffset * 4;
744 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
745 AMDGPUAS::PARAM_I_ADDRESS);
747 // We shouldn't be using an offset wider than 16-bits for implicit parameters.
748 assert(isInt<16>(ByteOffset));
750 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
751 DAG.getConstant(ByteOffset, MVT::i32), // PTR
752 MachinePointerInfo(ConstantPointerNull::get(PtrType)),
753 false, false, false, 0);
756 SDValue R600TargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
758 MachineFunction &MF = DAG.getMachineFunction();
759 const AMDGPUFrameLowering *TFL =
760 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
762 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op);
765 unsigned FrameIndex = FIN->getIndex();
766 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
767 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), MVT::i32);
770 bool R600TargetLowering::isZero(SDValue Op) const {
771 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
772 return Cst->isNullValue();
773 } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
774 return CstFP->isZero();
780 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
782 EVT VT = Op.getValueType();
784 SDValue LHS = Op.getOperand(0);
785 SDValue RHS = Op.getOperand(1);
786 SDValue True = Op.getOperand(2);
787 SDValue False = Op.getOperand(3);
788 SDValue CC = Op.getOperand(4);
791 // LHS and RHS are guaranteed to be the same value type
792 EVT CompareVT = LHS.getValueType();
794 // Check if we can lower this to a native operation.
796 // Try to lower to a SET* instruction:
798 // SET* can match the following patterns:
800 // select_cc f32, f32, -1, 0, cc_any
801 // select_cc f32, f32, 1.0f, 0.0f, cc_any
802 // select_cc i32, i32, -1, 0, cc_any
805 // Move hardware True/False values to the correct operand.
806 if (isHWTrueValue(False) && isHWFalseValue(True)) {
807 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
808 std::swap(False, True);
809 CC = DAG.getCondCode(ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32));
812 if (isHWTrueValue(True) && isHWFalseValue(False) &&
813 (CompareVT == VT || VT == MVT::i32)) {
814 // This can be matched by a SET* instruction.
815 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
818 // Try to lower to a CND* instruction:
820 // CND* can match the following patterns:
822 // select_cc f32, 0.0, f32, f32, cc_any
823 // select_cc f32, 0.0, i32, i32, cc_any
824 // select_cc i32, 0, f32, f32, cc_any
825 // select_cc i32, 0, i32, i32, cc_any
827 if (isZero(LHS) || isZero(RHS)) {
828 SDValue Cond = (isZero(LHS) ? RHS : LHS);
829 SDValue Zero = (isZero(LHS) ? LHS : RHS);
830 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
831 if (CompareVT != VT) {
832 // Bitcast True / False to the correct types. This will end up being
833 // a nop, but it allows us to define only a single pattern in the
834 // .TD files for each CND* instruction rather than having to have
835 // one pattern for integer True/False and one for fp True/False
836 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
837 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
840 CCOpcode = ISD::getSetCCSwappedOperands(CCOpcode);
853 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
861 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
864 DAG.getCondCode(CCOpcode));
865 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
869 // Possible Min/Max pattern
870 SDValue MinMax = LowerMinMax(Op, DAG);
871 if (MinMax.getNode()) {
875 // If we make it this for it means we have no native instructions to handle
876 // this SELECT_CC, so we must lower it.
877 SDValue HWTrue, HWFalse;
879 if (CompareVT == MVT::f32) {
880 HWTrue = DAG.getConstantFP(1.0f, CompareVT);
881 HWFalse = DAG.getConstantFP(0.0f, CompareVT);
882 } else if (CompareVT == MVT::i32) {
883 HWTrue = DAG.getConstant(-1, CompareVT);
884 HWFalse = DAG.getConstant(0, CompareVT);
887 assert(!"Unhandled value type in LowerSELECT_CC");
890 // Lower this unsupported SELECT_CC into a combination of two supported
891 // SELECT_CC operations.
892 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
894 return DAG.getNode(ISD::SELECT_CC, DL, VT,
897 DAG.getCondCode(ISD::SETNE));
900 SDValue R600TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
901 return DAG.getNode(ISD::SELECT_CC,
905 DAG.getConstant(0, MVT::i32),
908 DAG.getCondCode(ISD::SETNE));
911 /// LLVM generates byte-addresed pointers. For indirect addressing, we need to
912 /// convert these pointers to a register index. Each register holds
913 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
914 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
915 /// for indirect addressing.
916 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
918 SelectionDAG &DAG) const {
930 default: llvm_unreachable("Invalid stack width");
933 return DAG.getNode(ISD::SRL, SDLoc(Ptr), Ptr.getValueType(), Ptr,
934 DAG.getConstant(SRLPad, MVT::i32));
937 void R600TargetLowering::getStackAddress(unsigned StackWidth,
940 unsigned &PtrIncr) const {
941 switch (StackWidth) {
952 Channel = ElemIdx % 2;
966 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
968 StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
969 SDValue Chain = Op.getOperand(0);
970 SDValue Value = Op.getOperand(1);
971 SDValue Ptr = Op.getOperand(2);
973 if (StoreNode->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
974 Ptr->getOpcode() != AMDGPUISD::DWORDADDR) {
975 // Convert pointer from byte address to dword address.
976 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(),
977 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
978 Ptr, DAG.getConstant(2, MVT::i32)));
980 if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
981 assert(!"Truncated and indexed stores not supported yet");
983 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
988 EVT ValueVT = Value.getValueType();
990 if (StoreNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
994 // Lowering for indirect addressing
996 const MachineFunction &MF = DAG.getMachineFunction();
997 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
998 getTargetMachine().getFrameLowering());
999 unsigned StackWidth = TFL->getStackWidth(MF);
1001 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1003 if (ValueVT.isVector()) {
1004 unsigned NumElemVT = ValueVT.getVectorNumElements();
1005 EVT ElemVT = ValueVT.getVectorElementType();
1008 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1009 "vector width in load");
1011 for (unsigned i = 0; i < NumElemVT; ++i) {
1012 unsigned Channel, PtrIncr;
1013 getStackAddress(StackWidth, i, Channel, PtrIncr);
1014 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1015 DAG.getConstant(PtrIncr, MVT::i32));
1016 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
1017 Value, DAG.getConstant(i, MVT::i32));
1019 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1021 DAG.getTargetConstant(Channel, MVT::i32));
1023 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores, NumElemVT);
1025 if (ValueVT == MVT::i8) {
1026 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
1028 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
1029 DAG.getTargetConstant(0, MVT::i32)); // Channel
1035 // return (512 + (kc_bank << 12)
1037 ConstantAddressBlock(unsigned AddressSpace) {
1038 switch (AddressSpace) {
1039 case AMDGPUAS::CONSTANT_BUFFER_0:
1041 case AMDGPUAS::CONSTANT_BUFFER_1:
1043 case AMDGPUAS::CONSTANT_BUFFER_2:
1044 return 512 + 4096 * 2;
1045 case AMDGPUAS::CONSTANT_BUFFER_3:
1046 return 512 + 4096 * 3;
1047 case AMDGPUAS::CONSTANT_BUFFER_4:
1048 return 512 + 4096 * 4;
1049 case AMDGPUAS::CONSTANT_BUFFER_5:
1050 return 512 + 4096 * 5;
1051 case AMDGPUAS::CONSTANT_BUFFER_6:
1052 return 512 + 4096 * 6;
1053 case AMDGPUAS::CONSTANT_BUFFER_7:
1054 return 512 + 4096 * 7;
1055 case AMDGPUAS::CONSTANT_BUFFER_8:
1056 return 512 + 4096 * 8;
1057 case AMDGPUAS::CONSTANT_BUFFER_9:
1058 return 512 + 4096 * 9;
1059 case AMDGPUAS::CONSTANT_BUFFER_10:
1060 return 512 + 4096 * 10;
1061 case AMDGPUAS::CONSTANT_BUFFER_11:
1062 return 512 + 4096 * 11;
1063 case AMDGPUAS::CONSTANT_BUFFER_12:
1064 return 512 + 4096 * 12;
1065 case AMDGPUAS::CONSTANT_BUFFER_13:
1066 return 512 + 4096 * 13;
1067 case AMDGPUAS::CONSTANT_BUFFER_14:
1068 return 512 + 4096 * 14;
1069 case AMDGPUAS::CONSTANT_BUFFER_15:
1070 return 512 + 4096 * 15;
1076 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
1078 EVT VT = Op.getValueType();
1080 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1081 SDValue Chain = Op.getOperand(0);
1082 SDValue Ptr = Op.getOperand(1);
1083 SDValue LoweredLoad;
1085 int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
1086 if (ConstantBlock > -1) {
1088 if (dyn_cast<ConstantExpr>(LoadNode->getSrcValue()) ||
1089 dyn_cast<Constant>(LoadNode->getSrcValue()) ||
1090 dyn_cast<ConstantSDNode>(Ptr)) {
1092 for (unsigned i = 0; i < 4; i++) {
1093 // We want Const position encoded with the following formula :
1094 // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
1095 // const_index is Ptr computed by llvm using an alignment of 16.
1096 // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
1097 // then div by 4 at the ISel step
1098 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1099 DAG.getConstant(4 * i + ConstantBlock * 16, MVT::i32));
1100 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1102 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Slots, 4);
1104 // non constant ptr cant be folded, keeps it as a v4f32 load
1105 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
1106 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
1107 DAG.getConstant(LoadNode->getAddressSpace() -
1108 AMDGPUAS::CONSTANT_BUFFER_0, MVT::i32)
1112 if (!VT.isVector()) {
1113 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1114 DAG.getConstant(0, MVT::i32));
1117 SDValue MergedValues[2] = {
1121 return DAG.getMergeValues(MergedValues, 2, DL);
1124 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1128 // Lowering for indirect addressing
1129 const MachineFunction &MF = DAG.getMachineFunction();
1130 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
1131 getTargetMachine().getFrameLowering());
1132 unsigned StackWidth = TFL->getStackWidth(MF);
1134 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1136 if (VT.isVector()) {
1137 unsigned NumElemVT = VT.getVectorNumElements();
1138 EVT ElemVT = VT.getVectorElementType();
1141 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1142 "vector width in load");
1144 for (unsigned i = 0; i < NumElemVT; ++i) {
1145 unsigned Channel, PtrIncr;
1146 getStackAddress(StackWidth, i, Channel, PtrIncr);
1147 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1148 DAG.getConstant(PtrIncr, MVT::i32));
1149 Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT,
1151 DAG.getTargetConstant(Channel, MVT::i32),
1154 for (unsigned i = NumElemVT; i < 4; ++i) {
1155 Loads[i] = DAG.getUNDEF(ElemVT);
1157 EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4);
1158 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads, 4);
1160 LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
1162 DAG.getTargetConstant(0, MVT::i32), // Channel
1167 Ops[0] = LoweredLoad;
1170 return DAG.getMergeValues(Ops, 2, DL);
1173 /// XXX Only kernel functions are supported, so we can assume for now that
1174 /// every function is a kernel function, but in the future we should use
1175 /// separate calling conventions for kernel and non-kernel functions.
1176 SDValue R600TargetLowering::LowerFormalArguments(
1178 CallingConv::ID CallConv,
1180 const SmallVectorImpl<ISD::InputArg> &Ins,
1181 SDLoc DL, SelectionDAG &DAG,
1182 SmallVectorImpl<SDValue> &InVals) const {
1183 unsigned ParamOffsetBytes = 36;
1184 Function::const_arg_iterator FuncArg =
1185 DAG.getMachineFunction().getFunction()->arg_begin();
1186 for (unsigned i = 0, e = Ins.size(); i < e; ++i, ++FuncArg) {
1188 Type *ArgType = FuncArg->getType();
1189 unsigned ArgSizeInBits = ArgType->isPointerTy() ?
1190 32 : ArgType->getPrimitiveSizeInBits();
1191 unsigned ArgBytes = ArgSizeInBits >> 3;
1193 if (ArgSizeInBits < VT.getSizeInBits()) {
1194 assert(!ArgType->isFloatTy() &&
1195 "Extending floating point arguments not supported yet");
1196 ArgVT = MVT::getIntegerVT(ArgSizeInBits);
1200 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1201 AMDGPUAS::PARAM_I_ADDRESS);
1202 SDValue Arg = DAG.getExtLoad(ISD::ZEXTLOAD, DL, VT, DAG.getRoot(),
1203 DAG.getConstant(ParamOffsetBytes, MVT::i32),
1204 MachinePointerInfo(UndefValue::get(PtrTy)),
1205 ArgVT, false, false, ArgBytes);
1206 InVals.push_back(Arg);
1207 ParamOffsetBytes += ArgBytes;
1212 EVT R600TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1213 if (!VT.isVector()) return MVT::i32;
1214 return VT.changeVectorElementTypeToInteger();
1218 CompactSwizzlableVector(SelectionDAG &DAG, SDValue VectorEntry,
1219 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1220 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1221 assert(RemapSwizzle.empty());
1222 SDValue NewBldVec[4] = {
1223 VectorEntry.getOperand(0),
1224 VectorEntry.getOperand(1),
1225 VectorEntry.getOperand(2),
1226 VectorEntry.getOperand(3)
1229 for (unsigned i = 0; i < 4; i++) {
1230 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(NewBldVec[i])) {
1232 RemapSwizzle[i] = 4; // SEL_0
1233 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1234 } else if (C->isExactlyValue(1.0)) {
1235 RemapSwizzle[i] = 5; // SEL_1
1236 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1240 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1242 for (unsigned j = 0; j < i; j++) {
1243 if (NewBldVec[i] == NewBldVec[j]) {
1244 NewBldVec[i] = DAG.getUNDEF(NewBldVec[i].getValueType());
1245 RemapSwizzle[i] = j;
1251 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1252 VectorEntry.getValueType(), NewBldVec, 4);
1255 static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
1256 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1257 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1258 assert(RemapSwizzle.empty());
1259 SDValue NewBldVec[4] = {
1260 VectorEntry.getOperand(0),
1261 VectorEntry.getOperand(1),
1262 VectorEntry.getOperand(2),
1263 VectorEntry.getOperand(3)
1265 bool isUnmovable[4] = { false, false, false, false };
1267 for (unsigned i = 0; i < 4; i++) {
1268 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1269 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1271 if (!isUnmovable[Idx]) {
1273 std::swap(NewBldVec[Idx], NewBldVec[i]);
1274 RemapSwizzle[Idx] = i;
1275 RemapSwizzle[i] = Idx;
1277 isUnmovable[Idx] = true;
1281 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1282 VectorEntry.getValueType(), NewBldVec, 4);
1286 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector,
1287 SDValue Swz[4], SelectionDAG &DAG) const {
1288 assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR);
1289 // Old -> New swizzle values
1290 DenseMap<unsigned, unsigned> SwizzleRemap;
1292 BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap);
1293 for (unsigned i = 0; i < 4; i++) {
1294 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1295 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1296 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1299 SwizzleRemap.clear();
1300 BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap);
1301 for (unsigned i = 0; i < 4; i++) {
1302 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1303 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1304 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1311 //===----------------------------------------------------------------------===//
1312 // Custom DAG Optimizations
1313 //===----------------------------------------------------------------------===//
1315 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1316 DAGCombinerInfo &DCI) const {
1317 SelectionDAG &DAG = DCI.DAG;
1319 switch (N->getOpcode()) {
1320 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1321 case ISD::FP_ROUND: {
1322 SDValue Arg = N->getOperand(0);
1323 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1324 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), N->getValueType(0),
1330 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1331 // (i32 select_cc f32, f32, -1, 0 cc)
1333 // Mesa's GLSL frontend generates the above pattern a lot and we can lower
1334 // this to one of the SET*_DX10 instructions.
1335 case ISD::FP_TO_SINT: {
1336 SDValue FNeg = N->getOperand(0);
1337 if (FNeg.getOpcode() != ISD::FNEG) {
1340 SDValue SelectCC = FNeg.getOperand(0);
1341 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1342 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1343 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1344 !isHWTrueValue(SelectCC.getOperand(2)) ||
1345 !isHWFalseValue(SelectCC.getOperand(3))) {
1349 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
1350 SelectCC.getOperand(0), // LHS
1351 SelectCC.getOperand(1), // RHS
1352 DAG.getConstant(-1, MVT::i32), // True
1353 DAG.getConstant(0, MVT::i32), // Flase
1354 SelectCC.getOperand(4)); // CC
1358 // Extract_vec (Build_vector) generated by custom lowering
1359 // also needs to be customly combined
1360 case ISD::EXTRACT_VECTOR_ELT: {
1361 SDValue Arg = N->getOperand(0);
1362 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1363 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1364 unsigned Element = Const->getZExtValue();
1365 return Arg->getOperand(Element);
1368 if (Arg.getOpcode() == ISD::BITCAST &&
1369 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1370 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1371 unsigned Element = Const->getZExtValue();
1372 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getVTList(),
1373 Arg->getOperand(0).getOperand(Element));
1378 case ISD::SELECT_CC: {
1379 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1380 // selectcc x, y, a, b, inv(cc)
1382 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
1383 // selectcc x, y, a, b, cc
1384 SDValue LHS = N->getOperand(0);
1385 if (LHS.getOpcode() != ISD::SELECT_CC) {
1389 SDValue RHS = N->getOperand(1);
1390 SDValue True = N->getOperand(2);
1391 SDValue False = N->getOperand(3);
1392 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1394 if (LHS.getOperand(2).getNode() != True.getNode() ||
1395 LHS.getOperand(3).getNode() != False.getNode() ||
1396 RHS.getNode() != False.getNode()) {
1401 default: return SDValue();
1402 case ISD::SETNE: return LHS;
1404 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
1405 LHSCC = ISD::getSetCCInverse(LHSCC,
1406 LHS.getOperand(0).getValueType().isInteger());
1407 return DAG.getSelectCC(SDLoc(N),
1416 case AMDGPUISD::EXPORT: {
1417 SDValue Arg = N->getOperand(1);
1418 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1421 SDValue NewArgs[8] = {
1422 N->getOperand(0), // Chain
1424 N->getOperand(2), // ArrayBase
1425 N->getOperand(3), // Type
1426 N->getOperand(4), // SWZ_X
1427 N->getOperand(5), // SWZ_Y
1428 N->getOperand(6), // SWZ_Z
1429 N->getOperand(7) // SWZ_W
1432 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG);
1433 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs, 8);
1435 case AMDGPUISD::TEXTURE_FETCH: {
1436 SDValue Arg = N->getOperand(1);
1437 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1440 SDValue NewArgs[19] = {
1461 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG);
1462 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, SDLoc(N), N->getVTList(),