1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for R600
13 //===----------------------------------------------------------------------===//
15 #include "R600ISelLowering.h"
16 #include "R600Defines.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineFunctionInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/IR/Argument.h"
25 #include "llvm/IR/Function.h"
29 R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
30 AMDGPUTargetLowering(TM),
31 Gen(TM.getSubtarget<AMDGPUSubtarget>().getGeneration()) {
32 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
34 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
35 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
36 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
37 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
39 computeRegisterProperties();
41 // Set condition code actions
42 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
43 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
44 setCondCodeAction(ISD::SETLT, MVT::f32, Expand);
45 setCondCodeAction(ISD::SETLE, MVT::f32, Expand);
46 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
47 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
48 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
49 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
50 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
51 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
52 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
53 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
55 setCondCodeAction(ISD::SETLE, MVT::i32, Expand);
56 setCondCodeAction(ISD::SETLT, MVT::i32, Expand);
57 setCondCodeAction(ISD::SETULE, MVT::i32, Expand);
58 setCondCodeAction(ISD::SETULT, MVT::i32, Expand);
60 setOperationAction(ISD::FCOS, MVT::f32, Custom);
61 setOperationAction(ISD::FSIN, MVT::f32, Custom);
63 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
64 setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
66 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
67 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
69 setOperationAction(ISD::FSUB, MVT::f32, Expand);
71 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
72 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
73 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
75 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
76 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
78 setOperationAction(ISD::SETCC, MVT::i32, Expand);
79 setOperationAction(ISD::SETCC, MVT::f32, Expand);
80 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
82 setOperationAction(ISD::SELECT, MVT::i32, Expand);
83 setOperationAction(ISD::SELECT, MVT::f32, Expand);
84 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
85 setOperationAction(ISD::SELECT, MVT::v2f32, Expand);
86 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
87 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
89 // Legalize loads and stores to the private address space.
90 setOperationAction(ISD::LOAD, MVT::i32, Custom);
91 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
92 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
93 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
94 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
95 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
96 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
97 setOperationAction(ISD::STORE, MVT::i8, Custom);
98 setOperationAction(ISD::STORE, MVT::i32, Custom);
99 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
100 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
101 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
102 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
104 setOperationAction(ISD::LOAD, MVT::i32, Custom);
105 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
106 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
108 setTargetDAGCombine(ISD::FP_ROUND);
109 setTargetDAGCombine(ISD::FP_TO_SINT);
110 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
111 setTargetDAGCombine(ISD::SELECT_CC);
112 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
114 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
116 setBooleanContents(ZeroOrNegativeOneBooleanContent);
117 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
118 setSchedulingPreference(Sched::Source);
121 MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
122 MachineInstr * MI, MachineBasicBlock * BB) const {
123 MachineFunction * MF = BB->getParent();
124 MachineRegisterInfo &MRI = MF->getRegInfo();
125 MachineBasicBlock::iterator I = *MI;
126 const R600InstrInfo *TII =
127 static_cast<const R600InstrInfo*>(MF->getTarget().getInstrInfo());
129 switch (MI->getOpcode()) {
131 if (TII->isLDSInstr(MI->getOpcode()) &&
132 TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst) != -1) {
133 int DstIdx = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
134 assert(DstIdx != -1);
135 MachineInstrBuilder NewMI;
136 if (!MRI.use_empty(MI->getOperand(DstIdx).getReg())) {
137 NewMI = BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()),
139 TII->buildDefaultInstruction(*BB, I, AMDGPU::MOV,
140 MI->getOperand(0).getReg(),
143 NewMI = BuildMI(*BB, I, BB->findDebugLoc(I),
144 TII->get(AMDGPU::getLDSNoRetOp(MI->getOpcode())));
146 for (unsigned i = 1, e = MI->getNumOperands(); i < e; ++i) {
147 NewMI.addOperand(MI->getOperand(i));
150 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
153 case AMDGPU::CLAMP_R600: {
154 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
156 MI->getOperand(0).getReg(),
157 MI->getOperand(1).getReg());
158 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
162 case AMDGPU::FABS_R600: {
163 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
165 MI->getOperand(0).getReg(),
166 MI->getOperand(1).getReg());
167 TII->addFlag(NewMI, 0, MO_FLAG_ABS);
171 case AMDGPU::FNEG_R600: {
172 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
174 MI->getOperand(0).getReg(),
175 MI->getOperand(1).getReg());
176 TII->addFlag(NewMI, 0, MO_FLAG_NEG);
180 case AMDGPU::MASK_WRITE: {
181 unsigned maskedRegister = MI->getOperand(0).getReg();
182 assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
183 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
184 TII->addFlag(defInstr, 0, MO_FLAG_MASK);
188 case AMDGPU::MOV_IMM_F32:
189 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
190 MI->getOperand(1).getFPImm()->getValueAPF()
191 .bitcastToAPInt().getZExtValue());
193 case AMDGPU::MOV_IMM_I32:
194 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
195 MI->getOperand(1).getImm());
197 case AMDGPU::CONST_COPY: {
198 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
199 MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
200 TII->setImmOperand(NewMI, AMDGPU::OpName::src0_sel,
201 MI->getOperand(1).getImm());
205 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
206 case AMDGPU::RAT_WRITE_CACHELESS_64_eg:
207 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
208 unsigned EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
210 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
211 .addOperand(MI->getOperand(0))
212 .addOperand(MI->getOperand(1))
213 .addImm(EOP); // Set End of program bit
218 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
219 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
220 MachineOperand &RID = MI->getOperand(4);
221 MachineOperand &SID = MI->getOperand(5);
222 unsigned TextureId = MI->getOperand(6).getImm();
223 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
224 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
236 case 8: // ShadowRect
247 case 11: // Shadow1DArray
251 case 12: // Shadow2DArray
255 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
256 .addOperand(MI->getOperand(3))
274 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
275 .addOperand(MI->getOperand(2))
293 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
294 .addOperand(MI->getOperand(0))
295 .addOperand(MI->getOperand(1))
313 .addReg(T0, RegState::Implicit)
314 .addReg(T1, RegState::Implicit);
318 case AMDGPU::TXD_SHADOW: {
319 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
320 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
321 MachineOperand &RID = MI->getOperand(4);
322 MachineOperand &SID = MI->getOperand(5);
323 unsigned TextureId = MI->getOperand(6).getImm();
324 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
325 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
337 case 8: // ShadowRect
348 case 11: // Shadow1DArray
352 case 12: // Shadow2DArray
357 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
358 .addOperand(MI->getOperand(3))
376 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
377 .addOperand(MI->getOperand(2))
395 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
396 .addOperand(MI->getOperand(0))
397 .addOperand(MI->getOperand(1))
415 .addReg(T0, RegState::Implicit)
416 .addReg(T1, RegState::Implicit);
421 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
422 .addOperand(MI->getOperand(0));
425 case AMDGPU::BRANCH_COND_f32: {
426 MachineInstr *NewMI =
427 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
428 AMDGPU::PREDICATE_BIT)
429 .addOperand(MI->getOperand(1))
430 .addImm(OPCODE_IS_NOT_ZERO)
432 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
433 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
434 .addOperand(MI->getOperand(0))
435 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
439 case AMDGPU::BRANCH_COND_i32: {
440 MachineInstr *NewMI =
441 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
442 AMDGPU::PREDICATE_BIT)
443 .addOperand(MI->getOperand(1))
444 .addImm(OPCODE_IS_NOT_ZERO_INT)
446 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
447 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
448 .addOperand(MI->getOperand(0))
449 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
453 case AMDGPU::EG_ExportSwz:
454 case AMDGPU::R600_ExportSwz: {
455 // Instruction is left unmodified if its not the last one of its type
456 bool isLastInstructionOfItsType = true;
457 unsigned InstExportType = MI->getOperand(1).getImm();
458 for (MachineBasicBlock::iterator NextExportInst = llvm::next(I),
459 EndBlock = BB->end(); NextExportInst != EndBlock;
460 NextExportInst = llvm::next(NextExportInst)) {
461 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
462 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
463 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
465 if (CurrentInstExportType == InstExportType) {
466 isLastInstructionOfItsType = false;
471 bool EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN)? 1 : 0;
472 if (!EOP && !isLastInstructionOfItsType)
474 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
475 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
476 .addOperand(MI->getOperand(0))
477 .addOperand(MI->getOperand(1))
478 .addOperand(MI->getOperand(2))
479 .addOperand(MI->getOperand(3))
480 .addOperand(MI->getOperand(4))
481 .addOperand(MI->getOperand(5))
482 .addOperand(MI->getOperand(6))
487 case AMDGPU::RETURN: {
488 // RETURN instructions must have the live-out registers as implicit uses,
489 // otherwise they appear dead.
490 R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
491 MachineInstrBuilder MIB(*MF, MI);
492 for (unsigned i = 0, e = MFI->LiveOuts.size(); i != e; ++i)
493 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
498 MI->eraseFromParent();
502 //===----------------------------------------------------------------------===//
503 // Custom DAG Lowering Operations
504 //===----------------------------------------------------------------------===//
506 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
507 MachineFunction &MF = DAG.getMachineFunction();
508 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
509 switch (Op.getOpcode()) {
510 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
512 case ISD::FSIN: return LowerTrig(Op, DAG);
513 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
514 case ISD::STORE: return LowerSTORE(Op, DAG);
515 case ISD::LOAD: return LowerLOAD(Op, DAG);
516 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
517 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
518 case ISD::INTRINSIC_VOID: {
519 SDValue Chain = Op.getOperand(0);
520 unsigned IntrinsicID =
521 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
522 switch (IntrinsicID) {
523 case AMDGPUIntrinsic::AMDGPU_store_output: {
524 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
525 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
526 MFI->LiveOuts.push_back(Reg);
527 return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2));
529 case AMDGPUIntrinsic::R600_store_swizzle: {
530 const SDValue Args[8] = {
532 Op.getOperand(2), // Export Value
533 Op.getOperand(3), // ArrayBase
534 Op.getOperand(4), // Type
535 DAG.getConstant(0, MVT::i32), // SWZ_X
536 DAG.getConstant(1, MVT::i32), // SWZ_Y
537 DAG.getConstant(2, MVT::i32), // SWZ_Z
538 DAG.getConstant(3, MVT::i32) // SWZ_W
540 return DAG.getNode(AMDGPUISD::EXPORT, SDLoc(Op), Op.getValueType(),
544 // default for switch(IntrinsicID)
547 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
550 case ISD::INTRINSIC_WO_CHAIN: {
551 unsigned IntrinsicID =
552 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
553 EVT VT = Op.getValueType();
555 switch(IntrinsicID) {
556 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
557 case AMDGPUIntrinsic::R600_load_input: {
558 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
559 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
560 MachineFunction &MF = DAG.getMachineFunction();
561 MachineRegisterInfo &MRI = MF.getRegInfo();
563 return DAG.getCopyFromReg(DAG.getEntryNode(),
564 SDLoc(DAG.getEntryNode()), Reg, VT);
567 case AMDGPUIntrinsic::R600_interp_input: {
568 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
569 int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
570 MachineSDNode *interp;
572 const MachineFunction &MF = DAG.getMachineFunction();
573 const R600InstrInfo *TII =
574 static_cast<const R600InstrInfo*>(MF.getTarget().getInstrInfo());
575 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
576 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
577 return DAG.getTargetExtractSubreg(
578 TII->getRegisterInfo().getSubRegFromChannel(slot % 4),
579 DL, MVT::f32, SDValue(interp, 0));
582 MachineFunction &MF = DAG.getMachineFunction();
583 MachineRegisterInfo &MRI = MF.getRegInfo();
584 unsigned RegisterI = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb);
585 unsigned RegisterJ = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1);
586 MRI.addLiveIn(RegisterI);
587 MRI.addLiveIn(RegisterJ);
588 SDValue RegisterINode = DAG.getCopyFromReg(DAG.getEntryNode(),
589 SDLoc(DAG.getEntryNode()), RegisterI, MVT::f32);
590 SDValue RegisterJNode = DAG.getCopyFromReg(DAG.getEntryNode(),
591 SDLoc(DAG.getEntryNode()), RegisterJ, MVT::f32);
594 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
595 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
596 RegisterJNode, RegisterINode);
598 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
599 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
600 RegisterJNode, RegisterINode);
601 return SDValue(interp, slot % 2);
603 case AMDGPUIntrinsic::R600_tex:
604 case AMDGPUIntrinsic::R600_texc:
605 case AMDGPUIntrinsic::R600_txl:
606 case AMDGPUIntrinsic::R600_txlc:
607 case AMDGPUIntrinsic::R600_txb:
608 case AMDGPUIntrinsic::R600_txbc:
609 case AMDGPUIntrinsic::R600_txf:
610 case AMDGPUIntrinsic::R600_txq:
611 case AMDGPUIntrinsic::R600_ddx:
612 case AMDGPUIntrinsic::R600_ddy:
613 case AMDGPUIntrinsic::R600_ldptr: {
615 switch (IntrinsicID) {
616 case AMDGPUIntrinsic::R600_tex:
619 case AMDGPUIntrinsic::R600_texc:
622 case AMDGPUIntrinsic::R600_txl:
625 case AMDGPUIntrinsic::R600_txlc:
628 case AMDGPUIntrinsic::R600_txb:
631 case AMDGPUIntrinsic::R600_txbc:
634 case AMDGPUIntrinsic::R600_txf:
637 case AMDGPUIntrinsic::R600_txq:
640 case AMDGPUIntrinsic::R600_ddx:
643 case AMDGPUIntrinsic::R600_ddy:
646 case AMDGPUIntrinsic::R600_ldptr:
650 llvm_unreachable("Unknow Texture Operation");
653 SDValue TexArgs[19] = {
654 DAG.getConstant(TextureOp, MVT::i32),
656 DAG.getConstant(0, MVT::i32),
657 DAG.getConstant(1, MVT::i32),
658 DAG.getConstant(2, MVT::i32),
659 DAG.getConstant(3, MVT::i32),
663 DAG.getConstant(0, MVT::i32),
664 DAG.getConstant(1, MVT::i32),
665 DAG.getConstant(2, MVT::i32),
666 DAG.getConstant(3, MVT::i32),
674 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs, 19);
676 case AMDGPUIntrinsic::AMDGPU_dp4: {
678 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
679 DAG.getConstant(0, MVT::i32)),
680 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
681 DAG.getConstant(0, MVT::i32)),
682 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
683 DAG.getConstant(1, MVT::i32)),
684 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
685 DAG.getConstant(1, MVT::i32)),
686 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
687 DAG.getConstant(2, MVT::i32)),
688 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
689 DAG.getConstant(2, MVT::i32)),
690 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
691 DAG.getConstant(3, MVT::i32)),
692 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
693 DAG.getConstant(3, MVT::i32))
695 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args, 8);
698 case Intrinsic::r600_read_ngroups_x:
699 return LowerImplicitParameter(DAG, VT, DL, 0);
700 case Intrinsic::r600_read_ngroups_y:
701 return LowerImplicitParameter(DAG, VT, DL, 1);
702 case Intrinsic::r600_read_ngroups_z:
703 return LowerImplicitParameter(DAG, VT, DL, 2);
704 case Intrinsic::r600_read_global_size_x:
705 return LowerImplicitParameter(DAG, VT, DL, 3);
706 case Intrinsic::r600_read_global_size_y:
707 return LowerImplicitParameter(DAG, VT, DL, 4);
708 case Intrinsic::r600_read_global_size_z:
709 return LowerImplicitParameter(DAG, VT, DL, 5);
710 case Intrinsic::r600_read_local_size_x:
711 return LowerImplicitParameter(DAG, VT, DL, 6);
712 case Intrinsic::r600_read_local_size_y:
713 return LowerImplicitParameter(DAG, VT, DL, 7);
714 case Intrinsic::r600_read_local_size_z:
715 return LowerImplicitParameter(DAG, VT, DL, 8);
717 case Intrinsic::r600_read_tgid_x:
718 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
720 case Intrinsic::r600_read_tgid_y:
721 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
723 case Intrinsic::r600_read_tgid_z:
724 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
726 case Intrinsic::r600_read_tidig_x:
727 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
729 case Intrinsic::r600_read_tidig_y:
730 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
732 case Intrinsic::r600_read_tidig_z:
733 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
736 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
739 } // end switch(Op.getOpcode())
743 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
744 SmallVectorImpl<SDValue> &Results,
745 SelectionDAG &DAG) const {
746 switch (N->getOpcode()) {
748 case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
751 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
752 Results.push_back(SDValue(Node, 0));
753 Results.push_back(SDValue(Node, 1));
754 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
756 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
760 SDNode *Node = LowerSTORE(SDValue(N, 0), DAG).getNode();
761 Results.push_back(SDValue(Node, 0));
766 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
767 // On hw >= R700, COS/SIN input must be between -1. and 1.
768 // Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5)
769 EVT VT = Op.getValueType();
770 SDValue Arg = Op.getOperand(0);
771 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
772 DAG.getNode(ISD::FADD, SDLoc(Op), VT,
773 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
774 DAG.getConstantFP(0.15915494309, MVT::f32)),
775 DAG.getConstantFP(0.5, MVT::f32)));
777 switch (Op.getOpcode()) {
779 TrigNode = AMDGPUISD::COS_HW;
782 TrigNode = AMDGPUISD::SIN_HW;
785 llvm_unreachable("Wrong trig opcode");
787 SDValue TrigVal = DAG.getNode(TrigNode, SDLoc(Op), VT,
788 DAG.getNode(ISD::FADD, SDLoc(Op), VT, FractPart,
789 DAG.getConstantFP(-0.5, MVT::f32)));
790 if (Gen >= AMDGPUSubtarget::R700)
792 // On R600 hw, COS/SIN input must be between -Pi and Pi.
793 return DAG.getNode(ISD::FMUL, SDLoc(Op), VT, TrigVal,
794 DAG.getConstantFP(3.14159265359, MVT::f32));
797 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
802 Op, DAG.getConstantFP(0.0f, MVT::f32),
803 DAG.getCondCode(ISD::SETNE)
807 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
809 unsigned DwordOffset) const {
810 unsigned ByteOffset = DwordOffset * 4;
811 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
812 AMDGPUAS::CONSTANT_BUFFER_0);
814 // We shouldn't be using an offset wider than 16-bits for implicit parameters.
815 assert(isInt<16>(ByteOffset));
817 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
818 DAG.getConstant(ByteOffset, MVT::i32), // PTR
819 MachinePointerInfo(ConstantPointerNull::get(PtrType)),
820 false, false, false, 0);
823 SDValue R600TargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
825 MachineFunction &MF = DAG.getMachineFunction();
826 const AMDGPUFrameLowering *TFL =
827 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
829 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op);
832 unsigned FrameIndex = FIN->getIndex();
833 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
834 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), MVT::i32);
837 bool R600TargetLowering::isZero(SDValue Op) const {
838 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
839 return Cst->isNullValue();
840 } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
841 return CstFP->isZero();
847 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
849 EVT VT = Op.getValueType();
851 SDValue LHS = Op.getOperand(0);
852 SDValue RHS = Op.getOperand(1);
853 SDValue True = Op.getOperand(2);
854 SDValue False = Op.getOperand(3);
855 SDValue CC = Op.getOperand(4);
858 // LHS and RHS are guaranteed to be the same value type
859 EVT CompareVT = LHS.getValueType();
861 // Check if we can lower this to a native operation.
863 // Try to lower to a SET* instruction:
865 // SET* can match the following patterns:
867 // select_cc f32, f32, -1, 0, cc_supported
868 // select_cc f32, f32, 1.0f, 0.0f, cc_supported
869 // select_cc i32, i32, -1, 0, cc_supported
872 // Move hardware True/False values to the correct operand.
873 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
874 ISD::CondCode InverseCC =
875 ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
876 if (isHWTrueValue(False) && isHWFalseValue(True)) {
877 if (isCondCodeLegal(InverseCC, CompareVT.getSimpleVT())) {
878 std::swap(False, True);
879 CC = DAG.getCondCode(InverseCC);
881 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InverseCC);
882 if (isCondCodeLegal(SwapInvCC, CompareVT.getSimpleVT())) {
883 std::swap(False, True);
885 CC = DAG.getCondCode(SwapInvCC);
890 if (isHWTrueValue(True) && isHWFalseValue(False) &&
891 (CompareVT == VT || VT == MVT::i32)) {
892 // This can be matched by a SET* instruction.
893 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
896 // Try to lower to a CND* instruction:
898 // CND* can match the following patterns:
900 // select_cc f32, 0.0, f32, f32, cc_supported
901 // select_cc f32, 0.0, i32, i32, cc_supported
902 // select_cc i32, 0, f32, f32, cc_supported
903 // select_cc i32, 0, i32, i32, cc_supported
906 // Try to move the zero value to the RHS
908 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
909 // Try swapping the operands
910 ISD::CondCode CCSwapped = ISD::getSetCCSwappedOperands(CCOpcode);
911 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
913 CC = DAG.getCondCode(CCSwapped);
915 // Try inverting the conditon and then swapping the operands
916 ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT.isInteger());
917 CCSwapped = ISD::getSetCCSwappedOperands(CCInv);
918 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
919 std::swap(True, False);
921 CC = DAG.getCondCode(CCSwapped);
928 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
929 if (CompareVT != VT) {
930 // Bitcast True / False to the correct types. This will end up being
931 // a nop, but it allows us to define only a single pattern in the
932 // .TD files for each CND* instruction rather than having to have
933 // one pattern for integer True/False and one for fp True/False
934 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
935 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
942 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
950 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
953 DAG.getCondCode(CCOpcode));
954 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
958 // Possible Min/Max pattern
959 SDValue MinMax = LowerMinMax(Op, DAG);
960 if (MinMax.getNode()) {
964 // If we make it this for it means we have no native instructions to handle
965 // this SELECT_CC, so we must lower it.
966 SDValue HWTrue, HWFalse;
968 if (CompareVT == MVT::f32) {
969 HWTrue = DAG.getConstantFP(1.0f, CompareVT);
970 HWFalse = DAG.getConstantFP(0.0f, CompareVT);
971 } else if (CompareVT == MVT::i32) {
972 HWTrue = DAG.getConstant(-1, CompareVT);
973 HWFalse = DAG.getConstant(0, CompareVT);
976 assert(!"Unhandled value type in LowerSELECT_CC");
979 // Lower this unsupported SELECT_CC into a combination of two supported
980 // SELECT_CC operations.
981 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
983 return DAG.getNode(ISD::SELECT_CC, DL, VT,
986 DAG.getCondCode(ISD::SETNE));
989 /// LLVM generates byte-addresed pointers. For indirect addressing, we need to
990 /// convert these pointers to a register index. Each register holds
991 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
992 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
993 /// for indirect addressing.
994 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
996 SelectionDAG &DAG) const {
1008 default: llvm_unreachable("Invalid stack width");
1011 return DAG.getNode(ISD::SRL, SDLoc(Ptr), Ptr.getValueType(), Ptr,
1012 DAG.getConstant(SRLPad, MVT::i32));
1015 void R600TargetLowering::getStackAddress(unsigned StackWidth,
1018 unsigned &PtrIncr) const {
1019 switch (StackWidth) {
1030 Channel = ElemIdx % 2;
1044 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1046 StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
1047 SDValue Chain = Op.getOperand(0);
1048 SDValue Value = Op.getOperand(1);
1049 SDValue Ptr = Op.getOperand(2);
1051 SDValue Result = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1052 if (Result.getNode()) {
1056 if (StoreNode->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS) {
1057 if (StoreNode->isTruncatingStore()) {
1058 EVT VT = Value.getValueType();
1059 assert(VT.bitsLE(MVT::i32));
1060 EVT MemVT = StoreNode->getMemoryVT();
1061 SDValue MaskConstant;
1062 if (MemVT == MVT::i8) {
1063 MaskConstant = DAG.getConstant(0xFF, MVT::i32);
1065 assert(MemVT == MVT::i16);
1066 MaskConstant = DAG.getConstant(0xFFFF, MVT::i32);
1068 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, VT, Ptr,
1069 DAG.getConstant(2, MVT::i32));
1070 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, Ptr.getValueType(), Ptr,
1071 DAG.getConstant(0x00000003, VT));
1072 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant);
1073 SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex,
1074 DAG.getConstant(3, VT));
1075 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, Shift);
1076 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, Shift);
1077 // XXX: If we add a 64-bit ZW register class, then we could use a 2 x i32
1081 DAG.getConstant(0, MVT::i32),
1082 DAG.getConstant(0, MVT::i32),
1085 SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src, 4);
1086 SDValue Args[3] = { Chain, Input, DWordAddr };
1087 return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL,
1088 Op->getVTList(), Args, 3, MemVT,
1089 StoreNode->getMemOperand());
1090 } else if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR &&
1091 Value.getValueType().bitsGE(MVT::i32)) {
1092 // Convert pointer from byte address to dword address.
1093 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(),
1094 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
1095 Ptr, DAG.getConstant(2, MVT::i32)));
1097 if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
1098 assert(!"Truncated and indexed stores not supported yet");
1100 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
1106 EVT ValueVT = Value.getValueType();
1108 if (StoreNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1112 // Lowering for indirect addressing
1114 const MachineFunction &MF = DAG.getMachineFunction();
1115 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
1116 getTargetMachine().getFrameLowering());
1117 unsigned StackWidth = TFL->getStackWidth(MF);
1119 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1121 if (ValueVT.isVector()) {
1122 unsigned NumElemVT = ValueVT.getVectorNumElements();
1123 EVT ElemVT = ValueVT.getVectorElementType();
1126 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1127 "vector width in load");
1129 for (unsigned i = 0; i < NumElemVT; ++i) {
1130 unsigned Channel, PtrIncr;
1131 getStackAddress(StackWidth, i, Channel, PtrIncr);
1132 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1133 DAG.getConstant(PtrIncr, MVT::i32));
1134 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
1135 Value, DAG.getConstant(i, MVT::i32));
1137 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1139 DAG.getTargetConstant(Channel, MVT::i32));
1141 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores, NumElemVT);
1143 if (ValueVT == MVT::i8) {
1144 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
1146 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
1147 DAG.getTargetConstant(0, MVT::i32)); // Channel
1153 // return (512 + (kc_bank << 12)
1155 ConstantAddressBlock(unsigned AddressSpace) {
1156 switch (AddressSpace) {
1157 case AMDGPUAS::CONSTANT_BUFFER_0:
1159 case AMDGPUAS::CONSTANT_BUFFER_1:
1161 case AMDGPUAS::CONSTANT_BUFFER_2:
1162 return 512 + 4096 * 2;
1163 case AMDGPUAS::CONSTANT_BUFFER_3:
1164 return 512 + 4096 * 3;
1165 case AMDGPUAS::CONSTANT_BUFFER_4:
1166 return 512 + 4096 * 4;
1167 case AMDGPUAS::CONSTANT_BUFFER_5:
1168 return 512 + 4096 * 5;
1169 case AMDGPUAS::CONSTANT_BUFFER_6:
1170 return 512 + 4096 * 6;
1171 case AMDGPUAS::CONSTANT_BUFFER_7:
1172 return 512 + 4096 * 7;
1173 case AMDGPUAS::CONSTANT_BUFFER_8:
1174 return 512 + 4096 * 8;
1175 case AMDGPUAS::CONSTANT_BUFFER_9:
1176 return 512 + 4096 * 9;
1177 case AMDGPUAS::CONSTANT_BUFFER_10:
1178 return 512 + 4096 * 10;
1179 case AMDGPUAS::CONSTANT_BUFFER_11:
1180 return 512 + 4096 * 11;
1181 case AMDGPUAS::CONSTANT_BUFFER_12:
1182 return 512 + 4096 * 12;
1183 case AMDGPUAS::CONSTANT_BUFFER_13:
1184 return 512 + 4096 * 13;
1185 case AMDGPUAS::CONSTANT_BUFFER_14:
1186 return 512 + 4096 * 14;
1187 case AMDGPUAS::CONSTANT_BUFFER_15:
1188 return 512 + 4096 * 15;
1194 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
1196 EVT VT = Op.getValueType();
1198 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1199 SDValue Chain = Op.getOperand(0);
1200 SDValue Ptr = Op.getOperand(1);
1201 SDValue LoweredLoad;
1203 if (LoadNode->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS && VT.isVector()) {
1204 SDValue MergedValues[2] = {
1205 SplitVectorLoad(Op, DAG),
1208 return DAG.getMergeValues(MergedValues, 2, DL);
1211 int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
1212 if (ConstantBlock > -1) {
1214 if (dyn_cast<ConstantExpr>(LoadNode->getSrcValue()) ||
1215 dyn_cast<Constant>(LoadNode->getSrcValue()) ||
1216 dyn_cast<ConstantSDNode>(Ptr)) {
1218 for (unsigned i = 0; i < 4; i++) {
1219 // We want Const position encoded with the following formula :
1220 // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
1221 // const_index is Ptr computed by llvm using an alignment of 16.
1222 // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
1223 // then div by 4 at the ISel step
1224 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1225 DAG.getConstant(4 * i + ConstantBlock * 16, MVT::i32));
1226 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1228 EVT NewVT = MVT::v4i32;
1229 unsigned NumElements = 4;
1230 if (VT.isVector()) {
1232 NumElements = VT.getVectorNumElements();
1234 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT, Slots, NumElements);
1236 // non constant ptr cant be folded, keeps it as a v4f32 load
1237 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
1238 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
1239 DAG.getConstant(LoadNode->getAddressSpace() -
1240 AMDGPUAS::CONSTANT_BUFFER_0, MVT::i32)
1244 if (!VT.isVector()) {
1245 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1246 DAG.getConstant(0, MVT::i32));
1249 SDValue MergedValues[2] = {
1253 return DAG.getMergeValues(MergedValues, 2, DL);
1256 // For most operations returning SDValue() will result int he node being
1257 // expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so
1258 // we need to manually expand loads that may be legal in some address spaces
1259 // and illegal in others. SEXT loads from CONSTANT_BUFFER_0 are supported
1260 // for compute shaders, since the data is sign extended when it is uploaded
1261 // to the buffer. Howerver SEXT loads from other addresspaces are not
1262 // supported, so we need to expand them here.
1263 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
1264 EVT MemVT = LoadNode->getMemoryVT();
1265 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
1266 SDValue ShiftAmount =
1267 DAG.getConstant(VT.getSizeInBits() - MemVT.getSizeInBits(), MVT::i32);
1268 SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr,
1269 LoadNode->getPointerInfo(), MemVT,
1270 LoadNode->isVolatile(),
1271 LoadNode->isNonTemporal(),
1272 LoadNode->getAlignment());
1273 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, NewLoad, ShiftAmount);
1274 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Shl, ShiftAmount);
1276 SDValue MergedValues[2] = { Sra, Chain };
1277 return DAG.getMergeValues(MergedValues, 2, DL);
1280 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1284 // Lowering for indirect addressing
1285 const MachineFunction &MF = DAG.getMachineFunction();
1286 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
1287 getTargetMachine().getFrameLowering());
1288 unsigned StackWidth = TFL->getStackWidth(MF);
1290 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1292 if (VT.isVector()) {
1293 unsigned NumElemVT = VT.getVectorNumElements();
1294 EVT ElemVT = VT.getVectorElementType();
1297 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1298 "vector width in load");
1300 for (unsigned i = 0; i < NumElemVT; ++i) {
1301 unsigned Channel, PtrIncr;
1302 getStackAddress(StackWidth, i, Channel, PtrIncr);
1303 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1304 DAG.getConstant(PtrIncr, MVT::i32));
1305 Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT,
1307 DAG.getTargetConstant(Channel, MVT::i32),
1310 for (unsigned i = NumElemVT; i < 4; ++i) {
1311 Loads[i] = DAG.getUNDEF(ElemVT);
1313 EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4);
1314 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads, 4);
1316 LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
1318 DAG.getTargetConstant(0, MVT::i32), // Channel
1323 Ops[0] = LoweredLoad;
1326 return DAG.getMergeValues(Ops, 2, DL);
1329 /// XXX Only kernel functions are supported, so we can assume for now that
1330 /// every function is a kernel function, but in the future we should use
1331 /// separate calling conventions for kernel and non-kernel functions.
1332 SDValue R600TargetLowering::LowerFormalArguments(
1334 CallingConv::ID CallConv,
1336 const SmallVectorImpl<ISD::InputArg> &Ins,
1337 SDLoc DL, SelectionDAG &DAG,
1338 SmallVectorImpl<SDValue> &InVals) const {
1339 SmallVector<CCValAssign, 16> ArgLocs;
1340 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1341 getTargetMachine(), ArgLocs, *DAG.getContext());
1343 AnalyzeFormalArguments(CCInfo, Ins);
1345 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1346 CCValAssign &VA = ArgLocs[i];
1347 EVT VT = VA.getLocVT();
1349 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1350 AMDGPUAS::CONSTANT_BUFFER_0);
1352 // The first 36 bytes of the input buffer contains information about
1353 // thread group and global sizes.
1354 SDValue Arg = DAG.getLoad(VT, DL, Chain,
1355 DAG.getConstant(36 + VA.getLocMemOffset(), MVT::i32),
1356 MachinePointerInfo(UndefValue::get(PtrTy)), false,
1357 false, false, 4); // 4 is the prefered alignment for
1358 // the CONSTANT memory space.
1359 InVals.push_back(Arg);
1364 EVT R600TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1365 if (!VT.isVector()) return MVT::i32;
1366 return VT.changeVectorElementTypeToInteger();
1370 CompactSwizzlableVector(SelectionDAG &DAG, SDValue VectorEntry,
1371 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1372 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1373 assert(RemapSwizzle.empty());
1374 SDValue NewBldVec[4] = {
1375 VectorEntry.getOperand(0),
1376 VectorEntry.getOperand(1),
1377 VectorEntry.getOperand(2),
1378 VectorEntry.getOperand(3)
1381 for (unsigned i = 0; i < 4; i++) {
1382 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1383 // We mask write here to teach later passes that the ith element of this
1384 // vector is undef. Thus we can use it to reduce 128 bits reg usage,
1385 // break false dependencies and additionnaly make assembly easier to read.
1386 RemapSwizzle[i] = 7; // SEL_MASK_WRITE
1387 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(NewBldVec[i])) {
1389 RemapSwizzle[i] = 4; // SEL_0
1390 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1391 } else if (C->isExactlyValue(1.0)) {
1392 RemapSwizzle[i] = 5; // SEL_1
1393 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1397 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1399 for (unsigned j = 0; j < i; j++) {
1400 if (NewBldVec[i] == NewBldVec[j]) {
1401 NewBldVec[i] = DAG.getUNDEF(NewBldVec[i].getValueType());
1402 RemapSwizzle[i] = j;
1408 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1409 VectorEntry.getValueType(), NewBldVec, 4);
1412 static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
1413 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1414 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1415 assert(RemapSwizzle.empty());
1416 SDValue NewBldVec[4] = {
1417 VectorEntry.getOperand(0),
1418 VectorEntry.getOperand(1),
1419 VectorEntry.getOperand(2),
1420 VectorEntry.getOperand(3)
1422 bool isUnmovable[4] = { false, false, false, false };
1423 for (unsigned i = 0; i < 4; i++)
1424 RemapSwizzle[i] = i;
1426 for (unsigned i = 0; i < 4; i++) {
1427 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1428 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1431 isUnmovable[Idx] = true;
1434 if (isUnmovable[Idx])
1437 std::swap(NewBldVec[Idx], NewBldVec[i]);
1438 std::swap(RemapSwizzle[i], RemapSwizzle[Idx]);
1443 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1444 VectorEntry.getValueType(), NewBldVec, 4);
1448 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector,
1449 SDValue Swz[4], SelectionDAG &DAG) const {
1450 assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR);
1451 // Old -> New swizzle values
1452 DenseMap<unsigned, unsigned> SwizzleRemap;
1454 BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap);
1455 for (unsigned i = 0; i < 4; i++) {
1456 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1457 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1458 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1461 SwizzleRemap.clear();
1462 BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap);
1463 for (unsigned i = 0; i < 4; i++) {
1464 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1465 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1466 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1473 //===----------------------------------------------------------------------===//
1474 // Custom DAG Optimizations
1475 //===----------------------------------------------------------------------===//
1477 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1478 DAGCombinerInfo &DCI) const {
1479 SelectionDAG &DAG = DCI.DAG;
1481 switch (N->getOpcode()) {
1482 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1483 case ISD::FP_ROUND: {
1484 SDValue Arg = N->getOperand(0);
1485 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1486 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), N->getValueType(0),
1492 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1493 // (i32 select_cc f32, f32, -1, 0 cc)
1495 // Mesa's GLSL frontend generates the above pattern a lot and we can lower
1496 // this to one of the SET*_DX10 instructions.
1497 case ISD::FP_TO_SINT: {
1498 SDValue FNeg = N->getOperand(0);
1499 if (FNeg.getOpcode() != ISD::FNEG) {
1502 SDValue SelectCC = FNeg.getOperand(0);
1503 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1504 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1505 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1506 !isHWTrueValue(SelectCC.getOperand(2)) ||
1507 !isHWFalseValue(SelectCC.getOperand(3))) {
1511 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
1512 SelectCC.getOperand(0), // LHS
1513 SelectCC.getOperand(1), // RHS
1514 DAG.getConstant(-1, MVT::i32), // True
1515 DAG.getConstant(0, MVT::i32), // Flase
1516 SelectCC.getOperand(4)); // CC
1521 // insert_vector_elt (build_vector elt0, …, eltN), NewEltIdx, idx
1522 // => build_vector elt0, …, NewEltIdx, …, eltN
1523 case ISD::INSERT_VECTOR_ELT: {
1524 SDValue InVec = N->getOperand(0);
1525 SDValue InVal = N->getOperand(1);
1526 SDValue EltNo = N->getOperand(2);
1529 // If the inserted element is an UNDEF, just use the input vector.
1530 if (InVal.getOpcode() == ISD::UNDEF)
1533 EVT VT = InVec.getValueType();
1535 // If we can't generate a legal BUILD_VECTOR, exit
1536 if (!isOperationLegal(ISD::BUILD_VECTOR, VT))
1539 // Check that we know which element is being inserted
1540 if (!isa<ConstantSDNode>(EltNo))
1542 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
1544 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
1545 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
1547 SmallVector<SDValue, 8> Ops;
1548 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
1549 Ops.append(InVec.getNode()->op_begin(),
1550 InVec.getNode()->op_end());
1551 } else if (InVec.getOpcode() == ISD::UNDEF) {
1552 unsigned NElts = VT.getVectorNumElements();
1553 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
1558 // Insert the element
1559 if (Elt < Ops.size()) {
1560 // All the operands of BUILD_VECTOR must have the same type;
1561 // we enforce that here.
1562 EVT OpVT = Ops[0].getValueType();
1563 if (InVal.getValueType() != OpVT)
1564 InVal = OpVT.bitsGT(InVal.getValueType()) ?
1565 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
1566 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
1570 // Return the new vector
1571 return DAG.getNode(ISD::BUILD_VECTOR, dl,
1572 VT, &Ops[0], Ops.size());
1575 // Extract_vec (Build_vector) generated by custom lowering
1576 // also needs to be customly combined
1577 case ISD::EXTRACT_VECTOR_ELT: {
1578 SDValue Arg = N->getOperand(0);
1579 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1580 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1581 unsigned Element = Const->getZExtValue();
1582 return Arg->getOperand(Element);
1585 if (Arg.getOpcode() == ISD::BITCAST &&
1586 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1587 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1588 unsigned Element = Const->getZExtValue();
1589 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getVTList(),
1590 Arg->getOperand(0).getOperand(Element));
1595 case ISD::SELECT_CC: {
1596 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1597 // selectcc x, y, a, b, inv(cc)
1599 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
1600 // selectcc x, y, a, b, cc
1601 SDValue LHS = N->getOperand(0);
1602 if (LHS.getOpcode() != ISD::SELECT_CC) {
1606 SDValue RHS = N->getOperand(1);
1607 SDValue True = N->getOperand(2);
1608 SDValue False = N->getOperand(3);
1609 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1611 if (LHS.getOperand(2).getNode() != True.getNode() ||
1612 LHS.getOperand(3).getNode() != False.getNode() ||
1613 RHS.getNode() != False.getNode()) {
1618 default: return SDValue();
1619 case ISD::SETNE: return LHS;
1621 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
1622 LHSCC = ISD::getSetCCInverse(LHSCC,
1623 LHS.getOperand(0).getValueType().isInteger());
1624 if (DCI.isBeforeLegalizeOps() ||
1625 isCondCodeLegal(LHSCC, LHS.getOperand(0).getSimpleValueType()))
1626 return DAG.getSelectCC(SDLoc(N),
1638 case AMDGPUISD::EXPORT: {
1639 SDValue Arg = N->getOperand(1);
1640 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1643 SDValue NewArgs[8] = {
1644 N->getOperand(0), // Chain
1646 N->getOperand(2), // ArrayBase
1647 N->getOperand(3), // Type
1648 N->getOperand(4), // SWZ_X
1649 N->getOperand(5), // SWZ_Y
1650 N->getOperand(6), // SWZ_Z
1651 N->getOperand(7) // SWZ_W
1654 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG);
1655 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs, 8);
1657 case AMDGPUISD::TEXTURE_FETCH: {
1658 SDValue Arg = N->getOperand(1);
1659 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1662 SDValue NewArgs[19] = {
1683 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG);
1684 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, SDLoc(N), N->getVTList(),
1692 FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src, SDValue &Neg,
1693 SDValue &Abs, SDValue &Sel, SDValue &Imm, SelectionDAG &DAG) {
1694 const R600InstrInfo *TII =
1695 static_cast<const R600InstrInfo *>(DAG.getTarget().getInstrInfo());
1696 if (!Src.isMachineOpcode())
1698 switch (Src.getMachineOpcode()) {
1699 case AMDGPU::FNEG_R600:
1702 Src = Src.getOperand(0);
1703 Neg = DAG.getTargetConstant(1, MVT::i32);
1705 case AMDGPU::FABS_R600:
1708 Src = Src.getOperand(0);
1709 Abs = DAG.getTargetConstant(1, MVT::i32);
1711 case AMDGPU::CONST_COPY: {
1712 unsigned Opcode = ParentNode->getMachineOpcode();
1713 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
1718 SDValue CstOffset = Src.getOperand(0);
1719 if (ParentNode->getValueType(0).isVector())
1722 // Gather constants values
1723 int SrcIndices[] = {
1724 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
1725 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
1726 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2),
1727 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
1728 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
1729 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
1730 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
1731 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
1732 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
1733 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
1734 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
1736 std::vector<unsigned> Consts;
1737 for (unsigned i = 0; i < sizeof(SrcIndices) / sizeof(int); i++) {
1738 int OtherSrcIdx = SrcIndices[i];
1739 int OtherSelIdx = TII->getSelIdx(Opcode, OtherSrcIdx);
1740 if (OtherSrcIdx < 0 || OtherSelIdx < 0)
1746 if (RegisterSDNode *Reg =
1747 dyn_cast<RegisterSDNode>(ParentNode->getOperand(OtherSrcIdx))) {
1748 if (Reg->getReg() == AMDGPU::ALU_CONST) {
1749 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(
1750 ParentNode->getOperand(OtherSelIdx));
1751 Consts.push_back(Cst->getZExtValue());
1756 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(CstOffset);
1757 Consts.push_back(Cst->getZExtValue());
1758 if (!TII->fitsConstReadLimitations(Consts)) {
1763 Src = DAG.getRegister(AMDGPU::ALU_CONST, MVT::f32);
1766 case AMDGPU::MOV_IMM_I32:
1767 case AMDGPU::MOV_IMM_F32: {
1768 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
1769 uint64_t ImmValue = 0;
1772 if (Src.getMachineOpcode() == AMDGPU::MOV_IMM_F32) {
1773 ConstantFPSDNode *FPC = dyn_cast<ConstantFPSDNode>(Src.getOperand(0));
1774 float FloatValue = FPC->getValueAPF().convertToFloat();
1775 if (FloatValue == 0.0) {
1776 ImmReg = AMDGPU::ZERO;
1777 } else if (FloatValue == 0.5) {
1778 ImmReg = AMDGPU::HALF;
1779 } else if (FloatValue == 1.0) {
1780 ImmReg = AMDGPU::ONE;
1782 ImmValue = FPC->getValueAPF().bitcastToAPInt().getZExtValue();
1785 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src.getOperand(0));
1786 uint64_t Value = C->getZExtValue();
1788 ImmReg = AMDGPU::ZERO;
1789 } else if (Value == 1) {
1790 ImmReg = AMDGPU::ONE_INT;
1796 // Check that we aren't already using an immediate.
1797 // XXX: It's possible for an instruction to have more than one
1798 // immediate operand, but this is not supported yet.
1799 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
1802 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Imm);
1804 if (C->getZExtValue())
1806 Imm = DAG.getTargetConstant(ImmValue, MVT::i32);
1808 Src = DAG.getRegister(ImmReg, MVT::i32);
1817 /// \brief Fold the instructions after selecting them
1818 SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node,
1819 SelectionDAG &DAG) const {
1820 const R600InstrInfo *TII =
1821 static_cast<const R600InstrInfo *>(DAG.getTarget().getInstrInfo());
1822 if (!Node->isMachineOpcode())
1824 unsigned Opcode = Node->getMachineOpcode();
1827 std::vector<SDValue> Ops;
1828 for(SDNode::op_iterator I = Node->op_begin(), E = Node->op_end();
1832 if (Opcode == AMDGPU::DOT_4) {
1833 int OperandIdx[] = {
1834 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
1835 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
1836 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
1837 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
1838 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
1839 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
1840 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
1841 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
1844 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_X),
1845 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Y),
1846 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Z),
1847 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_W),
1848 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_X),
1849 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Y),
1850 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Z),
1851 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_W)
1854 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_X),
1855 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Y),
1856 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Z),
1857 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_W),
1858 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_X),
1859 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Y),
1860 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Z),
1861 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_W)
1863 for (unsigned i = 0; i < 8; i++) {
1864 if (OperandIdx[i] < 0)
1866 SDValue &Src = Ops[OperandIdx[i] - 1];
1867 SDValue &Neg = Ops[NegIdx[i] - 1];
1868 SDValue &Abs = Ops[AbsIdx[i] - 1];
1869 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
1870 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
1873 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
1874 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, FakeOp, DAG))
1875 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
1877 } else if (Opcode == AMDGPU::REG_SEQUENCE) {
1878 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) {
1879 SDValue &Src = Ops[i];
1880 if (FoldOperand(Node, i, Src, FakeOp, FakeOp, FakeOp, FakeOp, DAG))
1881 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
1883 } else if (Opcode == AMDGPU::CLAMP_R600) {
1884 SDValue Src = Node->getOperand(0);
1885 if (!Src.isMachineOpcode() ||
1886 !TII->hasInstrModifiers(Src.getMachineOpcode()))
1888 int ClampIdx = TII->getOperandIdx(Src.getMachineOpcode(),
1889 AMDGPU::OpName::clamp);
1892 std::vector<SDValue> Ops;
1893 unsigned NumOp = Src.getNumOperands();
1894 for(unsigned i = 0; i < NumOp; ++i)
1895 Ops.push_back(Src.getOperand(i));
1896 Ops[ClampIdx - 1] = DAG.getTargetConstant(1, MVT::i32);
1897 return DAG.getMachineNode(Src.getMachineOpcode(), SDLoc(Node),
1898 Node->getVTList(), Ops);
1900 if (!TII->hasInstrModifiers(Opcode))
1902 int OperandIdx[] = {
1903 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
1904 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
1905 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2)
1908 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg),
1909 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg),
1910 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2_neg)
1913 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs),
1914 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs),
1917 for (unsigned i = 0; i < 3; i++) {
1918 if (OperandIdx[i] < 0)
1920 SDValue &Src = Ops[OperandIdx[i] - 1];
1921 SDValue &Neg = Ops[NegIdx[i] - 1];
1923 SDValue &Abs = (AbsIdx[i] > -1) ? Ops[AbsIdx[i] - 1] : FakeAbs;
1924 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
1925 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
1926 int ImmIdx = TII->getOperandIdx(Opcode, AMDGPU::OpName::literal);
1931 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
1932 SDValue &Imm = Ops[ImmIdx];
1933 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, Imm, DAG))
1934 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);