1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for R600
13 //===----------------------------------------------------------------------===//
15 #include "R600ISelLowering.h"
16 #include "R600Defines.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineFunctionInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/IR/Argument.h"
25 #include "llvm/IR/Function.h"
29 R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
30 AMDGPUTargetLowering(TM),
31 Gen(TM.getSubtarget<AMDGPUSubtarget>().getGeneration()) {
32 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
34 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
35 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
36 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
37 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
39 computeRegisterProperties();
41 // Set condition code actions
42 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
43 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
44 setCondCodeAction(ISD::SETLT, MVT::f32, Expand);
45 setCondCodeAction(ISD::SETLE, MVT::f32, Expand);
46 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
47 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
48 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
49 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
50 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
51 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
52 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
53 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
55 setCondCodeAction(ISD::SETLE, MVT::i32, Expand);
56 setCondCodeAction(ISD::SETLT, MVT::i32, Expand);
57 setCondCodeAction(ISD::SETULE, MVT::i32, Expand);
58 setCondCodeAction(ISD::SETULT, MVT::i32, Expand);
60 setOperationAction(ISD::FCOS, MVT::f32, Custom);
61 setOperationAction(ISD::FSIN, MVT::f32, Custom);
63 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
64 setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
66 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
67 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
69 setOperationAction(ISD::FSUB, MVT::f32, Expand);
71 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
72 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
73 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
75 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
76 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
78 setOperationAction(ISD::SETCC, MVT::i32, Expand);
79 setOperationAction(ISD::SETCC, MVT::f32, Expand);
80 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
82 setOperationAction(ISD::SELECT, MVT::i32, Expand);
83 setOperationAction(ISD::SELECT, MVT::f32, Expand);
84 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
85 setOperationAction(ISD::SELECT, MVT::v2f32, Expand);
86 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
87 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
89 // Expand sign extension of vectors
90 if (!Subtarget->hasBFE())
91 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
93 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand);
94 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand);
96 if (!Subtarget->hasBFE())
97 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
98 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand);
99 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand);
101 if (!Subtarget->hasBFE())
102 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
103 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand);
104 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
106 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand);
108 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand);
110 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
113 // Legalize loads and stores to the private address space.
114 setOperationAction(ISD::LOAD, MVT::i32, Custom);
115 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
116 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
118 // EXTLOAD should be the same as ZEXTLOAD. It is legal for some address
119 // spaces, so it is custom lowered to handle those where it isn't.
120 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
121 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
122 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
123 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
124 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
125 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Custom);
127 setOperationAction(ISD::STORE, MVT::i8, Custom);
128 setOperationAction(ISD::STORE, MVT::i32, Custom);
129 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
130 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
131 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
132 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
134 setOperationAction(ISD::LOAD, MVT::i32, Custom);
135 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
136 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
138 setTargetDAGCombine(ISD::FP_ROUND);
139 setTargetDAGCombine(ISD::FP_TO_SINT);
140 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
141 setTargetDAGCombine(ISD::SELECT_CC);
142 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
144 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
146 setBooleanContents(ZeroOrNegativeOneBooleanContent);
147 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
148 setSchedulingPreference(Sched::Source);
151 MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
152 MachineInstr * MI, MachineBasicBlock * BB) const {
153 MachineFunction * MF = BB->getParent();
154 MachineRegisterInfo &MRI = MF->getRegInfo();
155 MachineBasicBlock::iterator I = *MI;
156 const R600InstrInfo *TII =
157 static_cast<const R600InstrInfo*>(MF->getTarget().getInstrInfo());
159 switch (MI->getOpcode()) {
161 // Replace LDS_*_RET instruction that don't have any uses with the
162 // equivalent LDS_*_NORET instruction.
163 if (TII->isLDSRetInstr(MI->getOpcode())) {
164 int DstIdx = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
165 assert(DstIdx != -1);
166 MachineInstrBuilder NewMI;
167 if (!MRI.use_empty(MI->getOperand(DstIdx).getReg()))
170 NewMI = BuildMI(*BB, I, BB->findDebugLoc(I),
171 TII->get(AMDGPU::getLDSNoRetOp(MI->getOpcode())));
172 for (unsigned i = 1, e = MI->getNumOperands(); i < e; ++i) {
173 NewMI.addOperand(MI->getOperand(i));
176 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
179 case AMDGPU::CLAMP_R600: {
180 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
182 MI->getOperand(0).getReg(),
183 MI->getOperand(1).getReg());
184 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
188 case AMDGPU::FABS_R600: {
189 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
191 MI->getOperand(0).getReg(),
192 MI->getOperand(1).getReg());
193 TII->addFlag(NewMI, 0, MO_FLAG_ABS);
197 case AMDGPU::FNEG_R600: {
198 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
200 MI->getOperand(0).getReg(),
201 MI->getOperand(1).getReg());
202 TII->addFlag(NewMI, 0, MO_FLAG_NEG);
206 case AMDGPU::MASK_WRITE: {
207 unsigned maskedRegister = MI->getOperand(0).getReg();
208 assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
209 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
210 TII->addFlag(defInstr, 0, MO_FLAG_MASK);
214 case AMDGPU::MOV_IMM_F32:
215 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
216 MI->getOperand(1).getFPImm()->getValueAPF()
217 .bitcastToAPInt().getZExtValue());
219 case AMDGPU::MOV_IMM_I32:
220 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
221 MI->getOperand(1).getImm());
223 case AMDGPU::CONST_COPY: {
224 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
225 MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
226 TII->setImmOperand(NewMI, AMDGPU::OpName::src0_sel,
227 MI->getOperand(1).getImm());
231 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
232 case AMDGPU::RAT_WRITE_CACHELESS_64_eg:
233 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
234 unsigned EOP = (std::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
236 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
237 .addOperand(MI->getOperand(0))
238 .addOperand(MI->getOperand(1))
239 .addImm(EOP); // Set End of program bit
244 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
245 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
246 MachineOperand &RID = MI->getOperand(4);
247 MachineOperand &SID = MI->getOperand(5);
248 unsigned TextureId = MI->getOperand(6).getImm();
249 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
250 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
262 case 8: // ShadowRect
273 case 11: // Shadow1DArray
277 case 12: // Shadow2DArray
281 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
282 .addOperand(MI->getOperand(3))
300 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
301 .addOperand(MI->getOperand(2))
319 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
320 .addOperand(MI->getOperand(0))
321 .addOperand(MI->getOperand(1))
339 .addReg(T0, RegState::Implicit)
340 .addReg(T1, RegState::Implicit);
344 case AMDGPU::TXD_SHADOW: {
345 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
346 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
347 MachineOperand &RID = MI->getOperand(4);
348 MachineOperand &SID = MI->getOperand(5);
349 unsigned TextureId = MI->getOperand(6).getImm();
350 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
351 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
363 case 8: // ShadowRect
374 case 11: // Shadow1DArray
378 case 12: // Shadow2DArray
383 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
384 .addOperand(MI->getOperand(3))
402 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
403 .addOperand(MI->getOperand(2))
421 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
422 .addOperand(MI->getOperand(0))
423 .addOperand(MI->getOperand(1))
441 .addReg(T0, RegState::Implicit)
442 .addReg(T1, RegState::Implicit);
447 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
448 .addOperand(MI->getOperand(0));
451 case AMDGPU::BRANCH_COND_f32: {
452 MachineInstr *NewMI =
453 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
454 AMDGPU::PREDICATE_BIT)
455 .addOperand(MI->getOperand(1))
456 .addImm(OPCODE_IS_NOT_ZERO)
458 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
459 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
460 .addOperand(MI->getOperand(0))
461 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
465 case AMDGPU::BRANCH_COND_i32: {
466 MachineInstr *NewMI =
467 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
468 AMDGPU::PREDICATE_BIT)
469 .addOperand(MI->getOperand(1))
470 .addImm(OPCODE_IS_NOT_ZERO_INT)
472 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
473 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
474 .addOperand(MI->getOperand(0))
475 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
479 case AMDGPU::EG_ExportSwz:
480 case AMDGPU::R600_ExportSwz: {
481 // Instruction is left unmodified if its not the last one of its type
482 bool isLastInstructionOfItsType = true;
483 unsigned InstExportType = MI->getOperand(1).getImm();
484 for (MachineBasicBlock::iterator NextExportInst = std::next(I),
485 EndBlock = BB->end(); NextExportInst != EndBlock;
486 NextExportInst = std::next(NextExportInst)) {
487 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
488 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
489 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
491 if (CurrentInstExportType == InstExportType) {
492 isLastInstructionOfItsType = false;
497 bool EOP = (std::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
498 if (!EOP && !isLastInstructionOfItsType)
500 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
501 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
502 .addOperand(MI->getOperand(0))
503 .addOperand(MI->getOperand(1))
504 .addOperand(MI->getOperand(2))
505 .addOperand(MI->getOperand(3))
506 .addOperand(MI->getOperand(4))
507 .addOperand(MI->getOperand(5))
508 .addOperand(MI->getOperand(6))
513 case AMDGPU::RETURN: {
514 // RETURN instructions must have the live-out registers as implicit uses,
515 // otherwise they appear dead.
516 R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
517 MachineInstrBuilder MIB(*MF, MI);
518 for (unsigned i = 0, e = MFI->LiveOuts.size(); i != e; ++i)
519 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
524 MI->eraseFromParent();
528 //===----------------------------------------------------------------------===//
529 // Custom DAG Lowering Operations
530 //===----------------------------------------------------------------------===//
532 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
533 MachineFunction &MF = DAG.getMachineFunction();
534 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
535 switch (Op.getOpcode()) {
536 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
538 case ISD::FSIN: return LowerTrig(Op, DAG);
539 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
540 case ISD::STORE: return LowerSTORE(Op, DAG);
541 case ISD::LOAD: return LowerLOAD(Op, DAG);
542 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
543 case ISD::INTRINSIC_VOID: {
544 SDValue Chain = Op.getOperand(0);
545 unsigned IntrinsicID =
546 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
547 switch (IntrinsicID) {
548 case AMDGPUIntrinsic::AMDGPU_store_output: {
549 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
550 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
551 MFI->LiveOuts.push_back(Reg);
552 return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2));
554 case AMDGPUIntrinsic::R600_store_swizzle: {
555 const SDValue Args[8] = {
557 Op.getOperand(2), // Export Value
558 Op.getOperand(3), // ArrayBase
559 Op.getOperand(4), // Type
560 DAG.getConstant(0, MVT::i32), // SWZ_X
561 DAG.getConstant(1, MVT::i32), // SWZ_Y
562 DAG.getConstant(2, MVT::i32), // SWZ_Z
563 DAG.getConstant(3, MVT::i32) // SWZ_W
565 return DAG.getNode(AMDGPUISD::EXPORT, SDLoc(Op), Op.getValueType(),
569 // default for switch(IntrinsicID)
572 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
575 case ISD::INTRINSIC_WO_CHAIN: {
576 unsigned IntrinsicID =
577 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
578 EVT VT = Op.getValueType();
580 switch(IntrinsicID) {
581 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
582 case AMDGPUIntrinsic::R600_load_input: {
583 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
584 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
585 MachineFunction &MF = DAG.getMachineFunction();
586 MachineRegisterInfo &MRI = MF.getRegInfo();
588 return DAG.getCopyFromReg(DAG.getEntryNode(),
589 SDLoc(DAG.getEntryNode()), Reg, VT);
592 case AMDGPUIntrinsic::R600_interp_input: {
593 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
594 int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
595 MachineSDNode *interp;
597 const MachineFunction &MF = DAG.getMachineFunction();
598 const R600InstrInfo *TII =
599 static_cast<const R600InstrInfo*>(MF.getTarget().getInstrInfo());
600 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
601 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
602 return DAG.getTargetExtractSubreg(
603 TII->getRegisterInfo().getSubRegFromChannel(slot % 4),
604 DL, MVT::f32, SDValue(interp, 0));
606 MachineFunction &MF = DAG.getMachineFunction();
607 MachineRegisterInfo &MRI = MF.getRegInfo();
608 unsigned RegisterI = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb);
609 unsigned RegisterJ = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1);
610 MRI.addLiveIn(RegisterI);
611 MRI.addLiveIn(RegisterJ);
612 SDValue RegisterINode = DAG.getCopyFromReg(DAG.getEntryNode(),
613 SDLoc(DAG.getEntryNode()), RegisterI, MVT::f32);
614 SDValue RegisterJNode = DAG.getCopyFromReg(DAG.getEntryNode(),
615 SDLoc(DAG.getEntryNode()), RegisterJ, MVT::f32);
618 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
619 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
620 RegisterJNode, RegisterINode);
622 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
623 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
624 RegisterJNode, RegisterINode);
625 return SDValue(interp, slot % 2);
627 case AMDGPUIntrinsic::R600_interp_xy:
628 case AMDGPUIntrinsic::R600_interp_zw: {
629 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
630 MachineSDNode *interp;
631 SDValue RegisterINode = Op.getOperand(2);
632 SDValue RegisterJNode = Op.getOperand(3);
634 if (IntrinsicID == AMDGPUIntrinsic::R600_interp_xy)
635 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
636 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, MVT::i32),
637 RegisterJNode, RegisterINode);
639 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
640 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, MVT::i32),
641 RegisterJNode, RegisterINode);
642 return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32,
643 SDValue(interp, 0), SDValue(interp, 1));
645 case AMDGPUIntrinsic::R600_tex:
646 case AMDGPUIntrinsic::R600_texc:
647 case AMDGPUIntrinsic::R600_txl:
648 case AMDGPUIntrinsic::R600_txlc:
649 case AMDGPUIntrinsic::R600_txb:
650 case AMDGPUIntrinsic::R600_txbc:
651 case AMDGPUIntrinsic::R600_txf:
652 case AMDGPUIntrinsic::R600_txq:
653 case AMDGPUIntrinsic::R600_ddx:
654 case AMDGPUIntrinsic::R600_ddy:
655 case AMDGPUIntrinsic::R600_ldptr: {
657 switch (IntrinsicID) {
658 case AMDGPUIntrinsic::R600_tex:
661 case AMDGPUIntrinsic::R600_texc:
664 case AMDGPUIntrinsic::R600_txl:
667 case AMDGPUIntrinsic::R600_txlc:
670 case AMDGPUIntrinsic::R600_txb:
673 case AMDGPUIntrinsic::R600_txbc:
676 case AMDGPUIntrinsic::R600_txf:
679 case AMDGPUIntrinsic::R600_txq:
682 case AMDGPUIntrinsic::R600_ddx:
685 case AMDGPUIntrinsic::R600_ddy:
688 case AMDGPUIntrinsic::R600_ldptr:
692 llvm_unreachable("Unknow Texture Operation");
695 SDValue TexArgs[19] = {
696 DAG.getConstant(TextureOp, MVT::i32),
698 DAG.getConstant(0, MVT::i32),
699 DAG.getConstant(1, MVT::i32),
700 DAG.getConstant(2, MVT::i32),
701 DAG.getConstant(3, MVT::i32),
705 DAG.getConstant(0, MVT::i32),
706 DAG.getConstant(1, MVT::i32),
707 DAG.getConstant(2, MVT::i32),
708 DAG.getConstant(3, MVT::i32),
716 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs, 19);
718 case AMDGPUIntrinsic::AMDGPU_dp4: {
720 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
721 DAG.getConstant(0, MVT::i32)),
722 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
723 DAG.getConstant(0, MVT::i32)),
724 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
725 DAG.getConstant(1, MVT::i32)),
726 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
727 DAG.getConstant(1, MVT::i32)),
728 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
729 DAG.getConstant(2, MVT::i32)),
730 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
731 DAG.getConstant(2, MVT::i32)),
732 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
733 DAG.getConstant(3, MVT::i32)),
734 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
735 DAG.getConstant(3, MVT::i32))
737 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args, 8);
740 case Intrinsic::r600_read_ngroups_x:
741 return LowerImplicitParameter(DAG, VT, DL, 0);
742 case Intrinsic::r600_read_ngroups_y:
743 return LowerImplicitParameter(DAG, VT, DL, 1);
744 case Intrinsic::r600_read_ngroups_z:
745 return LowerImplicitParameter(DAG, VT, DL, 2);
746 case Intrinsic::r600_read_global_size_x:
747 return LowerImplicitParameter(DAG, VT, DL, 3);
748 case Intrinsic::r600_read_global_size_y:
749 return LowerImplicitParameter(DAG, VT, DL, 4);
750 case Intrinsic::r600_read_global_size_z:
751 return LowerImplicitParameter(DAG, VT, DL, 5);
752 case Intrinsic::r600_read_local_size_x:
753 return LowerImplicitParameter(DAG, VT, DL, 6);
754 case Intrinsic::r600_read_local_size_y:
755 return LowerImplicitParameter(DAG, VT, DL, 7);
756 case Intrinsic::r600_read_local_size_z:
757 return LowerImplicitParameter(DAG, VT, DL, 8);
759 case Intrinsic::r600_read_tgid_x:
760 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
762 case Intrinsic::r600_read_tgid_y:
763 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
765 case Intrinsic::r600_read_tgid_z:
766 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
768 case Intrinsic::r600_read_tidig_x:
769 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
771 case Intrinsic::r600_read_tidig_y:
772 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
774 case Intrinsic::r600_read_tidig_z:
775 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
778 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
781 } // end switch(Op.getOpcode())
785 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
786 SmallVectorImpl<SDValue> &Results,
787 SelectionDAG &DAG) const {
788 switch (N->getOpcode()) {
790 AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG);
792 case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
795 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
796 Results.push_back(SDValue(Node, 0));
797 Results.push_back(SDValue(Node, 1));
798 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
800 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
804 SDNode *Node = LowerSTORE(SDValue(N, 0), DAG).getNode();
805 Results.push_back(SDValue(Node, 0));
810 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
811 // On hw >= R700, COS/SIN input must be between -1. and 1.
812 // Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5)
813 EVT VT = Op.getValueType();
814 SDValue Arg = Op.getOperand(0);
815 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
816 DAG.getNode(ISD::FADD, SDLoc(Op), VT,
817 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
818 DAG.getConstantFP(0.15915494309, MVT::f32)),
819 DAG.getConstantFP(0.5, MVT::f32)));
821 switch (Op.getOpcode()) {
823 TrigNode = AMDGPUISD::COS_HW;
826 TrigNode = AMDGPUISD::SIN_HW;
829 llvm_unreachable("Wrong trig opcode");
831 SDValue TrigVal = DAG.getNode(TrigNode, SDLoc(Op), VT,
832 DAG.getNode(ISD::FADD, SDLoc(Op), VT, FractPart,
833 DAG.getConstantFP(-0.5, MVT::f32)));
834 if (Gen >= AMDGPUSubtarget::R700)
836 // On R600 hw, COS/SIN input must be between -Pi and Pi.
837 return DAG.getNode(ISD::FMUL, SDLoc(Op), VT, TrigVal,
838 DAG.getConstantFP(3.14159265359, MVT::f32));
841 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
846 Op, DAG.getConstantFP(0.0f, MVT::f32),
847 DAG.getCondCode(ISD::SETNE)
851 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
853 unsigned DwordOffset) const {
854 unsigned ByteOffset = DwordOffset * 4;
855 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
856 AMDGPUAS::CONSTANT_BUFFER_0);
858 // We shouldn't be using an offset wider than 16-bits for implicit parameters.
859 assert(isInt<16>(ByteOffset));
861 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
862 DAG.getConstant(ByteOffset, MVT::i32), // PTR
863 MachinePointerInfo(ConstantPointerNull::get(PtrType)),
864 false, false, false, 0);
867 bool R600TargetLowering::isZero(SDValue Op) const {
868 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
869 return Cst->isNullValue();
870 } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
871 return CstFP->isZero();
877 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
879 EVT VT = Op.getValueType();
881 SDValue LHS = Op.getOperand(0);
882 SDValue RHS = Op.getOperand(1);
883 SDValue True = Op.getOperand(2);
884 SDValue False = Op.getOperand(3);
885 SDValue CC = Op.getOperand(4);
888 // LHS and RHS are guaranteed to be the same value type
889 EVT CompareVT = LHS.getValueType();
891 // Check if we can lower this to a native operation.
893 // Try to lower to a SET* instruction:
895 // SET* can match the following patterns:
897 // select_cc f32, f32, -1, 0, cc_supported
898 // select_cc f32, f32, 1.0f, 0.0f, cc_supported
899 // select_cc i32, i32, -1, 0, cc_supported
902 // Move hardware True/False values to the correct operand.
903 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
904 ISD::CondCode InverseCC =
905 ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
906 if (isHWTrueValue(False) && isHWFalseValue(True)) {
907 if (isCondCodeLegal(InverseCC, CompareVT.getSimpleVT())) {
908 std::swap(False, True);
909 CC = DAG.getCondCode(InverseCC);
911 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InverseCC);
912 if (isCondCodeLegal(SwapInvCC, CompareVT.getSimpleVT())) {
913 std::swap(False, True);
915 CC = DAG.getCondCode(SwapInvCC);
920 if (isHWTrueValue(True) && isHWFalseValue(False) &&
921 (CompareVT == VT || VT == MVT::i32)) {
922 // This can be matched by a SET* instruction.
923 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
926 // Try to lower to a CND* instruction:
928 // CND* can match the following patterns:
930 // select_cc f32, 0.0, f32, f32, cc_supported
931 // select_cc f32, 0.0, i32, i32, cc_supported
932 // select_cc i32, 0, f32, f32, cc_supported
933 // select_cc i32, 0, i32, i32, cc_supported
936 // Try to move the zero value to the RHS
938 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
939 // Try swapping the operands
940 ISD::CondCode CCSwapped = ISD::getSetCCSwappedOperands(CCOpcode);
941 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
943 CC = DAG.getCondCode(CCSwapped);
945 // Try inverting the conditon and then swapping the operands
946 ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT.isInteger());
947 CCSwapped = ISD::getSetCCSwappedOperands(CCInv);
948 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
949 std::swap(True, False);
951 CC = DAG.getCondCode(CCSwapped);
958 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
959 if (CompareVT != VT) {
960 // Bitcast True / False to the correct types. This will end up being
961 // a nop, but it allows us to define only a single pattern in the
962 // .TD files for each CND* instruction rather than having to have
963 // one pattern for integer True/False and one for fp True/False
964 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
965 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
972 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
980 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
983 DAG.getCondCode(CCOpcode));
984 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
988 // Possible Min/Max pattern
989 SDValue MinMax = LowerMinMax(Op, DAG);
990 if (MinMax.getNode()) {
994 // If we make it this for it means we have no native instructions to handle
995 // this SELECT_CC, so we must lower it.
996 SDValue HWTrue, HWFalse;
998 if (CompareVT == MVT::f32) {
999 HWTrue = DAG.getConstantFP(1.0f, CompareVT);
1000 HWFalse = DAG.getConstantFP(0.0f, CompareVT);
1001 } else if (CompareVT == MVT::i32) {
1002 HWTrue = DAG.getConstant(-1, CompareVT);
1003 HWFalse = DAG.getConstant(0, CompareVT);
1006 llvm_unreachable("Unhandled value type in LowerSELECT_CC");
1009 // Lower this unsupported SELECT_CC into a combination of two supported
1010 // SELECT_CC operations.
1011 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
1013 return DAG.getNode(ISD::SELECT_CC, DL, VT,
1016 DAG.getCondCode(ISD::SETNE));
1019 /// LLVM generates byte-addressed pointers. For indirect addressing, we need to
1020 /// convert these pointers to a register index. Each register holds
1021 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
1022 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
1023 /// for indirect addressing.
1024 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
1025 unsigned StackWidth,
1026 SelectionDAG &DAG) const {
1028 switch(StackWidth) {
1038 default: llvm_unreachable("Invalid stack width");
1041 return DAG.getNode(ISD::SRL, SDLoc(Ptr), Ptr.getValueType(), Ptr,
1042 DAG.getConstant(SRLPad, MVT::i32));
1045 void R600TargetLowering::getStackAddress(unsigned StackWidth,
1048 unsigned &PtrIncr) const {
1049 switch (StackWidth) {
1060 Channel = ElemIdx % 2;
1074 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1076 StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
1077 SDValue Chain = Op.getOperand(0);
1078 SDValue Value = Op.getOperand(1);
1079 SDValue Ptr = Op.getOperand(2);
1081 SDValue Result = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1082 if (Result.getNode()) {
1086 if (StoreNode->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS) {
1087 if (StoreNode->isTruncatingStore()) {
1088 EVT VT = Value.getValueType();
1089 assert(VT.bitsLE(MVT::i32));
1090 EVT MemVT = StoreNode->getMemoryVT();
1091 SDValue MaskConstant;
1092 if (MemVT == MVT::i8) {
1093 MaskConstant = DAG.getConstant(0xFF, MVT::i32);
1095 assert(MemVT == MVT::i16);
1096 MaskConstant = DAG.getConstant(0xFFFF, MVT::i32);
1098 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, VT, Ptr,
1099 DAG.getConstant(2, MVT::i32));
1100 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, Ptr.getValueType(), Ptr,
1101 DAG.getConstant(0x00000003, VT));
1102 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant);
1103 SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex,
1104 DAG.getConstant(3, VT));
1105 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, Shift);
1106 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, Shift);
1107 // XXX: If we add a 64-bit ZW register class, then we could use a 2 x i32
1111 DAG.getConstant(0, MVT::i32),
1112 DAG.getConstant(0, MVT::i32),
1115 SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src, 4);
1116 SDValue Args[3] = { Chain, Input, DWordAddr };
1117 return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL,
1118 Op->getVTList(), Args, 3, MemVT,
1119 StoreNode->getMemOperand());
1120 } else if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR &&
1121 Value.getValueType().bitsGE(MVT::i32)) {
1122 // Convert pointer from byte address to dword address.
1123 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(),
1124 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
1125 Ptr, DAG.getConstant(2, MVT::i32)));
1127 if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
1128 llvm_unreachable("Truncated and indexed stores not supported yet");
1130 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
1136 EVT ValueVT = Value.getValueType();
1138 if (StoreNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1142 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1143 if (Ret.getNode()) {
1146 // Lowering for indirect addressing
1148 const MachineFunction &MF = DAG.getMachineFunction();
1149 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
1150 getTargetMachine().getFrameLowering());
1151 unsigned StackWidth = TFL->getStackWidth(MF);
1153 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1155 if (ValueVT.isVector()) {
1156 unsigned NumElemVT = ValueVT.getVectorNumElements();
1157 EVT ElemVT = ValueVT.getVectorElementType();
1160 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1161 "vector width in load");
1163 for (unsigned i = 0; i < NumElemVT; ++i) {
1164 unsigned Channel, PtrIncr;
1165 getStackAddress(StackWidth, i, Channel, PtrIncr);
1166 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1167 DAG.getConstant(PtrIncr, MVT::i32));
1168 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
1169 Value, DAG.getConstant(i, MVT::i32));
1171 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1173 DAG.getTargetConstant(Channel, MVT::i32));
1175 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores, NumElemVT);
1177 if (ValueVT == MVT::i8) {
1178 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
1180 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
1181 DAG.getTargetConstant(0, MVT::i32)); // Channel
1187 // return (512 + (kc_bank << 12)
1189 ConstantAddressBlock(unsigned AddressSpace) {
1190 switch (AddressSpace) {
1191 case AMDGPUAS::CONSTANT_BUFFER_0:
1193 case AMDGPUAS::CONSTANT_BUFFER_1:
1195 case AMDGPUAS::CONSTANT_BUFFER_2:
1196 return 512 + 4096 * 2;
1197 case AMDGPUAS::CONSTANT_BUFFER_3:
1198 return 512 + 4096 * 3;
1199 case AMDGPUAS::CONSTANT_BUFFER_4:
1200 return 512 + 4096 * 4;
1201 case AMDGPUAS::CONSTANT_BUFFER_5:
1202 return 512 + 4096 * 5;
1203 case AMDGPUAS::CONSTANT_BUFFER_6:
1204 return 512 + 4096 * 6;
1205 case AMDGPUAS::CONSTANT_BUFFER_7:
1206 return 512 + 4096 * 7;
1207 case AMDGPUAS::CONSTANT_BUFFER_8:
1208 return 512 + 4096 * 8;
1209 case AMDGPUAS::CONSTANT_BUFFER_9:
1210 return 512 + 4096 * 9;
1211 case AMDGPUAS::CONSTANT_BUFFER_10:
1212 return 512 + 4096 * 10;
1213 case AMDGPUAS::CONSTANT_BUFFER_11:
1214 return 512 + 4096 * 11;
1215 case AMDGPUAS::CONSTANT_BUFFER_12:
1216 return 512 + 4096 * 12;
1217 case AMDGPUAS::CONSTANT_BUFFER_13:
1218 return 512 + 4096 * 13;
1219 case AMDGPUAS::CONSTANT_BUFFER_14:
1220 return 512 + 4096 * 14;
1221 case AMDGPUAS::CONSTANT_BUFFER_15:
1222 return 512 + 4096 * 15;
1228 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
1230 EVT VT = Op.getValueType();
1232 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1233 SDValue Chain = Op.getOperand(0);
1234 SDValue Ptr = Op.getOperand(1);
1235 SDValue LoweredLoad;
1237 SDValue Ret = AMDGPUTargetLowering::LowerLOAD(Op, DAG);
1238 if (Ret.getNode()) {
1243 return DAG.getMergeValues(Ops, 2, DL);
1247 if (LoadNode->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS && VT.isVector()) {
1248 SDValue MergedValues[2] = {
1249 SplitVectorLoad(Op, DAG),
1252 return DAG.getMergeValues(MergedValues, 2, DL);
1255 int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
1256 if (ConstantBlock > -1 &&
1257 ((LoadNode->getExtensionType() == ISD::NON_EXTLOAD) ||
1258 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) {
1260 if (isa<ConstantExpr>(LoadNode->getMemOperand()->getValue()) ||
1261 isa<Constant>(LoadNode->getMemOperand()->getValue()) ||
1262 isa<ConstantSDNode>(Ptr)) {
1264 for (unsigned i = 0; i < 4; i++) {
1265 // We want Const position encoded with the following formula :
1266 // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
1267 // const_index is Ptr computed by llvm using an alignment of 16.
1268 // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
1269 // then div by 4 at the ISel step
1270 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1271 DAG.getConstant(4 * i + ConstantBlock * 16, MVT::i32));
1272 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1274 EVT NewVT = MVT::v4i32;
1275 unsigned NumElements = 4;
1276 if (VT.isVector()) {
1278 NumElements = VT.getVectorNumElements();
1280 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT, Slots, NumElements);
1282 // non-constant ptr can't be folded, keeps it as a v4f32 load
1283 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
1284 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
1285 DAG.getConstant(LoadNode->getAddressSpace() -
1286 AMDGPUAS::CONSTANT_BUFFER_0, MVT::i32)
1290 if (!VT.isVector()) {
1291 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1292 DAG.getConstant(0, MVT::i32));
1295 SDValue MergedValues[2] = {
1299 return DAG.getMergeValues(MergedValues, 2, DL);
1302 // For most operations returning SDValue() will result in the node being
1303 // expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so we
1304 // need to manually expand loads that may be legal in some address spaces and
1305 // illegal in others. SEXT loads from CONSTANT_BUFFER_0 are supported for
1306 // compute shaders, since the data is sign extended when it is uploaded to the
1307 // buffer. However SEXT loads from other address spaces are not supported, so
1308 // we need to expand them here.
1309 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
1310 EVT MemVT = LoadNode->getMemoryVT();
1311 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
1312 SDValue ShiftAmount =
1313 DAG.getConstant(VT.getSizeInBits() - MemVT.getSizeInBits(), MVT::i32);
1314 SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr,
1315 LoadNode->getPointerInfo(), MemVT,
1316 LoadNode->isVolatile(),
1317 LoadNode->isNonTemporal(),
1318 LoadNode->getAlignment());
1319 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, NewLoad, ShiftAmount);
1320 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Shl, ShiftAmount);
1322 SDValue MergedValues[2] = { Sra, Chain };
1323 return DAG.getMergeValues(MergedValues, 2, DL);
1326 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1330 // Lowering for indirect addressing
1331 const MachineFunction &MF = DAG.getMachineFunction();
1332 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
1333 getTargetMachine().getFrameLowering());
1334 unsigned StackWidth = TFL->getStackWidth(MF);
1336 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1338 if (VT.isVector()) {
1339 unsigned NumElemVT = VT.getVectorNumElements();
1340 EVT ElemVT = VT.getVectorElementType();
1343 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1344 "vector width in load");
1346 for (unsigned i = 0; i < NumElemVT; ++i) {
1347 unsigned Channel, PtrIncr;
1348 getStackAddress(StackWidth, i, Channel, PtrIncr);
1349 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1350 DAG.getConstant(PtrIncr, MVT::i32));
1351 Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT,
1353 DAG.getTargetConstant(Channel, MVT::i32),
1356 for (unsigned i = NumElemVT; i < 4; ++i) {
1357 Loads[i] = DAG.getUNDEF(ElemVT);
1359 EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4);
1360 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads, 4);
1362 LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
1364 DAG.getTargetConstant(0, MVT::i32), // Channel
1373 return DAG.getMergeValues(Ops, 2, DL);
1376 /// XXX Only kernel functions are supported, so we can assume for now that
1377 /// every function is a kernel function, but in the future we should use
1378 /// separate calling conventions for kernel and non-kernel functions.
1379 SDValue R600TargetLowering::LowerFormalArguments(
1381 CallingConv::ID CallConv,
1383 const SmallVectorImpl<ISD::InputArg> &Ins,
1384 SDLoc DL, SelectionDAG &DAG,
1385 SmallVectorImpl<SDValue> &InVals) const {
1386 SmallVector<CCValAssign, 16> ArgLocs;
1387 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1388 getTargetMachine(), ArgLocs, *DAG.getContext());
1389 MachineFunction &MF = DAG.getMachineFunction();
1390 unsigned ShaderType = MF.getInfo<R600MachineFunctionInfo>()->ShaderType;
1392 SmallVector<ISD::InputArg, 8> LocalIns;
1394 getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
1397 AnalyzeFormalArguments(CCInfo, LocalIns);
1399 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1400 CCValAssign &VA = ArgLocs[i];
1402 EVT MemVT = LocalIns[i].VT;
1404 if (ShaderType != ShaderType::COMPUTE) {
1405 unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass);
1406 SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT);
1407 InVals.push_back(Register);
1411 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1412 AMDGPUAS::CONSTANT_BUFFER_0);
1414 // i64 isn't a legal type, so the register type used ends up as i32, which
1415 // isn't expected here. It attempts to create this sextload, but it ends up
1416 // being invalid. Somehow this seems to work with i64 arguments, but breaks
1419 // The first 36 bytes of the input buffer contains information about
1420 // thread group and global sizes.
1422 // FIXME: This should really check the extload type, but the handling of
1423 // extload vecto parameters seems to be broken.
1424 //ISD::LoadExtType Ext = Ins[i].Flags.isSExt() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
1425 ISD::LoadExtType Ext = ISD::SEXTLOAD;
1426 SDValue Arg = DAG.getExtLoad(Ext, DL, VT, Chain,
1427 DAG.getConstant(36 + VA.getLocMemOffset(), MVT::i32),
1428 MachinePointerInfo(UndefValue::get(PtrTy)),
1429 MemVT, false, false, 4);
1430 // 4 is the preferred alignment for
1431 // the CONSTANT memory space.
1432 InVals.push_back(Arg);
1437 EVT R600TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1438 if (!VT.isVector()) return MVT::i32;
1439 return VT.changeVectorElementTypeToInteger();
1443 CompactSwizzlableVector(SelectionDAG &DAG, SDValue VectorEntry,
1444 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1445 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1446 assert(RemapSwizzle.empty());
1447 SDValue NewBldVec[4] = {
1448 VectorEntry.getOperand(0),
1449 VectorEntry.getOperand(1),
1450 VectorEntry.getOperand(2),
1451 VectorEntry.getOperand(3)
1454 for (unsigned i = 0; i < 4; i++) {
1455 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1456 // We mask write here to teach later passes that the ith element of this
1457 // vector is undef. Thus we can use it to reduce 128 bits reg usage,
1458 // break false dependencies and additionnaly make assembly easier to read.
1459 RemapSwizzle[i] = 7; // SEL_MASK_WRITE
1460 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(NewBldVec[i])) {
1462 RemapSwizzle[i] = 4; // SEL_0
1463 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1464 } else if (C->isExactlyValue(1.0)) {
1465 RemapSwizzle[i] = 5; // SEL_1
1466 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1470 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1472 for (unsigned j = 0; j < i; j++) {
1473 if (NewBldVec[i] == NewBldVec[j]) {
1474 NewBldVec[i] = DAG.getUNDEF(NewBldVec[i].getValueType());
1475 RemapSwizzle[i] = j;
1481 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1482 VectorEntry.getValueType(), NewBldVec, 4);
1485 static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
1486 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1487 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1488 assert(RemapSwizzle.empty());
1489 SDValue NewBldVec[4] = {
1490 VectorEntry.getOperand(0),
1491 VectorEntry.getOperand(1),
1492 VectorEntry.getOperand(2),
1493 VectorEntry.getOperand(3)
1495 bool isUnmovable[4] = { false, false, false, false };
1496 for (unsigned i = 0; i < 4; i++) {
1497 RemapSwizzle[i] = i;
1498 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1499 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1502 isUnmovable[Idx] = true;
1506 for (unsigned i = 0; i < 4; i++) {
1507 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1508 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1510 if (isUnmovable[Idx])
1513 std::swap(NewBldVec[Idx], NewBldVec[i]);
1514 std::swap(RemapSwizzle[i], RemapSwizzle[Idx]);
1519 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1520 VectorEntry.getValueType(), NewBldVec, 4);
1524 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector,
1525 SDValue Swz[4], SelectionDAG &DAG) const {
1526 assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR);
1527 // Old -> New swizzle values
1528 DenseMap<unsigned, unsigned> SwizzleRemap;
1530 BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap);
1531 for (unsigned i = 0; i < 4; i++) {
1532 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1533 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1534 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1537 SwizzleRemap.clear();
1538 BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap);
1539 for (unsigned i = 0; i < 4; i++) {
1540 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1541 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1542 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1549 //===----------------------------------------------------------------------===//
1550 // Custom DAG Optimizations
1551 //===----------------------------------------------------------------------===//
1553 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1554 DAGCombinerInfo &DCI) const {
1555 SelectionDAG &DAG = DCI.DAG;
1557 switch (N->getOpcode()) {
1558 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1559 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1560 case ISD::FP_ROUND: {
1561 SDValue Arg = N->getOperand(0);
1562 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1563 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), N->getValueType(0),
1569 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1570 // (i32 select_cc f32, f32, -1, 0 cc)
1572 // Mesa's GLSL frontend generates the above pattern a lot and we can lower
1573 // this to one of the SET*_DX10 instructions.
1574 case ISD::FP_TO_SINT: {
1575 SDValue FNeg = N->getOperand(0);
1576 if (FNeg.getOpcode() != ISD::FNEG) {
1579 SDValue SelectCC = FNeg.getOperand(0);
1580 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1581 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1582 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1583 !isHWTrueValue(SelectCC.getOperand(2)) ||
1584 !isHWFalseValue(SelectCC.getOperand(3))) {
1588 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
1589 SelectCC.getOperand(0), // LHS
1590 SelectCC.getOperand(1), // RHS
1591 DAG.getConstant(-1, MVT::i32), // True
1592 DAG.getConstant(0, MVT::i32), // Flase
1593 SelectCC.getOperand(4)); // CC
1598 // insert_vector_elt (build_vector elt0, ... , eltN), NewEltIdx, idx
1599 // => build_vector elt0, ... , NewEltIdx, ... , eltN
1600 case ISD::INSERT_VECTOR_ELT: {
1601 SDValue InVec = N->getOperand(0);
1602 SDValue InVal = N->getOperand(1);
1603 SDValue EltNo = N->getOperand(2);
1606 // If the inserted element is an UNDEF, just use the input vector.
1607 if (InVal.getOpcode() == ISD::UNDEF)
1610 EVT VT = InVec.getValueType();
1612 // If we can't generate a legal BUILD_VECTOR, exit
1613 if (!isOperationLegal(ISD::BUILD_VECTOR, VT))
1616 // Check that we know which element is being inserted
1617 if (!isa<ConstantSDNode>(EltNo))
1619 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
1621 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
1622 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
1624 SmallVector<SDValue, 8> Ops;
1625 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
1626 Ops.append(InVec.getNode()->op_begin(),
1627 InVec.getNode()->op_end());
1628 } else if (InVec.getOpcode() == ISD::UNDEF) {
1629 unsigned NElts = VT.getVectorNumElements();
1630 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
1635 // Insert the element
1636 if (Elt < Ops.size()) {
1637 // All the operands of BUILD_VECTOR must have the same type;
1638 // we enforce that here.
1639 EVT OpVT = Ops[0].getValueType();
1640 if (InVal.getValueType() != OpVT)
1641 InVal = OpVT.bitsGT(InVal.getValueType()) ?
1642 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
1643 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
1647 // Return the new vector
1648 return DAG.getNode(ISD::BUILD_VECTOR, dl,
1649 VT, Ops.data(), Ops.size());
1652 // Extract_vec (Build_vector) generated by custom lowering
1653 // also needs to be customly combined
1654 case ISD::EXTRACT_VECTOR_ELT: {
1655 SDValue Arg = N->getOperand(0);
1656 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1657 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1658 unsigned Element = Const->getZExtValue();
1659 return Arg->getOperand(Element);
1662 if (Arg.getOpcode() == ISD::BITCAST &&
1663 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1664 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1665 unsigned Element = Const->getZExtValue();
1666 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getVTList(),
1667 Arg->getOperand(0).getOperand(Element));
1672 case ISD::SELECT_CC: {
1673 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1674 // selectcc x, y, a, b, inv(cc)
1676 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
1677 // selectcc x, y, a, b, cc
1678 SDValue LHS = N->getOperand(0);
1679 if (LHS.getOpcode() != ISD::SELECT_CC) {
1683 SDValue RHS = N->getOperand(1);
1684 SDValue True = N->getOperand(2);
1685 SDValue False = N->getOperand(3);
1686 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1688 if (LHS.getOperand(2).getNode() != True.getNode() ||
1689 LHS.getOperand(3).getNode() != False.getNode() ||
1690 RHS.getNode() != False.getNode()) {
1695 default: return SDValue();
1696 case ISD::SETNE: return LHS;
1698 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
1699 LHSCC = ISD::getSetCCInverse(LHSCC,
1700 LHS.getOperand(0).getValueType().isInteger());
1701 if (DCI.isBeforeLegalizeOps() ||
1702 isCondCodeLegal(LHSCC, LHS.getOperand(0).getSimpleValueType()))
1703 return DAG.getSelectCC(SDLoc(N),
1715 case AMDGPUISD::EXPORT: {
1716 SDValue Arg = N->getOperand(1);
1717 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1720 SDValue NewArgs[8] = {
1721 N->getOperand(0), // Chain
1723 N->getOperand(2), // ArrayBase
1724 N->getOperand(3), // Type
1725 N->getOperand(4), // SWZ_X
1726 N->getOperand(5), // SWZ_Y
1727 N->getOperand(6), // SWZ_Z
1728 N->getOperand(7) // SWZ_W
1731 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG);
1732 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs, 8);
1734 case AMDGPUISD::TEXTURE_FETCH: {
1735 SDValue Arg = N->getOperand(1);
1736 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1739 SDValue NewArgs[19] = {
1760 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG);
1761 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, SDLoc(N), N->getVTList(),
1769 FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src, SDValue &Neg,
1770 SDValue &Abs, SDValue &Sel, SDValue &Imm, SelectionDAG &DAG) {
1771 const R600InstrInfo *TII =
1772 static_cast<const R600InstrInfo *>(DAG.getTarget().getInstrInfo());
1773 if (!Src.isMachineOpcode())
1775 switch (Src.getMachineOpcode()) {
1776 case AMDGPU::FNEG_R600:
1779 Src = Src.getOperand(0);
1780 Neg = DAG.getTargetConstant(1, MVT::i32);
1782 case AMDGPU::FABS_R600:
1785 Src = Src.getOperand(0);
1786 Abs = DAG.getTargetConstant(1, MVT::i32);
1788 case AMDGPU::CONST_COPY: {
1789 unsigned Opcode = ParentNode->getMachineOpcode();
1790 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
1795 SDValue CstOffset = Src.getOperand(0);
1796 if (ParentNode->getValueType(0).isVector())
1799 // Gather constants values
1800 int SrcIndices[] = {
1801 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
1802 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
1803 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2),
1804 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
1805 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
1806 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
1807 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
1808 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
1809 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
1810 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
1811 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
1813 std::vector<unsigned> Consts;
1814 for (unsigned i = 0; i < sizeof(SrcIndices) / sizeof(int); i++) {
1815 int OtherSrcIdx = SrcIndices[i];
1816 int OtherSelIdx = TII->getSelIdx(Opcode, OtherSrcIdx);
1817 if (OtherSrcIdx < 0 || OtherSelIdx < 0)
1823 if (RegisterSDNode *Reg =
1824 dyn_cast<RegisterSDNode>(ParentNode->getOperand(OtherSrcIdx))) {
1825 if (Reg->getReg() == AMDGPU::ALU_CONST) {
1826 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(
1827 ParentNode->getOperand(OtherSelIdx));
1828 Consts.push_back(Cst->getZExtValue());
1833 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(CstOffset);
1834 Consts.push_back(Cst->getZExtValue());
1835 if (!TII->fitsConstReadLimitations(Consts)) {
1840 Src = DAG.getRegister(AMDGPU::ALU_CONST, MVT::f32);
1843 case AMDGPU::MOV_IMM_I32:
1844 case AMDGPU::MOV_IMM_F32: {
1845 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
1846 uint64_t ImmValue = 0;
1849 if (Src.getMachineOpcode() == AMDGPU::MOV_IMM_F32) {
1850 ConstantFPSDNode *FPC = dyn_cast<ConstantFPSDNode>(Src.getOperand(0));
1851 float FloatValue = FPC->getValueAPF().convertToFloat();
1852 if (FloatValue == 0.0) {
1853 ImmReg = AMDGPU::ZERO;
1854 } else if (FloatValue == 0.5) {
1855 ImmReg = AMDGPU::HALF;
1856 } else if (FloatValue == 1.0) {
1857 ImmReg = AMDGPU::ONE;
1859 ImmValue = FPC->getValueAPF().bitcastToAPInt().getZExtValue();
1862 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src.getOperand(0));
1863 uint64_t Value = C->getZExtValue();
1865 ImmReg = AMDGPU::ZERO;
1866 } else if (Value == 1) {
1867 ImmReg = AMDGPU::ONE_INT;
1873 // Check that we aren't already using an immediate.
1874 // XXX: It's possible for an instruction to have more than one
1875 // immediate operand, but this is not supported yet.
1876 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
1879 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Imm);
1881 if (C->getZExtValue())
1883 Imm = DAG.getTargetConstant(ImmValue, MVT::i32);
1885 Src = DAG.getRegister(ImmReg, MVT::i32);
1894 /// \brief Fold the instructions after selecting them
1895 SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node,
1896 SelectionDAG &DAG) const {
1897 const R600InstrInfo *TII =
1898 static_cast<const R600InstrInfo *>(DAG.getTarget().getInstrInfo());
1899 if (!Node->isMachineOpcode())
1901 unsigned Opcode = Node->getMachineOpcode();
1904 std::vector<SDValue> Ops;
1905 for(SDNode::op_iterator I = Node->op_begin(), E = Node->op_end();
1909 if (Opcode == AMDGPU::DOT_4) {
1910 int OperandIdx[] = {
1911 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
1912 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
1913 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
1914 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
1915 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
1916 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
1917 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
1918 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
1921 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_X),
1922 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Y),
1923 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Z),
1924 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_W),
1925 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_X),
1926 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Y),
1927 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Z),
1928 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_W)
1931 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_X),
1932 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Y),
1933 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Z),
1934 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_W),
1935 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_X),
1936 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Y),
1937 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Z),
1938 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_W)
1940 for (unsigned i = 0; i < 8; i++) {
1941 if (OperandIdx[i] < 0)
1943 SDValue &Src = Ops[OperandIdx[i] - 1];
1944 SDValue &Neg = Ops[NegIdx[i] - 1];
1945 SDValue &Abs = Ops[AbsIdx[i] - 1];
1946 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
1947 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
1950 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
1951 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, FakeOp, DAG))
1952 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
1954 } else if (Opcode == AMDGPU::REG_SEQUENCE) {
1955 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) {
1956 SDValue &Src = Ops[i];
1957 if (FoldOperand(Node, i, Src, FakeOp, FakeOp, FakeOp, FakeOp, DAG))
1958 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
1960 } else if (Opcode == AMDGPU::CLAMP_R600) {
1961 SDValue Src = Node->getOperand(0);
1962 if (!Src.isMachineOpcode() ||
1963 !TII->hasInstrModifiers(Src.getMachineOpcode()))
1965 int ClampIdx = TII->getOperandIdx(Src.getMachineOpcode(),
1966 AMDGPU::OpName::clamp);
1969 std::vector<SDValue> Ops;
1970 unsigned NumOp = Src.getNumOperands();
1971 for(unsigned i = 0; i < NumOp; ++i)
1972 Ops.push_back(Src.getOperand(i));
1973 Ops[ClampIdx - 1] = DAG.getTargetConstant(1, MVT::i32);
1974 return DAG.getMachineNode(Src.getMachineOpcode(), SDLoc(Node),
1975 Node->getVTList(), Ops);
1977 if (!TII->hasInstrModifiers(Opcode))
1979 int OperandIdx[] = {
1980 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
1981 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
1982 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2)
1985 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg),
1986 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg),
1987 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2_neg)
1990 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs),
1991 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs),
1994 for (unsigned i = 0; i < 3; i++) {
1995 if (OperandIdx[i] < 0)
1997 SDValue &Src = Ops[OperandIdx[i] - 1];
1998 SDValue &Neg = Ops[NegIdx[i] - 1];
2000 SDValue &Abs = (AbsIdx[i] > -1) ? Ops[AbsIdx[i] - 1] : FakeAbs;
2001 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2002 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
2003 int ImmIdx = TII->getOperandIdx(Opcode, AMDGPU::OpName::literal);
2008 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2009 SDValue &Imm = Ops[ImmIdx];
2010 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, Imm, DAG))
2011 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);