1 //===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief R600 Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
15 #include "R600InstrInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "R600Defines.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #define GET_INSTRINFO_CTOR_DTOR
27 #include "AMDGPUGenDFAPacketizer.inc"
31 R600InstrInfo::R600InstrInfo(AMDGPUTargetMachine &tm)
32 : AMDGPUInstrInfo(tm),
34 ST(tm.getSubtarget<AMDGPUSubtarget>())
37 const R600RegisterInfo &R600InstrInfo::getRegisterInfo() const {
41 bool R600InstrInfo::isTrig(const MachineInstr &MI) const {
42 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
45 bool R600InstrInfo::isVector(const MachineInstr &MI) const {
46 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
50 R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
51 MachineBasicBlock::iterator MI, DebugLoc DL,
52 unsigned DestReg, unsigned SrcReg,
54 unsigned VectorComponents = 0;
55 if (AMDGPU::R600_Reg128RegClass.contains(DestReg) &&
56 AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
58 } else if(AMDGPU::R600_Reg64RegClass.contains(DestReg) &&
59 AMDGPU::R600_Reg64RegClass.contains(SrcReg)) {
63 if (VectorComponents > 0) {
64 for (unsigned I = 0; I < VectorComponents; I++) {
65 unsigned SubRegIndex = RI.getSubRegFromChannel(I);
66 buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
67 RI.getSubReg(DestReg, SubRegIndex),
68 RI.getSubReg(SrcReg, SubRegIndex))
70 RegState::Define | RegState::Implicit);
73 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
75 NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0))
80 /// \returns true if \p MBBI can be moved into a new basic.
81 bool R600InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
82 MachineBasicBlock::iterator MBBI) const {
83 for (MachineInstr::const_mop_iterator I = MBBI->operands_begin(),
84 E = MBBI->operands_end(); I != E; ++I) {
85 if (I->isReg() && !TargetRegisterInfo::isVirtualRegister(I->getReg()) &&
86 I->isUse() && RI.isPhysRegLiveAcrossClauses(I->getReg()))
92 unsigned R600InstrInfo::getIEQOpcode() const {
93 return AMDGPU::SETE_INT;
96 bool R600InstrInfo::isMov(unsigned Opcode) const {
100 default: return false;
102 case AMDGPU::MOV_IMM_F32:
103 case AMDGPU::MOV_IMM_I32:
108 // Some instructions act as place holders to emulate operations that the GPU
109 // hardware does automatically. This function can be used to check if
110 // an opcode falls into this category.
111 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const {
113 default: return false;
119 bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
123 bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
125 default: return false;
126 case AMDGPU::CUBE_r600_pseudo:
127 case AMDGPU::CUBE_r600_real:
128 case AMDGPU::CUBE_eg_pseudo:
129 case AMDGPU::CUBE_eg_real:
134 bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
135 unsigned TargetFlags = get(Opcode).TSFlags;
137 return (TargetFlags & R600_InstFlag::ALU_INST);
140 bool R600InstrInfo::hasInstrModifiers(unsigned Opcode) const {
141 unsigned TargetFlags = get(Opcode).TSFlags;
143 return ((TargetFlags & R600_InstFlag::OP1) |
144 (TargetFlags & R600_InstFlag::OP2) |
145 (TargetFlags & R600_InstFlag::OP3));
148 bool R600InstrInfo::isLDSInstr(unsigned Opcode) const {
149 unsigned TargetFlags = get(Opcode).TSFlags;
151 return ((TargetFlags & R600_InstFlag::LDS_1A) |
152 (TargetFlags & R600_InstFlag::LDS_1A1D) |
153 (TargetFlags & R600_InstFlag::LDS_1A2D));
156 bool R600InstrInfo::isLDSNoRetInstr(unsigned Opcode) const {
157 return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) == -1;
160 bool R600InstrInfo::isLDSRetInstr(unsigned Opcode) const {
161 return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) != -1;
164 bool R600InstrInfo::canBeConsideredALU(const MachineInstr *MI) const {
165 if (isALUInstr(MI->getOpcode()))
167 if (isVector(*MI) || isCubeOp(MI->getOpcode()))
169 switch (MI->getOpcode()) {
171 case AMDGPU::INTERP_PAIR_XY:
172 case AMDGPU::INTERP_PAIR_ZW:
173 case AMDGPU::INTERP_VEC_LOAD:
182 bool R600InstrInfo::isTransOnly(unsigned Opcode) const {
183 if (ST.hasCaymanISA())
185 return (get(Opcode).getSchedClass() == AMDGPU::Sched::TransALU);
188 bool R600InstrInfo::isTransOnly(const MachineInstr *MI) const {
189 return isTransOnly(MI->getOpcode());
192 bool R600InstrInfo::isVectorOnly(unsigned Opcode) const {
193 return (get(Opcode).getSchedClass() == AMDGPU::Sched::VecALU);
196 bool R600InstrInfo::isVectorOnly(const MachineInstr *MI) const {
197 return isVectorOnly(MI->getOpcode());
200 bool R600InstrInfo::isExport(unsigned Opcode) const {
201 return (get(Opcode).TSFlags & R600_InstFlag::IS_EXPORT);
204 bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
205 return ST.hasVertexCache() && IS_VTX(get(Opcode));
208 bool R600InstrInfo::usesVertexCache(const MachineInstr *MI) const {
209 const R600MachineFunctionInfo *MFI = MI->getParent()->getParent()->getInfo<R600MachineFunctionInfo>();
210 return MFI->ShaderType != ShaderType::COMPUTE && usesVertexCache(MI->getOpcode());
213 bool R600InstrInfo::usesTextureCache(unsigned Opcode) const {
214 return (!ST.hasVertexCache() && IS_VTX(get(Opcode))) || IS_TEX(get(Opcode));
217 bool R600InstrInfo::usesTextureCache(const MachineInstr *MI) const {
218 const R600MachineFunctionInfo *MFI = MI->getParent()->getParent()->getInfo<R600MachineFunctionInfo>();
219 return (MFI->ShaderType == ShaderType::COMPUTE && usesVertexCache(MI->getOpcode())) ||
220 usesTextureCache(MI->getOpcode());
223 bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const {
226 case AMDGPU::GROUP_BARRIER:
233 bool R600InstrInfo::usesAddressRegister(MachineInstr *MI) const {
234 return MI->findRegisterUseOperandIdx(AMDGPU::AR_X) != -1;
237 bool R600InstrInfo::definesAddressRegister(MachineInstr *MI) const {
238 return MI->findRegisterDefOperandIdx(AMDGPU::AR_X) != -1;
241 bool R600InstrInfo::readsLDSSrcReg(const MachineInstr *MI) const {
242 if (!isALUInstr(MI->getOpcode())) {
245 for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
246 E = MI->operands_end(); I != E; ++I) {
247 if (!I->isReg() || !I->isUse() ||
248 TargetRegisterInfo::isVirtualRegister(I->getReg()))
251 if (AMDGPU::R600_LDS_SRC_REGRegClass.contains(I->getReg()))
257 int R600InstrInfo::getSrcIdx(unsigned Opcode, unsigned SrcNum) const {
258 static const unsigned OpTable[] = {
259 AMDGPU::OpName::src0,
260 AMDGPU::OpName::src1,
265 return getOperandIdx(Opcode, OpTable[SrcNum]);
268 #define SRC_SEL_ROWS 11
269 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const {
270 static const unsigned SrcSelTable[SRC_SEL_ROWS][2] = {
271 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
272 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
273 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
274 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
275 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
276 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
277 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
278 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
279 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
280 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
281 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W}
284 for (unsigned i = 0; i < SRC_SEL_ROWS; ++i) {
285 if (getOperandIdx(Opcode, SrcSelTable[i][0]) == (int)SrcIdx) {
286 return getOperandIdx(Opcode, SrcSelTable[i][1]);
293 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
294 R600InstrInfo::getSrcs(MachineInstr *MI) const {
295 SmallVector<std::pair<MachineOperand *, int64_t>, 3> Result;
297 if (MI->getOpcode() == AMDGPU::DOT_4) {
298 static const unsigned OpTable[8][2] = {
299 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
300 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
301 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
302 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
303 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
304 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
305 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
306 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W},
309 for (unsigned j = 0; j < 8; j++) {
310 MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
312 unsigned Reg = MO.getReg();
313 if (Reg == AMDGPU::ALU_CONST) {
314 unsigned Sel = MI->getOperand(getOperandIdx(MI->getOpcode(),
315 OpTable[j][1])).getImm();
316 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Sel));
324 static const unsigned OpTable[3][2] = {
325 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
326 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
327 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
330 for (unsigned j = 0; j < 3; j++) {
331 int SrcIdx = getOperandIdx(MI->getOpcode(), OpTable[j][0]);
334 MachineOperand &MO = MI->getOperand(SrcIdx);
335 unsigned Reg = MI->getOperand(SrcIdx).getReg();
336 if (Reg == AMDGPU::ALU_CONST) {
337 unsigned Sel = MI->getOperand(
338 getOperandIdx(MI->getOpcode(), OpTable[j][1])).getImm();
339 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Sel));
342 if (Reg == AMDGPU::ALU_LITERAL_X) {
343 unsigned Imm = MI->getOperand(
344 getOperandIdx(MI->getOpcode(), AMDGPU::OpName::literal)).getImm();
345 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Imm));
348 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, 0));
353 std::vector<std::pair<int, unsigned> >
354 R600InstrInfo::ExtractSrcs(MachineInstr *MI,
355 const DenseMap<unsigned, unsigned> &PV,
356 unsigned &ConstCount) const {
358 const SmallVector<std::pair<MachineOperand *, int64_t>, 3> Srcs = getSrcs(MI);
359 const std::pair<int, unsigned> DummyPair(-1, 0);
360 std::vector<std::pair<int, unsigned> > Result;
362 for (unsigned n = Srcs.size(); i < n; ++i) {
363 unsigned Reg = Srcs[i].first->getReg();
364 unsigned Index = RI.getEncodingValue(Reg) & 0xff;
365 if (Reg == AMDGPU::OQAP) {
366 Result.push_back(std::pair<int, unsigned>(Index, 0));
368 if (PV.find(Reg) != PV.end()) {
369 // 255 is used to tells its a PS/PV reg
370 Result.push_back(std::pair<int, unsigned>(255, 0));
375 Result.push_back(DummyPair);
378 unsigned Chan = RI.getHWRegChan(Reg);
379 Result.push_back(std::pair<int, unsigned>(Index, Chan));
382 Result.push_back(DummyPair);
386 static std::vector<std::pair<int, unsigned> >
387 Swizzle(std::vector<std::pair<int, unsigned> > Src,
388 R600InstrInfo::BankSwizzle Swz) {
389 if (Src[0] == Src[1])
392 case R600InstrInfo::ALU_VEC_012_SCL_210:
394 case R600InstrInfo::ALU_VEC_021_SCL_122:
395 std::swap(Src[1], Src[2]);
397 case R600InstrInfo::ALU_VEC_102_SCL_221:
398 std::swap(Src[0], Src[1]);
400 case R600InstrInfo::ALU_VEC_120_SCL_212:
401 std::swap(Src[0], Src[1]);
402 std::swap(Src[0], Src[2]);
404 case R600InstrInfo::ALU_VEC_201:
405 std::swap(Src[0], Src[2]);
406 std::swap(Src[0], Src[1]);
408 case R600InstrInfo::ALU_VEC_210:
409 std::swap(Src[0], Src[2]);
416 getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) {
418 case R600InstrInfo::ALU_VEC_012_SCL_210: {
419 unsigned Cycles[3] = { 2, 1, 0};
422 case R600InstrInfo::ALU_VEC_021_SCL_122: {
423 unsigned Cycles[3] = { 1, 2, 2};
426 case R600InstrInfo::ALU_VEC_120_SCL_212: {
427 unsigned Cycles[3] = { 2, 1, 2};
430 case R600InstrInfo::ALU_VEC_102_SCL_221: {
431 unsigned Cycles[3] = { 2, 2, 1};
435 llvm_unreachable("Wrong Swizzle for Trans Slot");
440 /// returns how many MIs (whose inputs are represented by IGSrcs) can be packed
441 /// in the same Instruction Group while meeting read port limitations given a
442 /// Swz swizzle sequence.
443 unsigned R600InstrInfo::isLegalUpTo(
444 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
445 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
446 const std::vector<std::pair<int, unsigned> > &TransSrcs,
447 R600InstrInfo::BankSwizzle TransSwz) const {
449 memset(Vector, -1, sizeof(Vector));
450 for (unsigned i = 0, e = IGSrcs.size(); i < e; i++) {
451 const std::vector<std::pair<int, unsigned> > &Srcs =
452 Swizzle(IGSrcs[i], Swz[i]);
453 for (unsigned j = 0; j < 3; j++) {
454 const std::pair<int, unsigned> &Src = Srcs[j];
455 if (Src.first < 0 || Src.first == 255)
457 if (Src.first == GET_REG_INDEX(RI.getEncodingValue(AMDGPU::OQAP))) {
458 if (Swz[i] != R600InstrInfo::ALU_VEC_012_SCL_210 &&
459 Swz[i] != R600InstrInfo::ALU_VEC_021_SCL_122) {
460 // The value from output queue A (denoted by register OQAP) can
461 // only be fetched during the first cycle.
464 // OQAP does not count towards the normal read port restrictions
467 if (Vector[Src.second][j] < 0)
468 Vector[Src.second][j] = Src.first;
469 if (Vector[Src.second][j] != Src.first)
473 // Now check Trans Alu
474 for (unsigned i = 0, e = TransSrcs.size(); i < e; ++i) {
475 const std::pair<int, unsigned> &Src = TransSrcs[i];
476 unsigned Cycle = getTransSwizzle(TransSwz, i);
479 if (Src.first == 255)
481 if (Vector[Src.second][Cycle] < 0)
482 Vector[Src.second][Cycle] = Src.first;
483 if (Vector[Src.second][Cycle] != Src.first)
484 return IGSrcs.size() - 1;
486 return IGSrcs.size();
489 /// Given a swizzle sequence SwzCandidate and an index Idx, returns the next
490 /// (in lexicographic term) swizzle sequence assuming that all swizzles after
491 /// Idx can be skipped
493 NextPossibleSolution(
494 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
496 assert(Idx < SwzCandidate.size());
498 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210)
500 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) {
501 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210;
505 int NextSwizzle = SwzCandidate[ResetIdx] + 1;
506 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle;
510 /// Enumerate all possible Swizzle sequence to find one that can meet all
511 /// read port requirements.
512 bool R600InstrInfo::FindSwizzleForVectorSlot(
513 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
514 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
515 const std::vector<std::pair<int, unsigned> > &TransSrcs,
516 R600InstrInfo::BankSwizzle TransSwz) const {
517 unsigned ValidUpTo = 0;
519 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz);
520 if (ValidUpTo == IGSrcs.size())
522 } while (NextPossibleSolution(SwzCandidate, ValidUpTo));
526 /// Instructions in Trans slot can't read gpr at cycle 0 if they also read
527 /// a const, and can't read a gpr at cycle 1 if they read 2 const.
529 isConstCompatible(R600InstrInfo::BankSwizzle TransSwz,
530 const std::vector<std::pair<int, unsigned> > &TransOps,
531 unsigned ConstCount) {
532 // TransALU can't read 3 constants
535 for (unsigned i = 0, e = TransOps.size(); i < e; ++i) {
536 const std::pair<int, unsigned> &Src = TransOps[i];
537 unsigned Cycle = getTransSwizzle(TransSwz, i);
540 if (ConstCount > 0 && Cycle == 0)
542 if (ConstCount > 1 && Cycle == 1)
549 R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,
550 const DenseMap<unsigned, unsigned> &PV,
551 std::vector<BankSwizzle> &ValidSwizzle,
554 //Todo : support shared src0 - src1 operand
556 std::vector<std::vector<std::pair<int, unsigned> > > IGSrcs;
557 ValidSwizzle.clear();
559 BankSwizzle TransBS = ALU_VEC_012_SCL_210;
560 for (unsigned i = 0, e = IG.size(); i < e; ++i) {
561 IGSrcs.push_back(ExtractSrcs(IG[i], PV, ConstCount));
562 unsigned Op = getOperandIdx(IG[i]->getOpcode(),
563 AMDGPU::OpName::bank_swizzle);
564 ValidSwizzle.push_back( (R600InstrInfo::BankSwizzle)
565 IG[i]->getOperand(Op).getImm());
567 std::vector<std::pair<int, unsigned> > TransOps;
569 return FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps, TransBS);
571 TransOps = IGSrcs.back();
573 ValidSwizzle.pop_back();
575 static const R600InstrInfo::BankSwizzle TransSwz[] = {
581 for (unsigned i = 0; i < 4; i++) {
582 TransBS = TransSwz[i];
583 if (!isConstCompatible(TransBS, TransOps, ConstCount))
585 bool Result = FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps,
588 ValidSwizzle.push_back(TransBS);
598 R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts)
600 assert (Consts.size() <= 12 && "Too many operands in instructions group");
601 unsigned Pair1 = 0, Pair2 = 0;
602 for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
603 unsigned ReadConstHalf = Consts[i] & 2;
604 unsigned ReadConstIndex = Consts[i] & (~3);
605 unsigned ReadHalfConst = ReadConstIndex | ReadConstHalf;
607 Pair1 = ReadHalfConst;
610 if (Pair1 == ReadHalfConst)
613 Pair2 = ReadHalfConst;
616 if (Pair2 != ReadHalfConst)
623 R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs)
625 std::vector<unsigned> Consts;
626 SmallSet<int64_t, 4> Literals;
627 for (unsigned i = 0, n = MIs.size(); i < n; i++) {
628 MachineInstr *MI = MIs[i];
629 if (!isALUInstr(MI->getOpcode()))
632 const SmallVectorImpl<std::pair<MachineOperand *, int64_t> > &Srcs =
635 for (unsigned j = 0, e = Srcs.size(); j < e; j++) {
636 std::pair<MachineOperand *, unsigned> Src = Srcs[j];
637 if (Src.first->getReg() == AMDGPU::ALU_LITERAL_X)
638 Literals.insert(Src.second);
639 if (Literals.size() > 4)
641 if (Src.first->getReg() == AMDGPU::ALU_CONST)
642 Consts.push_back(Src.second);
643 if (AMDGPU::R600_KC0RegClass.contains(Src.first->getReg()) ||
644 AMDGPU::R600_KC1RegClass.contains(Src.first->getReg())) {
645 unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
646 unsigned Chan = RI.getHWRegChan(Src.first->getReg());
647 Consts.push_back((Index << 2) | Chan);
651 return fitsConstReadLimitations(Consts);
654 DFAPacketizer *R600InstrInfo::CreateTargetScheduleState(const TargetMachine *TM,
655 const ScheduleDAG *DAG) const {
656 const InstrItineraryData *II = TM->getInstrItineraryData();
657 return TM->getSubtarget<AMDGPUSubtarget>().createDFAPacketizer(II);
661 isPredicateSetter(unsigned Opcode) {
670 static MachineInstr *
671 findFirstPredicateSetterFrom(MachineBasicBlock &MBB,
672 MachineBasicBlock::iterator I) {
673 while (I != MBB.begin()) {
675 MachineInstr *MI = I;
676 if (isPredicateSetter(MI->getOpcode()))
684 bool isJump(unsigned Opcode) {
685 return Opcode == AMDGPU::JUMP || Opcode == AMDGPU::JUMP_COND;
688 static bool isBranch(unsigned Opcode) {
689 return Opcode == AMDGPU::BRANCH || Opcode == AMDGPU::BRANCH_COND_i32 ||
690 Opcode == AMDGPU::BRANCH_COND_f32;
694 R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
695 MachineBasicBlock *&TBB,
696 MachineBasicBlock *&FBB,
697 SmallVectorImpl<MachineOperand> &Cond,
698 bool AllowModify) const {
699 // Most of the following comes from the ARM implementation of AnalyzeBranch
701 // If the block has no terminators, it just falls into the block after it.
702 MachineBasicBlock::iterator I = MBB.end();
703 if (I == MBB.begin())
706 while (I->isDebugValue()) {
707 if (I == MBB.begin())
711 // AMDGPU::BRANCH* instructions are only available after isel and are not
713 if (isBranch(I->getOpcode()))
715 if (!isJump(static_cast<MachineInstr *>(I)->getOpcode())) {
719 // Remove successive JUMP
720 while (I != MBB.begin() && std::prev(I)->getOpcode() == AMDGPU::JUMP) {
721 MachineBasicBlock::iterator PriorI = std::prev(I);
723 I->removeFromParent();
726 MachineInstr *LastInst = I;
728 // If there is only one terminator instruction, process it.
729 unsigned LastOpc = LastInst->getOpcode();
730 if (I == MBB.begin() ||
731 !isJump(static_cast<MachineInstr *>(--I)->getOpcode())) {
732 if (LastOpc == AMDGPU::JUMP) {
733 TBB = LastInst->getOperand(0).getMBB();
735 } else if (LastOpc == AMDGPU::JUMP_COND) {
736 MachineInstr *predSet = I;
737 while (!isPredicateSetter(predSet->getOpcode())) {
740 TBB = LastInst->getOperand(0).getMBB();
741 Cond.push_back(predSet->getOperand(1));
742 Cond.push_back(predSet->getOperand(2));
743 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
746 return true; // Can't handle indirect branch.
749 // Get the instruction before it if it is a terminator.
750 MachineInstr *SecondLastInst = I;
751 unsigned SecondLastOpc = SecondLastInst->getOpcode();
753 // If the block ends with a B and a Bcc, handle it.
754 if (SecondLastOpc == AMDGPU::JUMP_COND && LastOpc == AMDGPU::JUMP) {
755 MachineInstr *predSet = --I;
756 while (!isPredicateSetter(predSet->getOpcode())) {
759 TBB = SecondLastInst->getOperand(0).getMBB();
760 FBB = LastInst->getOperand(0).getMBB();
761 Cond.push_back(predSet->getOperand(1));
762 Cond.push_back(predSet->getOperand(2));
763 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
767 // Otherwise, can't handle this.
771 int R600InstrInfo::getBranchInstr(const MachineOperand &op) const {
772 const MachineInstr *MI = op.getParent();
774 switch (MI->getDesc().OpInfo->RegClass) {
775 default: // FIXME: fallthrough??
776 case AMDGPU::GPRI32RegClassID: return AMDGPU::BRANCH_COND_i32;
777 case AMDGPU::GPRF32RegClassID: return AMDGPU::BRANCH_COND_f32;
782 MachineBasicBlock::iterator FindLastAluClause(MachineBasicBlock &MBB) {
783 for (MachineBasicBlock::reverse_iterator It = MBB.rbegin(), E = MBB.rend();
785 if (It->getOpcode() == AMDGPU::CF_ALU ||
786 It->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE)
787 return std::prev(It.base());
793 R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
794 MachineBasicBlock *TBB,
795 MachineBasicBlock *FBB,
796 const SmallVectorImpl<MachineOperand> &Cond,
798 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
802 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB);
805 MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
806 assert(PredSet && "No previous predicate !");
807 addFlag(PredSet, 0, MO_FLAG_PUSH);
808 PredSet->getOperand(2).setImm(Cond[1].getImm());
810 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
812 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
813 MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
814 if (CfAlu == MBB.end())
816 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
817 CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
821 MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
822 assert(PredSet && "No previous predicate !");
823 addFlag(PredSet, 0, MO_FLAG_PUSH);
824 PredSet->getOperand(2).setImm(Cond[1].getImm());
825 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
827 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
828 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB);
829 MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
830 if (CfAlu == MBB.end())
832 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
833 CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
839 R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
841 // Note : we leave PRED* instructions there.
842 // They may be needed when predicating instructions.
844 MachineBasicBlock::iterator I = MBB.end();
846 if (I == MBB.begin()) {
850 switch (I->getOpcode()) {
853 case AMDGPU::JUMP_COND: {
854 MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
855 clearFlag(predSet, 0, MO_FLAG_PUSH);
856 I->eraseFromParent();
857 MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
858 if (CfAlu == MBB.end())
860 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
861 CfAlu->setDesc(get(AMDGPU::CF_ALU));
865 I->eraseFromParent();
870 if (I == MBB.begin()) {
874 switch (I->getOpcode()) {
875 // FIXME: only one case??
878 case AMDGPU::JUMP_COND: {
879 MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
880 clearFlag(predSet, 0, MO_FLAG_PUSH);
881 I->eraseFromParent();
882 MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
883 if (CfAlu == MBB.end())
885 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
886 CfAlu->setDesc(get(AMDGPU::CF_ALU));
890 I->eraseFromParent();
897 R600InstrInfo::isPredicated(const MachineInstr *MI) const {
898 int idx = MI->findFirstPredOperandIdx();
902 unsigned Reg = MI->getOperand(idx).getReg();
904 default: return false;
905 case AMDGPU::PRED_SEL_ONE:
906 case AMDGPU::PRED_SEL_ZERO:
907 case AMDGPU::PREDICATE_BIT:
913 R600InstrInfo::isPredicable(MachineInstr *MI) const {
914 // XXX: KILL* instructions can be predicated, but they must be the last
915 // instruction in a clause, so this means any instructions after them cannot
916 // be predicated. Until we have proper support for instruction clauses in the
917 // backend, we will mark KILL* instructions as unpredicable.
919 if (MI->getOpcode() == AMDGPU::KILLGT) {
921 } else if (MI->getOpcode() == AMDGPU::CF_ALU) {
922 // If the clause start in the middle of MBB then the MBB has more
923 // than a single clause, unable to predicate several clauses.
924 if (MI->getParent()->begin() != MachineBasicBlock::iterator(MI))
926 // TODO: We don't support KC merging atm
927 if (MI->getOperand(3).getImm() != 0 || MI->getOperand(4).getImm() != 0)
930 } else if (isVector(*MI)) {
933 return AMDGPUInstrInfo::isPredicable(MI);
939 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
941 unsigned ExtraPredCycles,
942 const BranchProbability &Probability) const{
947 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
949 unsigned ExtraTCycles,
950 MachineBasicBlock &FMBB,
952 unsigned ExtraFCycles,
953 const BranchProbability &Probability) const {
958 R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
960 const BranchProbability &Probability)
966 R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
967 MachineBasicBlock &FMBB) const {
973 R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
974 MachineOperand &MO = Cond[1];
975 switch (MO.getImm()) {
976 case OPCODE_IS_ZERO_INT:
977 MO.setImm(OPCODE_IS_NOT_ZERO_INT);
979 case OPCODE_IS_NOT_ZERO_INT:
980 MO.setImm(OPCODE_IS_ZERO_INT);
983 MO.setImm(OPCODE_IS_NOT_ZERO);
985 case OPCODE_IS_NOT_ZERO:
986 MO.setImm(OPCODE_IS_ZERO);
992 MachineOperand &MO2 = Cond[2];
993 switch (MO2.getReg()) {
994 case AMDGPU::PRED_SEL_ZERO:
995 MO2.setReg(AMDGPU::PRED_SEL_ONE);
997 case AMDGPU::PRED_SEL_ONE:
998 MO2.setReg(AMDGPU::PRED_SEL_ZERO);
1007 R600InstrInfo::DefinesPredicate(MachineInstr *MI,
1008 std::vector<MachineOperand> &Pred) const {
1009 return isPredicateSetter(MI->getOpcode());
1014 R600InstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
1015 const SmallVectorImpl<MachineOperand> &Pred2) const {
1021 R600InstrInfo::PredicateInstruction(MachineInstr *MI,
1022 const SmallVectorImpl<MachineOperand> &Pred) const {
1023 int PIdx = MI->findFirstPredOperandIdx();
1025 if (MI->getOpcode() == AMDGPU::CF_ALU) {
1026 MI->getOperand(8).setImm(0);
1030 if (MI->getOpcode() == AMDGPU::DOT_4) {
1031 MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_X))
1032 .setReg(Pred[2].getReg());
1033 MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_Y))
1034 .setReg(Pred[2].getReg());
1035 MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_Z))
1036 .setReg(Pred[2].getReg());
1037 MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_W))
1038 .setReg(Pred[2].getReg());
1039 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1040 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
1045 MachineOperand &PMO = MI->getOperand(PIdx);
1046 PMO.setReg(Pred[2].getReg());
1047 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1048 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
1055 unsigned int R600InstrInfo::getPredicationCost(const MachineInstr *) const {
1059 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1060 const MachineInstr *MI,
1061 unsigned *PredCost) const {
1067 void R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved,
1068 const MachineFunction &MF) const {
1069 const AMDGPUFrameLowering *TFL =
1070 static_cast<const AMDGPUFrameLowering*>(TM.getFrameLowering());
1072 unsigned StackWidth = TFL->getStackWidth(MF);
1073 int End = getIndirectIndexEnd(MF);
1078 for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) {
1079 unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
1080 Reserved.set(SuperReg);
1081 for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
1082 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
1088 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex,
1089 unsigned Channel) const {
1090 // XXX: Remove when we support a stack width > 2
1091 assert(Channel == 0);
1095 const TargetRegisterClass *R600InstrInfo::getIndirectAddrRegClass() const {
1096 return &AMDGPU::R600_TReg32_XRegClass;
1099 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
1100 MachineBasicBlock::iterator I,
1101 unsigned ValueReg, unsigned Address,
1102 unsigned OffsetReg) const {
1103 unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
1104 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1105 AMDGPU::AR_X, OffsetReg);
1106 setImmOperand(MOVA, AMDGPU::OpName::write, 0);
1108 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1110 .addReg(AMDGPU::AR_X,
1111 RegState::Implicit | RegState::Kill);
1112 setImmOperand(Mov, AMDGPU::OpName::dst_rel, 1);
1116 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
1117 MachineBasicBlock::iterator I,
1118 unsigned ValueReg, unsigned Address,
1119 unsigned OffsetReg) const {
1120 unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
1121 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1124 setImmOperand(MOVA, AMDGPU::OpName::write, 0);
1125 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1128 .addReg(AMDGPU::AR_X,
1129 RegState::Implicit | RegState::Kill);
1130 setImmOperand(Mov, AMDGPU::OpName::src0_rel, 1);
1135 unsigned R600InstrInfo::getMaxAlusPerClause() const {
1139 MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB,
1140 MachineBasicBlock::iterator I,
1144 unsigned Src1Reg) const {
1145 MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
1149 MIB.addImm(0) // $update_exec_mask
1150 .addImm(0); // $update_predicate
1152 MIB.addImm(1) // $write
1154 .addImm(0) // $dst_rel
1155 .addImm(0) // $dst_clamp
1156 .addReg(Src0Reg) // $src0
1157 .addImm(0) // $src0_neg
1158 .addImm(0) // $src0_rel
1159 .addImm(0) // $src0_abs
1160 .addImm(-1); // $src0_sel
1163 MIB.addReg(Src1Reg) // $src1
1164 .addImm(0) // $src1_neg
1165 .addImm(0) // $src1_rel
1166 .addImm(0) // $src1_abs
1167 .addImm(-1); // $src1_sel
1170 //XXX: The r600g finalizer expects this to be 1, once we've moved the
1171 //scheduling to the backend, we can change the default to 0.
1172 MIB.addImm(1) // $last
1173 .addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
1174 .addImm(0) // $literal
1175 .addImm(0); // $bank_swizzle
1180 #define OPERAND_CASE(Label) \
1182 static const unsigned Ops[] = \
1192 static unsigned getSlotedOps(unsigned Op, unsigned Slot) {
1194 OPERAND_CASE(AMDGPU::OpName::update_exec_mask)
1195 OPERAND_CASE(AMDGPU::OpName::update_pred)
1196 OPERAND_CASE(AMDGPU::OpName::write)
1197 OPERAND_CASE(AMDGPU::OpName::omod)
1198 OPERAND_CASE(AMDGPU::OpName::dst_rel)
1199 OPERAND_CASE(AMDGPU::OpName::clamp)
1200 OPERAND_CASE(AMDGPU::OpName::src0)
1201 OPERAND_CASE(AMDGPU::OpName::src0_neg)
1202 OPERAND_CASE(AMDGPU::OpName::src0_rel)
1203 OPERAND_CASE(AMDGPU::OpName::src0_abs)
1204 OPERAND_CASE(AMDGPU::OpName::src0_sel)
1205 OPERAND_CASE(AMDGPU::OpName::src1)
1206 OPERAND_CASE(AMDGPU::OpName::src1_neg)
1207 OPERAND_CASE(AMDGPU::OpName::src1_rel)
1208 OPERAND_CASE(AMDGPU::OpName::src1_abs)
1209 OPERAND_CASE(AMDGPU::OpName::src1_sel)
1210 OPERAND_CASE(AMDGPU::OpName::pred_sel)
1212 llvm_unreachable("Wrong Operand");
1218 MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction(
1219 MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg)
1221 assert (MI->getOpcode() == AMDGPU::DOT_4 && "Not Implemented");
1223 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
1224 if (ST.getGeneration() <= AMDGPUSubtarget::R700)
1225 Opcode = AMDGPU::DOT4_r600;
1227 Opcode = AMDGPU::DOT4_eg;
1228 MachineBasicBlock::iterator I = MI;
1229 MachineOperand &Src0 = MI->getOperand(
1230 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src0, Slot)));
1231 MachineOperand &Src1 = MI->getOperand(
1232 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src1, Slot)));
1233 MachineInstr *MIB = buildDefaultInstruction(
1234 MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
1235 static const unsigned Operands[14] = {
1236 AMDGPU::OpName::update_exec_mask,
1237 AMDGPU::OpName::update_pred,
1238 AMDGPU::OpName::write,
1239 AMDGPU::OpName::omod,
1240 AMDGPU::OpName::dst_rel,
1241 AMDGPU::OpName::clamp,
1242 AMDGPU::OpName::src0_neg,
1243 AMDGPU::OpName::src0_rel,
1244 AMDGPU::OpName::src0_abs,
1245 AMDGPU::OpName::src0_sel,
1246 AMDGPU::OpName::src1_neg,
1247 AMDGPU::OpName::src1_rel,
1248 AMDGPU::OpName::src1_abs,
1249 AMDGPU::OpName::src1_sel,
1252 MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
1253 getSlotedOps(AMDGPU::OpName::pred_sel, Slot)));
1254 MIB->getOperand(getOperandIdx(Opcode, AMDGPU::OpName::pred_sel))
1255 .setReg(MO.getReg());
1257 for (unsigned i = 0; i < 14; i++) {
1258 MachineOperand &MO = MI->getOperand(
1259 getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));
1260 assert (MO.isImm());
1261 setImmOperand(MIB, Operands[i], MO.getImm());
1263 MIB->getOperand(20).setImm(0);
1267 MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,
1268 MachineBasicBlock::iterator I,
1270 uint64_t Imm) const {
1271 MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg,
1272 AMDGPU::ALU_LITERAL_X);
1273 setImmOperand(MovImm, AMDGPU::OpName::literal, Imm);
1277 MachineInstr *R600InstrInfo::buildMovInstr(MachineBasicBlock *MBB,
1278 MachineBasicBlock::iterator I,
1279 unsigned DstReg, unsigned SrcReg) const {
1280 return buildDefaultInstruction(*MBB, I, AMDGPU::MOV, DstReg, SrcReg);
1283 int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const {
1284 return getOperandIdx(MI.getOpcode(), Op);
1287 int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const {
1288 return AMDGPU::getNamedOperandIdx(Opcode, Op);
1291 void R600InstrInfo::setImmOperand(MachineInstr *MI, unsigned Op,
1292 int64_t Imm) const {
1293 int Idx = getOperandIdx(*MI, Op);
1294 assert(Idx != -1 && "Operand not supported for this instruction.");
1295 assert(MI->getOperand(Idx).isImm());
1296 MI->getOperand(Idx).setImm(Imm);
1299 //===----------------------------------------------------------------------===//
1300 // Instruction flag getters/setters
1301 //===----------------------------------------------------------------------===//
1303 bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const {
1304 return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
1307 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr *MI, unsigned SrcIdx,
1308 unsigned Flag) const {
1309 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1312 // If we pass something other than the default value of Flag to this
1313 // function, it means we are want to set a flag on an instruction
1314 // that uses native encoding.
1315 assert(HAS_NATIVE_OPERANDS(TargetFlags));
1316 bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3;
1319 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::clamp);
1322 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::write);
1324 case MO_FLAG_NOT_LAST:
1326 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::last);
1330 case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_neg); break;
1331 case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_neg); break;
1332 case 2: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src2_neg); break;
1337 assert(!IsOP3 && "Cannot set absolute value modifier for OP3 "
1341 case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_abs); break;
1342 case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_abs); break;
1350 assert(FlagIndex != -1 && "Flag not supported for this instruction");
1352 FlagIndex = GET_FLAG_OPERAND_IDX(TargetFlags);
1353 assert(FlagIndex != 0 &&
1354 "Instruction flags not supported for this instruction");
1357 MachineOperand &FlagOp = MI->getOperand(FlagIndex);
1358 assert(FlagOp.isImm());
1362 void R600InstrInfo::addFlag(MachineInstr *MI, unsigned Operand,
1363 unsigned Flag) const {
1364 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1368 if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1369 MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1370 if (Flag == MO_FLAG_NOT_LAST) {
1371 clearFlag(MI, Operand, MO_FLAG_LAST);
1372 } else if (Flag == MO_FLAG_MASK) {
1373 clearFlag(MI, Operand, Flag);
1378 MachineOperand &FlagOp = getFlagOp(MI, Operand);
1379 FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
1383 void R600InstrInfo::clearFlag(MachineInstr *MI, unsigned Operand,
1384 unsigned Flag) const {
1385 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1386 if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1387 MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1390 MachineOperand &FlagOp = getFlagOp(MI);
1391 unsigned InstFlags = FlagOp.getImm();
1392 InstFlags &= ~(Flag << (NUM_MO_FLAGS * Operand));
1393 FlagOp.setImm(InstFlags);