1 //===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief R600 Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
15 #include "R600InstrInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "R600Defines.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #define GET_INSTRINFO_CTOR
27 #include "AMDGPUGenDFAPacketizer.inc"
31 R600InstrInfo::R600InstrInfo(AMDGPUTargetMachine &tm)
32 : AMDGPUInstrInfo(tm),
34 ST(tm.getSubtarget<AMDGPUSubtarget>())
37 const R600RegisterInfo &R600InstrInfo::getRegisterInfo() const {
41 bool R600InstrInfo::isTrig(const MachineInstr &MI) const {
42 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
45 bool R600InstrInfo::isVector(const MachineInstr &MI) const {
46 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
50 R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
51 MachineBasicBlock::iterator MI, DebugLoc DL,
52 unsigned DestReg, unsigned SrcReg,
54 if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
55 && AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
56 for (unsigned I = 0; I < 4; I++) {
57 unsigned SubRegIndex = RI.getSubRegFromChannel(I);
58 buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
59 RI.getSubReg(DestReg, SubRegIndex),
60 RI.getSubReg(SrcReg, SubRegIndex))
62 RegState::Define | RegState::Implicit);
66 // We can't copy vec4 registers
67 assert(!AMDGPU::R600_Reg128RegClass.contains(DestReg)
68 && !AMDGPU::R600_Reg128RegClass.contains(SrcReg));
70 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
72 NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0))
77 MachineInstr * R600InstrInfo::getMovImmInstr(MachineFunction *MF,
78 unsigned DstReg, int64_t Imm) const {
79 MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc());
80 MachineInstrBuilder MIB(*MF, MI);
81 MIB.addReg(DstReg, RegState::Define);
82 MIB.addReg(AMDGPU::ALU_LITERAL_X);
84 MIB.addReg(0); // PREDICATE_BIT
89 unsigned R600InstrInfo::getIEQOpcode() const {
90 return AMDGPU::SETE_INT;
93 bool R600InstrInfo::isMov(unsigned Opcode) const {
97 default: return false;
99 case AMDGPU::MOV_IMM_F32:
100 case AMDGPU::MOV_IMM_I32:
105 // Some instructions act as place holders to emulate operations that the GPU
106 // hardware does automatically. This function can be used to check if
107 // an opcode falls into this category.
108 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const {
110 default: return false;
116 bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
118 default: return false;
122 bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
124 default: return false;
125 case AMDGPU::CUBE_r600_pseudo:
126 case AMDGPU::CUBE_r600_real:
127 case AMDGPU::CUBE_eg_pseudo:
128 case AMDGPU::CUBE_eg_real:
133 bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
134 unsigned TargetFlags = get(Opcode).TSFlags;
136 return (TargetFlags & R600_InstFlag::ALU_INST);
139 bool R600InstrInfo::isTransOnly(unsigned Opcode) const {
140 return (get(Opcode).TSFlags & R600_InstFlag::TRANS_ONLY);
143 bool R600InstrInfo::isTransOnly(const MachineInstr *MI) const {
144 return isTransOnly(MI->getOpcode());
147 bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
148 return ST.hasVertexCache() && IS_VTX(get(Opcode));
151 bool R600InstrInfo::usesVertexCache(const MachineInstr *MI) const {
152 const R600MachineFunctionInfo *MFI = MI->getParent()->getParent()->getInfo<R600MachineFunctionInfo>();
153 return MFI->ShaderType != ShaderType::COMPUTE && usesVertexCache(MI->getOpcode());
156 bool R600InstrInfo::usesTextureCache(unsigned Opcode) const {
157 return (!ST.hasVertexCache() && IS_VTX(get(Opcode))) || IS_TEX(get(Opcode));
160 bool R600InstrInfo::usesTextureCache(const MachineInstr *MI) const {
161 const R600MachineFunctionInfo *MFI = MI->getParent()->getParent()->getInfo<R600MachineFunctionInfo>();
162 return (MFI->ShaderType == ShaderType::COMPUTE && usesVertexCache(MI->getOpcode())) ||
163 usesTextureCache(MI->getOpcode());
166 bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const {
169 case AMDGPU::GROUP_BARRIER:
176 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
177 R600InstrInfo::getSrcs(MachineInstr *MI) const {
178 SmallVector<std::pair<MachineOperand *, int64_t>, 3> Result;
180 if (MI->getOpcode() == AMDGPU::DOT_4) {
181 static const unsigned OpTable[8][2] = {
182 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
183 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
184 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
185 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
186 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
187 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
188 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
189 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W},
192 for (unsigned j = 0; j < 8; j++) {
193 MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
195 unsigned Reg = MO.getReg();
196 if (Reg == AMDGPU::ALU_CONST) {
197 unsigned Sel = MI->getOperand(getOperandIdx(MI->getOpcode(),
198 OpTable[j][1])).getImm();
199 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Sel));
207 static const unsigned OpTable[3][2] = {
208 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
209 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
210 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
213 for (unsigned j = 0; j < 3; j++) {
214 int SrcIdx = getOperandIdx(MI->getOpcode(), OpTable[j][0]);
217 MachineOperand &MO = MI->getOperand(SrcIdx);
218 unsigned Reg = MI->getOperand(SrcIdx).getReg();
219 if (Reg == AMDGPU::ALU_CONST) {
220 unsigned Sel = MI->getOperand(
221 getOperandIdx(MI->getOpcode(), OpTable[j][1])).getImm();
222 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Sel));
225 if (Reg == AMDGPU::ALU_LITERAL_X) {
226 unsigned Imm = MI->getOperand(
227 getOperandIdx(MI->getOpcode(), AMDGPU::OpName::literal)).getImm();
228 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Imm));
231 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, 0));
236 std::vector<std::pair<int, unsigned> >
237 R600InstrInfo::ExtractSrcs(MachineInstr *MI,
238 const DenseMap<unsigned, unsigned> &PV)
240 const SmallVector<std::pair<MachineOperand *, int64_t>, 3> Srcs = getSrcs(MI);
241 const std::pair<int, unsigned> DummyPair(-1, 0);
242 std::vector<std::pair<int, unsigned> > Result;
244 for (unsigned n = Srcs.size(); i < n; ++i) {
245 unsigned Reg = Srcs[i].first->getReg();
246 unsigned Index = RI.getEncodingValue(Reg) & 0xff;
247 unsigned Chan = RI.getHWRegChan(Reg);
249 Result.push_back(DummyPair);
252 if (PV.find(Reg) != PV.end()) {
253 Result.push_back(DummyPair);
256 Result.push_back(std::pair<int, unsigned>(Index, Chan));
259 Result.push_back(DummyPair);
263 static std::vector<std::pair<int, unsigned> >
264 Swizzle(std::vector<std::pair<int, unsigned> > Src,
265 R600InstrInfo::BankSwizzle Swz) {
267 case R600InstrInfo::ALU_VEC_012:
269 case R600InstrInfo::ALU_VEC_021:
270 std::swap(Src[1], Src[2]);
272 case R600InstrInfo::ALU_VEC_102:
273 std::swap(Src[0], Src[1]);
275 case R600InstrInfo::ALU_VEC_120:
276 std::swap(Src[0], Src[1]);
277 std::swap(Src[0], Src[2]);
279 case R600InstrInfo::ALU_VEC_201:
280 std::swap(Src[0], Src[2]);
281 std::swap(Src[0], Src[1]);
283 case R600InstrInfo::ALU_VEC_210:
284 std::swap(Src[0], Src[2]);
291 isLegal(const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
292 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
293 unsigned CheckedSize) {
295 memset(Vector, -1, sizeof(Vector));
296 for (unsigned i = 0; i < CheckedSize; i++) {
297 const std::vector<std::pair<int, unsigned> > &Srcs =
298 Swizzle(IGSrcs[i], Swz[i]);
299 for (unsigned j = 0; j < 3; j++) {
300 const std::pair<int, unsigned> &Src = Srcs[j];
303 if (Vector[Src.second][j] < 0)
304 Vector[Src.second][j] = Src.first;
305 if (Vector[Src.second][j] != Src.first)
312 static bool recursiveFitsFPLimitation(
313 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
314 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
315 unsigned Depth = 0) {
316 if (!isLegal(IGSrcs, SwzCandidate, Depth))
318 if (IGSrcs.size() == Depth)
320 unsigned i = SwzCandidate[Depth];
322 SwzCandidate[Depth] = (R600InstrInfo::BankSwizzle) i;
323 if (recursiveFitsFPLimitation(IGSrcs, SwzCandidate, Depth + 1))
326 SwzCandidate[Depth] = R600InstrInfo::ALU_VEC_012;
331 R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,
332 const DenseMap<unsigned, unsigned> &PV,
333 std::vector<BankSwizzle> &ValidSwizzle)
335 //Todo : support shared src0 - src1 operand
337 std::vector<std::vector<std::pair<int, unsigned> > > IGSrcs;
338 ValidSwizzle.clear();
339 for (unsigned i = 0, e = IG.size(); i < e; ++i) {
340 IGSrcs.push_back(ExtractSrcs(IG[i], PV));
341 unsigned Op = getOperandIdx(IG[i]->getOpcode(),
342 AMDGPU::OpName::bank_swizzle);
343 ValidSwizzle.push_back( (R600InstrInfo::BankSwizzle)
344 IG[i]->getOperand(Op).getImm());
346 bool Result = recursiveFitsFPLimitation(IGSrcs, ValidSwizzle);
354 R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts)
356 assert (Consts.size() <= 12 && "Too many operands in instructions group");
357 unsigned Pair1 = 0, Pair2 = 0;
358 for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
359 unsigned ReadConstHalf = Consts[i] & 2;
360 unsigned ReadConstIndex = Consts[i] & (~3);
361 unsigned ReadHalfConst = ReadConstIndex | ReadConstHalf;
363 Pair1 = ReadHalfConst;
366 if (Pair1 == ReadHalfConst)
369 Pair2 = ReadHalfConst;
372 if (Pair2 != ReadHalfConst)
379 R600InstrInfo::canBundle(const std::vector<MachineInstr *> &MIs) const {
380 std::vector<unsigned> Consts;
381 for (unsigned i = 0, n = MIs.size(); i < n; i++) {
382 MachineInstr *MI = MIs[i];
383 if (!isALUInstr(MI->getOpcode()))
386 const SmallVector<std::pair<MachineOperand *, int64_t>, 3> &Srcs =
389 for (unsigned j = 0, e = Srcs.size(); j < e; j++) {
390 std::pair<MachineOperand *, unsigned> Src = Srcs[j];
391 if (Src.first->getReg() == AMDGPU::ALU_CONST)
392 Consts.push_back(Src.second);
393 if (AMDGPU::R600_KC0RegClass.contains(Src.first->getReg()) ||
394 AMDGPU::R600_KC1RegClass.contains(Src.first->getReg())) {
395 unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
396 unsigned Chan = RI.getHWRegChan(Src.first->getReg());
397 Consts.push_back((Index << 2) | Chan);
401 return fitsConstReadLimitations(Consts);
404 DFAPacketizer *R600InstrInfo::CreateTargetScheduleState(const TargetMachine *TM,
405 const ScheduleDAG *DAG) const {
406 const InstrItineraryData *II = TM->getInstrItineraryData();
407 return TM->getSubtarget<AMDGPUSubtarget>().createDFAPacketizer(II);
411 isPredicateSetter(unsigned Opcode) {
420 static MachineInstr *
421 findFirstPredicateSetterFrom(MachineBasicBlock &MBB,
422 MachineBasicBlock::iterator I) {
423 while (I != MBB.begin()) {
425 MachineInstr *MI = I;
426 if (isPredicateSetter(MI->getOpcode()))
434 bool isJump(unsigned Opcode) {
435 return Opcode == AMDGPU::JUMP || Opcode == AMDGPU::JUMP_COND;
439 R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
440 MachineBasicBlock *&TBB,
441 MachineBasicBlock *&FBB,
442 SmallVectorImpl<MachineOperand> &Cond,
443 bool AllowModify) const {
444 // Most of the following comes from the ARM implementation of AnalyzeBranch
446 // If the block has no terminators, it just falls into the block after it.
447 MachineBasicBlock::iterator I = MBB.end();
448 if (I == MBB.begin())
451 while (I->isDebugValue()) {
452 if (I == MBB.begin())
456 if (!isJump(static_cast<MachineInstr *>(I)->getOpcode())) {
460 // Get the last instruction in the block.
461 MachineInstr *LastInst = I;
463 // If there is only one terminator instruction, process it.
464 unsigned LastOpc = LastInst->getOpcode();
465 if (I == MBB.begin() ||
466 !isJump(static_cast<MachineInstr *>(--I)->getOpcode())) {
467 if (LastOpc == AMDGPU::JUMP) {
468 TBB = LastInst->getOperand(0).getMBB();
470 } else if (LastOpc == AMDGPU::JUMP_COND) {
471 MachineInstr *predSet = I;
472 while (!isPredicateSetter(predSet->getOpcode())) {
475 TBB = LastInst->getOperand(0).getMBB();
476 Cond.push_back(predSet->getOperand(1));
477 Cond.push_back(predSet->getOperand(2));
478 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
481 return true; // Can't handle indirect branch.
484 // Get the instruction before it if it is a terminator.
485 MachineInstr *SecondLastInst = I;
486 unsigned SecondLastOpc = SecondLastInst->getOpcode();
488 // If the block ends with a B and a Bcc, handle it.
489 if (SecondLastOpc == AMDGPU::JUMP_COND && LastOpc == AMDGPU::JUMP) {
490 MachineInstr *predSet = --I;
491 while (!isPredicateSetter(predSet->getOpcode())) {
494 TBB = SecondLastInst->getOperand(0).getMBB();
495 FBB = LastInst->getOperand(0).getMBB();
496 Cond.push_back(predSet->getOperand(1));
497 Cond.push_back(predSet->getOperand(2));
498 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
502 // Otherwise, can't handle this.
506 int R600InstrInfo::getBranchInstr(const MachineOperand &op) const {
507 const MachineInstr *MI = op.getParent();
509 switch (MI->getDesc().OpInfo->RegClass) {
510 default: // FIXME: fallthrough??
511 case AMDGPU::GPRI32RegClassID: return AMDGPU::BRANCH_COND_i32;
512 case AMDGPU::GPRF32RegClassID: return AMDGPU::BRANCH_COND_f32;
517 R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
518 MachineBasicBlock *TBB,
519 MachineBasicBlock *FBB,
520 const SmallVectorImpl<MachineOperand> &Cond,
522 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
526 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB);
529 MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
530 assert(PredSet && "No previous predicate !");
531 addFlag(PredSet, 0, MO_FLAG_PUSH);
532 PredSet->getOperand(2).setImm(Cond[1].getImm());
534 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
536 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
540 MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
541 assert(PredSet && "No previous predicate !");
542 addFlag(PredSet, 0, MO_FLAG_PUSH);
543 PredSet->getOperand(2).setImm(Cond[1].getImm());
544 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
546 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
547 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB);
553 R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
555 // Note : we leave PRED* instructions there.
556 // They may be needed when predicating instructions.
558 MachineBasicBlock::iterator I = MBB.end();
560 if (I == MBB.begin()) {
564 switch (I->getOpcode()) {
567 case AMDGPU::JUMP_COND: {
568 MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
569 clearFlag(predSet, 0, MO_FLAG_PUSH);
570 I->eraseFromParent();
574 I->eraseFromParent();
579 if (I == MBB.begin()) {
583 switch (I->getOpcode()) {
584 // FIXME: only one case??
587 case AMDGPU::JUMP_COND: {
588 MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
589 clearFlag(predSet, 0, MO_FLAG_PUSH);
590 I->eraseFromParent();
594 I->eraseFromParent();
601 R600InstrInfo::isPredicated(const MachineInstr *MI) const {
602 int idx = MI->findFirstPredOperandIdx();
606 unsigned Reg = MI->getOperand(idx).getReg();
608 default: return false;
609 case AMDGPU::PRED_SEL_ONE:
610 case AMDGPU::PRED_SEL_ZERO:
611 case AMDGPU::PREDICATE_BIT:
617 R600InstrInfo::isPredicable(MachineInstr *MI) const {
618 // XXX: KILL* instructions can be predicated, but they must be the last
619 // instruction in a clause, so this means any instructions after them cannot
620 // be predicated. Until we have proper support for instruction clauses in the
621 // backend, we will mark KILL* instructions as unpredicable.
623 if (MI->getOpcode() == AMDGPU::KILLGT) {
625 } else if (isVector(*MI)) {
628 return AMDGPUInstrInfo::isPredicable(MI);
634 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
636 unsigned ExtraPredCycles,
637 const BranchProbability &Probability) const{
642 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
644 unsigned ExtraTCycles,
645 MachineBasicBlock &FMBB,
647 unsigned ExtraFCycles,
648 const BranchProbability &Probability) const {
653 R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
655 const BranchProbability &Probability)
661 R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
662 MachineBasicBlock &FMBB) const {
668 R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
669 MachineOperand &MO = Cond[1];
670 switch (MO.getImm()) {
671 case OPCODE_IS_ZERO_INT:
672 MO.setImm(OPCODE_IS_NOT_ZERO_INT);
674 case OPCODE_IS_NOT_ZERO_INT:
675 MO.setImm(OPCODE_IS_ZERO_INT);
678 MO.setImm(OPCODE_IS_NOT_ZERO);
680 case OPCODE_IS_NOT_ZERO:
681 MO.setImm(OPCODE_IS_ZERO);
687 MachineOperand &MO2 = Cond[2];
688 switch (MO2.getReg()) {
689 case AMDGPU::PRED_SEL_ZERO:
690 MO2.setReg(AMDGPU::PRED_SEL_ONE);
692 case AMDGPU::PRED_SEL_ONE:
693 MO2.setReg(AMDGPU::PRED_SEL_ZERO);
702 R600InstrInfo::DefinesPredicate(MachineInstr *MI,
703 std::vector<MachineOperand> &Pred) const {
704 return isPredicateSetter(MI->getOpcode());
709 R600InstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
710 const SmallVectorImpl<MachineOperand> &Pred2) const {
716 R600InstrInfo::PredicateInstruction(MachineInstr *MI,
717 const SmallVectorImpl<MachineOperand> &Pred) const {
718 int PIdx = MI->findFirstPredOperandIdx();
721 MachineOperand &PMO = MI->getOperand(PIdx);
722 PMO.setReg(Pred[2].getReg());
723 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
724 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
731 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
732 const MachineInstr *MI,
733 unsigned *PredCost) const {
739 int R600InstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
740 const MachineRegisterInfo &MRI = MF.getRegInfo();
741 const MachineFrameInfo *MFI = MF.getFrameInfo();
744 if (MFI->getNumObjects() == 0) {
748 if (MRI.livein_empty()) {
752 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
753 LE = MRI.livein_end();
755 Offset = std::max(Offset,
756 GET_REG_INDEX(RI.getEncodingValue(LI->first)));
762 int R600InstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
764 const MachineFrameInfo *MFI = MF.getFrameInfo();
766 // Variable sized objects are not supported
767 assert(!MFI->hasVarSizedObjects());
769 if (MFI->getNumObjects() == 0) {
773 Offset = TM.getFrameLowering()->getFrameIndexOffset(MF, -1);
775 return getIndirectIndexBegin(MF) + Offset;
778 std::vector<unsigned> R600InstrInfo::getIndirectReservedRegs(
779 const MachineFunction &MF) const {
780 const AMDGPUFrameLowering *TFL =
781 static_cast<const AMDGPUFrameLowering*>(TM.getFrameLowering());
782 std::vector<unsigned> Regs;
784 unsigned StackWidth = TFL->getStackWidth(MF);
785 int End = getIndirectIndexEnd(MF);
791 for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) {
792 unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
793 Regs.push_back(SuperReg);
794 for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
795 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
802 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex,
803 unsigned Channel) const {
804 // XXX: Remove when we support a stack width > 2
805 assert(Channel == 0);
809 const TargetRegisterClass * R600InstrInfo::getIndirectAddrStoreRegClass(
810 unsigned SourceReg) const {
811 return &AMDGPU::R600_TReg32RegClass;
814 const TargetRegisterClass *R600InstrInfo::getIndirectAddrLoadRegClass() const {
815 return &AMDGPU::TRegMemRegClass;
818 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
819 MachineBasicBlock::iterator I,
820 unsigned ValueReg, unsigned Address,
821 unsigned OffsetReg) const {
822 unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
823 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
824 AMDGPU::AR_X, OffsetReg);
825 setImmOperand(MOVA, AMDGPU::OpName::write, 0);
827 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
829 .addReg(AMDGPU::AR_X,
830 RegState::Implicit | RegState::Kill);
831 setImmOperand(Mov, AMDGPU::OpName::dst_rel, 1);
835 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
836 MachineBasicBlock::iterator I,
837 unsigned ValueReg, unsigned Address,
838 unsigned OffsetReg) const {
839 unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
840 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
843 setImmOperand(MOVA, AMDGPU::OpName::write, 0);
844 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
847 .addReg(AMDGPU::AR_X,
848 RegState::Implicit | RegState::Kill);
849 setImmOperand(Mov, AMDGPU::OpName::src0_rel, 1);
854 const TargetRegisterClass *R600InstrInfo::getSuperIndirectRegClass() const {
855 return &AMDGPU::IndirectRegRegClass;
858 unsigned R600InstrInfo::getMaxAlusPerClause() const {
862 MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB,
863 MachineBasicBlock::iterator I,
867 unsigned Src1Reg) const {
868 MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
872 MIB.addImm(0) // $update_exec_mask
873 .addImm(0); // $update_predicate
875 MIB.addImm(1) // $write
877 .addImm(0) // $dst_rel
878 .addImm(0) // $dst_clamp
879 .addReg(Src0Reg) // $src0
880 .addImm(0) // $src0_neg
881 .addImm(0) // $src0_rel
882 .addImm(0) // $src0_abs
883 .addImm(-1); // $src0_sel
886 MIB.addReg(Src1Reg) // $src1
887 .addImm(0) // $src1_neg
888 .addImm(0) // $src1_rel
889 .addImm(0) // $src1_abs
890 .addImm(-1); // $src1_sel
893 //XXX: The r600g finalizer expects this to be 1, once we've moved the
894 //scheduling to the backend, we can change the default to 0.
895 MIB.addImm(1) // $last
896 .addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
897 .addImm(0) // $literal
898 .addImm(0); // $bank_swizzle
903 #define OPERAND_CASE(Label) \
905 static const unsigned Ops[] = \
915 static unsigned getSlotedOps(unsigned Op, unsigned Slot) {
917 OPERAND_CASE(AMDGPU::OpName::update_exec_mask)
918 OPERAND_CASE(AMDGPU::OpName::update_pred)
919 OPERAND_CASE(AMDGPU::OpName::write)
920 OPERAND_CASE(AMDGPU::OpName::omod)
921 OPERAND_CASE(AMDGPU::OpName::dst_rel)
922 OPERAND_CASE(AMDGPU::OpName::clamp)
923 OPERAND_CASE(AMDGPU::OpName::src0)
924 OPERAND_CASE(AMDGPU::OpName::src0_neg)
925 OPERAND_CASE(AMDGPU::OpName::src0_rel)
926 OPERAND_CASE(AMDGPU::OpName::src0_abs)
927 OPERAND_CASE(AMDGPU::OpName::src0_sel)
928 OPERAND_CASE(AMDGPU::OpName::src1)
929 OPERAND_CASE(AMDGPU::OpName::src1_neg)
930 OPERAND_CASE(AMDGPU::OpName::src1_rel)
931 OPERAND_CASE(AMDGPU::OpName::src1_abs)
932 OPERAND_CASE(AMDGPU::OpName::src1_sel)
933 OPERAND_CASE(AMDGPU::OpName::pred_sel)
935 llvm_unreachable("Wrong Operand");
941 MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction(
942 MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg)
944 assert (MI->getOpcode() == AMDGPU::DOT_4 && "Not Implemented");
946 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
947 if (ST.getGeneration() <= AMDGPUSubtarget::R700)
948 Opcode = AMDGPU::DOT4_r600;
950 Opcode = AMDGPU::DOT4_eg;
951 MachineBasicBlock::iterator I = MI;
952 MachineOperand &Src0 = MI->getOperand(
953 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src0, Slot)));
954 MachineOperand &Src1 = MI->getOperand(
955 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src1, Slot)));
956 MachineInstr *MIB = buildDefaultInstruction(
957 MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
958 static const unsigned Operands[14] = {
959 AMDGPU::OpName::update_exec_mask,
960 AMDGPU::OpName::update_pred,
961 AMDGPU::OpName::write,
962 AMDGPU::OpName::omod,
963 AMDGPU::OpName::dst_rel,
964 AMDGPU::OpName::clamp,
965 AMDGPU::OpName::src0_neg,
966 AMDGPU::OpName::src0_rel,
967 AMDGPU::OpName::src0_abs,
968 AMDGPU::OpName::src0_sel,
969 AMDGPU::OpName::src1_neg,
970 AMDGPU::OpName::src1_rel,
971 AMDGPU::OpName::src1_abs,
972 AMDGPU::OpName::src1_sel,
975 for (unsigned i = 0; i < 14; i++) {
976 MachineOperand &MO = MI->getOperand(
977 getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));
979 setImmOperand(MIB, Operands[i], MO.getImm());
981 MIB->getOperand(20).setImm(0);
985 MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,
986 MachineBasicBlock::iterator I,
988 uint64_t Imm) const {
989 MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg,
990 AMDGPU::ALU_LITERAL_X);
991 setImmOperand(MovImm, AMDGPU::OpName::literal, Imm);
995 int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const {
996 return getOperandIdx(MI.getOpcode(), Op);
999 int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const {
1000 return AMDGPU::getNamedOperandIdx(Opcode, Op);
1003 void R600InstrInfo::setImmOperand(MachineInstr *MI, unsigned Op,
1004 int64_t Imm) const {
1005 int Idx = getOperandIdx(*MI, Op);
1006 assert(Idx != -1 && "Operand not supported for this instruction.");
1007 assert(MI->getOperand(Idx).isImm());
1008 MI->getOperand(Idx).setImm(Imm);
1011 //===----------------------------------------------------------------------===//
1012 // Instruction flag getters/setters
1013 //===----------------------------------------------------------------------===//
1015 bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const {
1016 return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
1019 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr *MI, unsigned SrcIdx,
1020 unsigned Flag) const {
1021 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1024 // If we pass something other than the default value of Flag to this
1025 // function, it means we are want to set a flag on an instruction
1026 // that uses native encoding.
1027 assert(HAS_NATIVE_OPERANDS(TargetFlags));
1028 bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3;
1031 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::clamp);
1034 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::write);
1036 case MO_FLAG_NOT_LAST:
1038 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::last);
1042 case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_neg); break;
1043 case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_neg); break;
1044 case 2: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src2_neg); break;
1049 assert(!IsOP3 && "Cannot set absolute value modifier for OP3 "
1053 case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_abs); break;
1054 case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_abs); break;
1062 assert(FlagIndex != -1 && "Flag not supported for this instruction");
1064 FlagIndex = GET_FLAG_OPERAND_IDX(TargetFlags);
1065 assert(FlagIndex != 0 &&
1066 "Instruction flags not supported for this instruction");
1069 MachineOperand &FlagOp = MI->getOperand(FlagIndex);
1070 assert(FlagOp.isImm());
1074 void R600InstrInfo::addFlag(MachineInstr *MI, unsigned Operand,
1075 unsigned Flag) const {
1076 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1080 if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1081 MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1082 if (Flag == MO_FLAG_NOT_LAST) {
1083 clearFlag(MI, Operand, MO_FLAG_LAST);
1084 } else if (Flag == MO_FLAG_MASK) {
1085 clearFlag(MI, Operand, Flag);
1090 MachineOperand &FlagOp = getFlagOp(MI, Operand);
1091 FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
1095 void R600InstrInfo::clearFlag(MachineInstr *MI, unsigned Operand,
1096 unsigned Flag) const {
1097 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1098 if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1099 MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1102 MachineOperand &FlagOp = getFlagOp(MI);
1103 unsigned InstFlags = FlagOp.getImm();
1104 InstFlags &= ~(Flag << (NUM_MO_FLAGS * Operand));
1105 FlagOp.setImm(InstFlags);