1 //===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief R600 Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
15 #include "R600InstrInfo.h"
16 #include "AMDGPUSubtarget.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "R600Defines.h"
19 #include "R600RegisterInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #define GET_INSTRINFO_CTOR
23 #include "AMDGPUGenDFAPacketizer.inc"
27 R600InstrInfo::R600InstrInfo(AMDGPUTargetMachine &tm)
28 : AMDGPUInstrInfo(tm),
32 const R600RegisterInfo &R600InstrInfo::getRegisterInfo() const {
36 bool R600InstrInfo::isTrig(const MachineInstr &MI) const {
37 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
40 bool R600InstrInfo::isVector(const MachineInstr &MI) const {
41 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
45 R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
46 MachineBasicBlock::iterator MI, DebugLoc DL,
47 unsigned DestReg, unsigned SrcReg,
49 if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
50 && AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
51 for (unsigned I = 0; I < 4; I++) {
52 unsigned SubRegIndex = RI.getSubRegFromChannel(I);
53 buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
54 RI.getSubReg(DestReg, SubRegIndex),
55 RI.getSubReg(SrcReg, SubRegIndex))
57 RegState::Define | RegState::Implicit);
61 // We can't copy vec4 registers
62 assert(!AMDGPU::R600_Reg128RegClass.contains(DestReg)
63 && !AMDGPU::R600_Reg128RegClass.contains(SrcReg));
65 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
67 NewMI->getOperand(getOperandIdx(*NewMI, R600Operands::SRC0))
72 MachineInstr * R600InstrInfo::getMovImmInstr(MachineFunction *MF,
73 unsigned DstReg, int64_t Imm) const {
74 MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc());
75 MachineInstrBuilder MIB(*MF, MI);
76 MIB.addReg(DstReg, RegState::Define);
77 MIB.addReg(AMDGPU::ALU_LITERAL_X);
79 MIB.addReg(0); // PREDICATE_BIT
84 unsigned R600InstrInfo::getIEQOpcode() const {
85 return AMDGPU::SETE_INT;
88 bool R600InstrInfo::isMov(unsigned Opcode) const {
92 default: return false;
94 case AMDGPU::MOV_IMM_F32:
95 case AMDGPU::MOV_IMM_I32:
100 // Some instructions act as place holders to emulate operations that the GPU
101 // hardware does automatically. This function can be used to check if
102 // an opcode falls into this category.
103 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const {
105 default: return false;
111 bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
113 default: return false;
114 case AMDGPU::DOT4_r600_pseudo:
115 case AMDGPU::DOT4_eg_pseudo:
120 bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
122 default: return false;
123 case AMDGPU::CUBE_r600_pseudo:
124 case AMDGPU::CUBE_r600_real:
125 case AMDGPU::CUBE_eg_pseudo:
126 case AMDGPU::CUBE_eg_real:
131 bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
132 unsigned TargetFlags = get(Opcode).TSFlags;
134 return ((TargetFlags & R600_InstFlag::OP1) |
135 (TargetFlags & R600_InstFlag::OP2) |
136 (TargetFlags & R600_InstFlag::OP3));
139 DFAPacketizer *R600InstrInfo::CreateTargetScheduleState(const TargetMachine *TM,
140 const ScheduleDAG *DAG) const {
141 const InstrItineraryData *II = TM->getInstrItineraryData();
142 return TM->getSubtarget<AMDGPUSubtarget>().createDFAPacketizer(II);
146 isPredicateSetter(unsigned Opcode) {
155 static MachineInstr *
156 findFirstPredicateSetterFrom(MachineBasicBlock &MBB,
157 MachineBasicBlock::iterator I) {
158 while (I != MBB.begin()) {
160 MachineInstr *MI = I;
161 if (isPredicateSetter(MI->getOpcode()))
169 R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
170 MachineBasicBlock *&TBB,
171 MachineBasicBlock *&FBB,
172 SmallVectorImpl<MachineOperand> &Cond,
173 bool AllowModify) const {
174 // Most of the following comes from the ARM implementation of AnalyzeBranch
176 // If the block has no terminators, it just falls into the block after it.
177 MachineBasicBlock::iterator I = MBB.end();
178 if (I == MBB.begin())
181 while (I->isDebugValue()) {
182 if (I == MBB.begin())
186 if (static_cast<MachineInstr *>(I)->getOpcode() != AMDGPU::JUMP) {
190 // Get the last instruction in the block.
191 MachineInstr *LastInst = I;
193 // If there is only one terminator instruction, process it.
194 unsigned LastOpc = LastInst->getOpcode();
195 if (I == MBB.begin() ||
196 static_cast<MachineInstr *>(--I)->getOpcode() != AMDGPU::JUMP) {
197 if (LastOpc == AMDGPU::JUMP) {
198 if(!isPredicated(LastInst)) {
199 TBB = LastInst->getOperand(0).getMBB();
202 MachineInstr *predSet = I;
203 while (!isPredicateSetter(predSet->getOpcode())) {
206 TBB = LastInst->getOperand(0).getMBB();
207 Cond.push_back(predSet->getOperand(1));
208 Cond.push_back(predSet->getOperand(2));
209 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
213 return true; // Can't handle indirect branch.
216 // Get the instruction before it if it is a terminator.
217 MachineInstr *SecondLastInst = I;
218 unsigned SecondLastOpc = SecondLastInst->getOpcode();
220 // If the block ends with a B and a Bcc, handle it.
221 if (SecondLastOpc == AMDGPU::JUMP &&
222 isPredicated(SecondLastInst) &&
223 LastOpc == AMDGPU::JUMP &&
224 !isPredicated(LastInst)) {
225 MachineInstr *predSet = --I;
226 while (!isPredicateSetter(predSet->getOpcode())) {
229 TBB = SecondLastInst->getOperand(0).getMBB();
230 FBB = LastInst->getOperand(0).getMBB();
231 Cond.push_back(predSet->getOperand(1));
232 Cond.push_back(predSet->getOperand(2));
233 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
237 // Otherwise, can't handle this.
241 int R600InstrInfo::getBranchInstr(const MachineOperand &op) const {
242 const MachineInstr *MI = op.getParent();
244 switch (MI->getDesc().OpInfo->RegClass) {
245 default: // FIXME: fallthrough??
246 case AMDGPU::GPRI32RegClassID: return AMDGPU::BRANCH_COND_i32;
247 case AMDGPU::GPRF32RegClassID: return AMDGPU::BRANCH_COND_f32;
252 R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
253 MachineBasicBlock *TBB,
254 MachineBasicBlock *FBB,
255 const SmallVectorImpl<MachineOperand> &Cond,
257 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
261 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB).addReg(0);
264 MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
265 assert(PredSet && "No previous predicate !");
266 addFlag(PredSet, 0, MO_FLAG_PUSH);
267 PredSet->getOperand(2).setImm(Cond[1].getImm());
269 BuildMI(&MBB, DL, get(AMDGPU::JUMP))
271 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
275 MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
276 assert(PredSet && "No previous predicate !");
277 addFlag(PredSet, 0, MO_FLAG_PUSH);
278 PredSet->getOperand(2).setImm(Cond[1].getImm());
279 BuildMI(&MBB, DL, get(AMDGPU::JUMP))
281 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
282 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB).addReg(0);
288 R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
290 // Note : we leave PRED* instructions there.
291 // They may be needed when predicating instructions.
293 MachineBasicBlock::iterator I = MBB.end();
295 if (I == MBB.begin()) {
299 switch (I->getOpcode()) {
303 if (isPredicated(I)) {
304 MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
305 clearFlag(predSet, 0, MO_FLAG_PUSH);
307 I->eraseFromParent();
312 if (I == MBB.begin()) {
316 switch (I->getOpcode()) {
317 // FIXME: only one case??
321 if (isPredicated(I)) {
322 MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
323 clearFlag(predSet, 0, MO_FLAG_PUSH);
325 I->eraseFromParent();
332 R600InstrInfo::isPredicated(const MachineInstr *MI) const {
333 int idx = MI->findFirstPredOperandIdx();
337 unsigned Reg = MI->getOperand(idx).getReg();
339 default: return false;
340 case AMDGPU::PRED_SEL_ONE:
341 case AMDGPU::PRED_SEL_ZERO:
342 case AMDGPU::PREDICATE_BIT:
348 R600InstrInfo::isPredicable(MachineInstr *MI) const {
349 // XXX: KILL* instructions can be predicated, but they must be the last
350 // instruction in a clause, so this means any instructions after them cannot
351 // be predicated. Until we have proper support for instruction clauses in the
352 // backend, we will mark KILL* instructions as unpredicable.
354 if (MI->getOpcode() == AMDGPU::KILLGT) {
357 return AMDGPUInstrInfo::isPredicable(MI);
363 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
365 unsigned ExtraPredCycles,
366 const BranchProbability &Probability) const{
371 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
373 unsigned ExtraTCycles,
374 MachineBasicBlock &FMBB,
376 unsigned ExtraFCycles,
377 const BranchProbability &Probability) const {
382 R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
384 const BranchProbability &Probability)
390 R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
391 MachineBasicBlock &FMBB) const {
397 R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
398 MachineOperand &MO = Cond[1];
399 switch (MO.getImm()) {
400 case OPCODE_IS_ZERO_INT:
401 MO.setImm(OPCODE_IS_NOT_ZERO_INT);
403 case OPCODE_IS_NOT_ZERO_INT:
404 MO.setImm(OPCODE_IS_ZERO_INT);
407 MO.setImm(OPCODE_IS_NOT_ZERO);
409 case OPCODE_IS_NOT_ZERO:
410 MO.setImm(OPCODE_IS_ZERO);
416 MachineOperand &MO2 = Cond[2];
417 switch (MO2.getReg()) {
418 case AMDGPU::PRED_SEL_ZERO:
419 MO2.setReg(AMDGPU::PRED_SEL_ONE);
421 case AMDGPU::PRED_SEL_ONE:
422 MO2.setReg(AMDGPU::PRED_SEL_ZERO);
431 R600InstrInfo::DefinesPredicate(MachineInstr *MI,
432 std::vector<MachineOperand> &Pred) const {
433 return isPredicateSetter(MI->getOpcode());
438 R600InstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
439 const SmallVectorImpl<MachineOperand> &Pred2) const {
445 R600InstrInfo::PredicateInstruction(MachineInstr *MI,
446 const SmallVectorImpl<MachineOperand> &Pred) const {
447 int PIdx = MI->findFirstPredOperandIdx();
450 MachineOperand &PMO = MI->getOperand(PIdx);
451 PMO.setReg(Pred[2].getReg());
452 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
453 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
460 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
461 const MachineInstr *MI,
462 unsigned *PredCost) const {
468 MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB,
469 MachineBasicBlock::iterator I,
473 unsigned Src1Reg) const {
474 MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
478 MIB.addImm(0) // $update_exec_mask
479 .addImm(0); // $update_predicate
481 MIB.addImm(1) // $write
483 .addImm(0) // $dst_rel
484 .addImm(0) // $dst_clamp
485 .addReg(Src0Reg) // $src0
486 .addImm(0) // $src0_neg
487 .addImm(0) // $src0_rel
488 .addImm(0) // $src0_abs
489 .addImm(-1); // $src0_sel
492 MIB.addReg(Src1Reg) // $src1
493 .addImm(0) // $src1_neg
494 .addImm(0) // $src1_rel
495 .addImm(0) // $src1_abs
496 .addImm(-1); // $src1_sel
499 //XXX: The r600g finalizer expects this to be 1, once we've moved the
500 //scheduling to the backend, we can change the default to 0.
501 MIB.addImm(1) // $last
502 .addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
503 .addImm(0); // $literal
508 MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,
509 MachineBasicBlock::iterator I,
511 uint64_t Imm) const {
512 MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg,
513 AMDGPU::ALU_LITERAL_X);
514 setImmOperand(MovImm, R600Operands::IMM, Imm);
518 int R600InstrInfo::getOperandIdx(const MachineInstr &MI,
519 R600Operands::Ops Op) const {
520 return getOperandIdx(MI.getOpcode(), Op);
523 int R600InstrInfo::getOperandIdx(unsigned Opcode,
524 R600Operands::Ops Op) const {
525 unsigned TargetFlags = get(Opcode).TSFlags;
528 if (!HAS_NATIVE_OPERANDS(TargetFlags)) {
530 case R600Operands::DST: return 0;
531 case R600Operands::SRC0: return 1;
532 case R600Operands::SRC1: return 2;
533 case R600Operands::SRC2: return 3;
535 assert(!"Unknown operand type for instruction");
540 if (TargetFlags & R600_InstFlag::OP1) {
542 } else if (TargetFlags & R600_InstFlag::OP2) {
545 assert((TargetFlags & R600_InstFlag::OP3) && "OP1, OP2, or OP3 not defined "
546 "for this instruction");
550 return R600Operands::ALUOpTable[OpTableIdx][Op];
553 void R600InstrInfo::setImmOperand(MachineInstr *MI, R600Operands::Ops Op,
555 int Idx = getOperandIdx(*MI, Op);
556 assert(Idx != -1 && "Operand not supported for this instruction.");
557 assert(MI->getOperand(Idx).isImm());
558 MI->getOperand(Idx).setImm(Imm);
561 //===----------------------------------------------------------------------===//
562 // Instruction flag getters/setters
563 //===----------------------------------------------------------------------===//
565 bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const {
566 return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
569 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr *MI, unsigned SrcIdx,
570 unsigned Flag) const {
571 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
574 // If we pass something other than the default value of Flag to this
575 // function, it means we are want to set a flag on an instruction
576 // that uses native encoding.
577 assert(HAS_NATIVE_OPERANDS(TargetFlags));
578 bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3;
581 FlagIndex = getOperandIdx(*MI, R600Operands::CLAMP);
584 FlagIndex = getOperandIdx(*MI, R600Operands::WRITE);
586 case MO_FLAG_NOT_LAST:
588 FlagIndex = getOperandIdx(*MI, R600Operands::LAST);
592 case 0: FlagIndex = getOperandIdx(*MI, R600Operands::SRC0_NEG); break;
593 case 1: FlagIndex = getOperandIdx(*MI, R600Operands::SRC1_NEG); break;
594 case 2: FlagIndex = getOperandIdx(*MI, R600Operands::SRC2_NEG); break;
599 assert(!IsOP3 && "Cannot set absolute value modifier for OP3 "
603 case 0: FlagIndex = getOperandIdx(*MI, R600Operands::SRC0_ABS); break;
604 case 1: FlagIndex = getOperandIdx(*MI, R600Operands::SRC1_ABS); break;
612 assert(FlagIndex != -1 && "Flag not supported for this instruction");
614 FlagIndex = GET_FLAG_OPERAND_IDX(TargetFlags);
615 assert(FlagIndex != 0 &&
616 "Instruction flags not supported for this instruction");
619 MachineOperand &FlagOp = MI->getOperand(FlagIndex);
620 assert(FlagOp.isImm());
624 void R600InstrInfo::addFlag(MachineInstr *MI, unsigned Operand,
625 unsigned Flag) const {
626 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
630 if (HAS_NATIVE_OPERANDS(TargetFlags)) {
631 MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
632 if (Flag == MO_FLAG_NOT_LAST) {
633 clearFlag(MI, Operand, MO_FLAG_LAST);
634 } else if (Flag == MO_FLAG_MASK) {
635 clearFlag(MI, Operand, Flag);
640 MachineOperand &FlagOp = getFlagOp(MI, Operand);
641 FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
645 void R600InstrInfo::clearFlag(MachineInstr *MI, unsigned Operand,
646 unsigned Flag) const {
647 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
648 if (HAS_NATIVE_OPERANDS(TargetFlags)) {
649 MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
652 MachineOperand &FlagOp = getFlagOp(MI);
653 unsigned InstFlags = FlagOp.getImm();
654 InstFlags &= ~(Flag << (NUM_MO_FLAGS * Operand));
655 FlagOp.setImm(InstFlags);