1 //===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief R600 Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
15 #include "R600InstrInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "R600Defines.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #define GET_INSTRINFO_CTOR
27 #include "AMDGPUGenDFAPacketizer.inc"
31 R600InstrInfo::R600InstrInfo(AMDGPUTargetMachine &tm)
32 : AMDGPUInstrInfo(tm),
34 ST(tm.getSubtarget<AMDGPUSubtarget>())
37 const R600RegisterInfo &R600InstrInfo::getRegisterInfo() const {
41 bool R600InstrInfo::isTrig(const MachineInstr &MI) const {
42 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
45 bool R600InstrInfo::isVector(const MachineInstr &MI) const {
46 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
50 R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
51 MachineBasicBlock::iterator MI, DebugLoc DL,
52 unsigned DestReg, unsigned SrcReg,
54 unsigned VectorComponents = 0;
55 if (AMDGPU::R600_Reg128RegClass.contains(DestReg) &&
56 AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
58 } else if(AMDGPU::R600_Reg64RegClass.contains(DestReg) &&
59 AMDGPU::R600_Reg64RegClass.contains(SrcReg)) {
63 if (VectorComponents > 0) {
64 for (unsigned I = 0; I < VectorComponents; I++) {
65 unsigned SubRegIndex = RI.getSubRegFromChannel(I);
66 buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
67 RI.getSubReg(DestReg, SubRegIndex),
68 RI.getSubReg(SrcReg, SubRegIndex))
70 RegState::Define | RegState::Implicit);
73 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
75 NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0))
80 unsigned R600InstrInfo::getIEQOpcode() const {
81 return AMDGPU::SETE_INT;
84 bool R600InstrInfo::isMov(unsigned Opcode) const {
88 default: return false;
90 case AMDGPU::MOV_IMM_F32:
91 case AMDGPU::MOV_IMM_I32:
96 // Some instructions act as place holders to emulate operations that the GPU
97 // hardware does automatically. This function can be used to check if
98 // an opcode falls into this category.
99 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const {
101 default: return false;
107 bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
111 bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
113 default: return false;
114 case AMDGPU::CUBE_r600_pseudo:
115 case AMDGPU::CUBE_r600_real:
116 case AMDGPU::CUBE_eg_pseudo:
117 case AMDGPU::CUBE_eg_real:
122 bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
123 unsigned TargetFlags = get(Opcode).TSFlags;
125 return (TargetFlags & R600_InstFlag::ALU_INST);
128 bool R600InstrInfo::hasInstrModifiers(unsigned Opcode) const {
129 unsigned TargetFlags = get(Opcode).TSFlags;
131 return ((TargetFlags & R600_InstFlag::OP1) |
132 (TargetFlags & R600_InstFlag::OP2) |
133 (TargetFlags & R600_InstFlag::OP3));
136 bool R600InstrInfo::isLDSInstr(unsigned Opcode) const {
137 unsigned TargetFlags = get(Opcode).TSFlags;
139 return ((TargetFlags & R600_InstFlag::LDS_1A) |
140 (TargetFlags & R600_InstFlag::LDS_1A1D) |
141 (TargetFlags & R600_InstFlag::LDS_1A2D));
144 bool R600InstrInfo::canBeConsideredALU(const MachineInstr *MI) const {
145 if (isALUInstr(MI->getOpcode()))
147 if (isVector(*MI) || isCubeOp(MI->getOpcode()))
149 switch (MI->getOpcode()) {
151 case AMDGPU::INTERP_PAIR_XY:
152 case AMDGPU::INTERP_PAIR_ZW:
153 case AMDGPU::INTERP_VEC_LOAD:
162 bool R600InstrInfo::isTransOnly(unsigned Opcode) const {
163 if (ST.hasCaymanISA())
165 return (get(Opcode).getSchedClass() == AMDGPU::Sched::TransALU);
168 bool R600InstrInfo::isTransOnly(const MachineInstr *MI) const {
169 return isTransOnly(MI->getOpcode());
172 bool R600InstrInfo::isVectorOnly(unsigned Opcode) const {
173 return (get(Opcode).getSchedClass() == AMDGPU::Sched::VecALU);
176 bool R600InstrInfo::isVectorOnly(const MachineInstr *MI) const {
177 return isVectorOnly(MI->getOpcode());
180 bool R600InstrInfo::isExport(unsigned Opcode) const {
181 return (get(Opcode).TSFlags & R600_InstFlag::IS_EXPORT);
184 bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
185 return ST.hasVertexCache() && IS_VTX(get(Opcode));
188 bool R600InstrInfo::usesVertexCache(const MachineInstr *MI) const {
189 const R600MachineFunctionInfo *MFI = MI->getParent()->getParent()->getInfo<R600MachineFunctionInfo>();
190 return MFI->ShaderType != ShaderType::COMPUTE && usesVertexCache(MI->getOpcode());
193 bool R600InstrInfo::usesTextureCache(unsigned Opcode) const {
194 return (!ST.hasVertexCache() && IS_VTX(get(Opcode))) || IS_TEX(get(Opcode));
197 bool R600InstrInfo::usesTextureCache(const MachineInstr *MI) const {
198 const R600MachineFunctionInfo *MFI = MI->getParent()->getParent()->getInfo<R600MachineFunctionInfo>();
199 return (MFI->ShaderType == ShaderType::COMPUTE && usesVertexCache(MI->getOpcode())) ||
200 usesTextureCache(MI->getOpcode());
203 bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const {
206 case AMDGPU::GROUP_BARRIER:
213 bool R600InstrInfo::usesAddressRegister(MachineInstr *MI) const {
214 return MI->findRegisterUseOperandIdx(AMDGPU::AR_X) != -1;
217 bool R600InstrInfo::definesAddressRegister(MachineInstr *MI) const {
218 return MI->findRegisterDefOperandIdx(AMDGPU::AR_X) != -1;
221 bool R600InstrInfo::readsLDSSrcReg(const MachineInstr *MI) const {
222 if (!isALUInstr(MI->getOpcode())) {
225 for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
226 E = MI->operands_end(); I != E; ++I) {
227 if (!I->isReg() || !I->isUse() ||
228 TargetRegisterInfo::isVirtualRegister(I->getReg()))
231 if (AMDGPU::R600_LDS_SRC_REGRegClass.contains(I->getReg()))
237 int R600InstrInfo::getSrcIdx(unsigned Opcode, unsigned SrcNum) const {
238 static const unsigned OpTable[] = {
239 AMDGPU::OpName::src0,
240 AMDGPU::OpName::src1,
245 return getOperandIdx(Opcode, OpTable[SrcNum]);
248 #define SRC_SEL_ROWS 11
249 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const {
250 static const unsigned SrcSelTable[SRC_SEL_ROWS][2] = {
251 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
252 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
253 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
254 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
255 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
256 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
257 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
258 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
259 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
260 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
261 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W}
264 for (unsigned i = 0; i < SRC_SEL_ROWS; ++i) {
265 if (getOperandIdx(Opcode, SrcSelTable[i][0]) == (int)SrcIdx) {
266 return getOperandIdx(Opcode, SrcSelTable[i][1]);
273 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
274 R600InstrInfo::getSrcs(MachineInstr *MI) const {
275 SmallVector<std::pair<MachineOperand *, int64_t>, 3> Result;
277 if (MI->getOpcode() == AMDGPU::DOT_4) {
278 static const unsigned OpTable[8][2] = {
279 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
280 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
281 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
282 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
283 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
284 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
285 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
286 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W},
289 for (unsigned j = 0; j < 8; j++) {
290 MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
292 unsigned Reg = MO.getReg();
293 if (Reg == AMDGPU::ALU_CONST) {
294 unsigned Sel = MI->getOperand(getOperandIdx(MI->getOpcode(),
295 OpTable[j][1])).getImm();
296 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Sel));
304 static const unsigned OpTable[3][2] = {
305 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
306 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
307 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
310 for (unsigned j = 0; j < 3; j++) {
311 int SrcIdx = getOperandIdx(MI->getOpcode(), OpTable[j][0]);
314 MachineOperand &MO = MI->getOperand(SrcIdx);
315 unsigned Reg = MI->getOperand(SrcIdx).getReg();
316 if (Reg == AMDGPU::ALU_CONST) {
317 unsigned Sel = MI->getOperand(
318 getOperandIdx(MI->getOpcode(), OpTable[j][1])).getImm();
319 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Sel));
322 if (Reg == AMDGPU::ALU_LITERAL_X) {
323 unsigned Imm = MI->getOperand(
324 getOperandIdx(MI->getOpcode(), AMDGPU::OpName::literal)).getImm();
325 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Imm));
328 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, 0));
333 std::vector<std::pair<int, unsigned> >
334 R600InstrInfo::ExtractSrcs(MachineInstr *MI,
335 const DenseMap<unsigned, unsigned> &PV,
336 unsigned &ConstCount) const {
338 const SmallVector<std::pair<MachineOperand *, int64_t>, 3> Srcs = getSrcs(MI);
339 const std::pair<int, unsigned> DummyPair(-1, 0);
340 std::vector<std::pair<int, unsigned> > Result;
342 for (unsigned n = Srcs.size(); i < n; ++i) {
343 unsigned Reg = Srcs[i].first->getReg();
344 unsigned Index = RI.getEncodingValue(Reg) & 0xff;
345 if (Reg == AMDGPU::OQAP) {
346 Result.push_back(std::pair<int, unsigned>(Index, 0));
348 if (PV.find(Reg) != PV.end()) {
349 // 255 is used to tells its a PS/PV reg
350 Result.push_back(std::pair<int, unsigned>(255, 0));
355 Result.push_back(DummyPair);
358 unsigned Chan = RI.getHWRegChan(Reg);
359 Result.push_back(std::pair<int, unsigned>(Index, Chan));
362 Result.push_back(DummyPair);
366 static std::vector<std::pair<int, unsigned> >
367 Swizzle(std::vector<std::pair<int, unsigned> > Src,
368 R600InstrInfo::BankSwizzle Swz) {
369 if (Src[0] == Src[1])
372 case R600InstrInfo::ALU_VEC_012_SCL_210:
374 case R600InstrInfo::ALU_VEC_021_SCL_122:
375 std::swap(Src[1], Src[2]);
377 case R600InstrInfo::ALU_VEC_102_SCL_221:
378 std::swap(Src[0], Src[1]);
380 case R600InstrInfo::ALU_VEC_120_SCL_212:
381 std::swap(Src[0], Src[1]);
382 std::swap(Src[0], Src[2]);
384 case R600InstrInfo::ALU_VEC_201:
385 std::swap(Src[0], Src[2]);
386 std::swap(Src[0], Src[1]);
388 case R600InstrInfo::ALU_VEC_210:
389 std::swap(Src[0], Src[2]);
396 getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) {
398 case R600InstrInfo::ALU_VEC_012_SCL_210: {
399 unsigned Cycles[3] = { 2, 1, 0};
402 case R600InstrInfo::ALU_VEC_021_SCL_122: {
403 unsigned Cycles[3] = { 1, 2, 2};
406 case R600InstrInfo::ALU_VEC_120_SCL_212: {
407 unsigned Cycles[3] = { 2, 1, 2};
410 case R600InstrInfo::ALU_VEC_102_SCL_221: {
411 unsigned Cycles[3] = { 2, 2, 1};
415 llvm_unreachable("Wrong Swizzle for Trans Slot");
420 /// returns how many MIs (whose inputs are represented by IGSrcs) can be packed
421 /// in the same Instruction Group while meeting read port limitations given a
422 /// Swz swizzle sequence.
423 unsigned R600InstrInfo::isLegalUpTo(
424 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
425 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
426 const std::vector<std::pair<int, unsigned> > &TransSrcs,
427 R600InstrInfo::BankSwizzle TransSwz) const {
429 memset(Vector, -1, sizeof(Vector));
430 for (unsigned i = 0, e = IGSrcs.size(); i < e; i++) {
431 const std::vector<std::pair<int, unsigned> > &Srcs =
432 Swizzle(IGSrcs[i], Swz[i]);
433 for (unsigned j = 0; j < 3; j++) {
434 const std::pair<int, unsigned> &Src = Srcs[j];
435 if (Src.first < 0 || Src.first == 255)
437 if (Src.first == GET_REG_INDEX(RI.getEncodingValue(AMDGPU::OQAP))) {
438 if (Swz[i] != R600InstrInfo::ALU_VEC_012_SCL_210 &&
439 Swz[i] != R600InstrInfo::ALU_VEC_021_SCL_122) {
440 // The value from output queue A (denoted by register OQAP) can
441 // only be fetched during the first cycle.
444 // OQAP does not count towards the normal read port restrictions
447 if (Vector[Src.second][j] < 0)
448 Vector[Src.second][j] = Src.first;
449 if (Vector[Src.second][j] != Src.first)
453 // Now check Trans Alu
454 for (unsigned i = 0, e = TransSrcs.size(); i < e; ++i) {
455 const std::pair<int, unsigned> &Src = TransSrcs[i];
456 unsigned Cycle = getTransSwizzle(TransSwz, i);
459 if (Src.first == 255)
461 if (Vector[Src.second][Cycle] < 0)
462 Vector[Src.second][Cycle] = Src.first;
463 if (Vector[Src.second][Cycle] != Src.first)
464 return IGSrcs.size() - 1;
466 return IGSrcs.size();
469 /// Given a swizzle sequence SwzCandidate and an index Idx, returns the next
470 /// (in lexicographic term) swizzle sequence assuming that all swizzles after
471 /// Idx can be skipped
473 NextPossibleSolution(
474 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
476 assert(Idx < SwzCandidate.size());
478 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210)
480 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) {
481 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210;
485 int NextSwizzle = SwzCandidate[ResetIdx] + 1;
486 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle;
490 /// Enumerate all possible Swizzle sequence to find one that can meet all
491 /// read port requirements.
492 bool R600InstrInfo::FindSwizzleForVectorSlot(
493 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
494 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
495 const std::vector<std::pair<int, unsigned> > &TransSrcs,
496 R600InstrInfo::BankSwizzle TransSwz) const {
497 unsigned ValidUpTo = 0;
499 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz);
500 if (ValidUpTo == IGSrcs.size())
502 } while (NextPossibleSolution(SwzCandidate, ValidUpTo));
506 /// Instructions in Trans slot can't read gpr at cycle 0 if they also read
507 /// a const, and can't read a gpr at cycle 1 if they read 2 const.
509 isConstCompatible(R600InstrInfo::BankSwizzle TransSwz,
510 const std::vector<std::pair<int, unsigned> > &TransOps,
511 unsigned ConstCount) {
512 // TransALU can't read 3 constants
515 for (unsigned i = 0, e = TransOps.size(); i < e; ++i) {
516 const std::pair<int, unsigned> &Src = TransOps[i];
517 unsigned Cycle = getTransSwizzle(TransSwz, i);
520 if (ConstCount > 0 && Cycle == 0)
522 if (ConstCount > 1 && Cycle == 1)
529 R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,
530 const DenseMap<unsigned, unsigned> &PV,
531 std::vector<BankSwizzle> &ValidSwizzle,
534 //Todo : support shared src0 - src1 operand
536 std::vector<std::vector<std::pair<int, unsigned> > > IGSrcs;
537 ValidSwizzle.clear();
539 BankSwizzle TransBS = ALU_VEC_012_SCL_210;
540 for (unsigned i = 0, e = IG.size(); i < e; ++i) {
541 IGSrcs.push_back(ExtractSrcs(IG[i], PV, ConstCount));
542 unsigned Op = getOperandIdx(IG[i]->getOpcode(),
543 AMDGPU::OpName::bank_swizzle);
544 ValidSwizzle.push_back( (R600InstrInfo::BankSwizzle)
545 IG[i]->getOperand(Op).getImm());
547 std::vector<std::pair<int, unsigned> > TransOps;
549 return FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps, TransBS);
551 TransOps = IGSrcs.back();
553 ValidSwizzle.pop_back();
555 static const R600InstrInfo::BankSwizzle TransSwz[] = {
561 for (unsigned i = 0; i < 4; i++) {
562 TransBS = TransSwz[i];
563 if (!isConstCompatible(TransBS, TransOps, ConstCount))
565 bool Result = FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps,
568 ValidSwizzle.push_back(TransBS);
578 R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts)
580 assert (Consts.size() <= 12 && "Too many operands in instructions group");
581 unsigned Pair1 = 0, Pair2 = 0;
582 for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
583 unsigned ReadConstHalf = Consts[i] & 2;
584 unsigned ReadConstIndex = Consts[i] & (~3);
585 unsigned ReadHalfConst = ReadConstIndex | ReadConstHalf;
587 Pair1 = ReadHalfConst;
590 if (Pair1 == ReadHalfConst)
593 Pair2 = ReadHalfConst;
596 if (Pair2 != ReadHalfConst)
603 R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs)
605 std::vector<unsigned> Consts;
606 SmallSet<int64_t, 4> Literals;
607 for (unsigned i = 0, n = MIs.size(); i < n; i++) {
608 MachineInstr *MI = MIs[i];
609 if (!isALUInstr(MI->getOpcode()))
612 const SmallVectorImpl<std::pair<MachineOperand *, int64_t> > &Srcs =
615 for (unsigned j = 0, e = Srcs.size(); j < e; j++) {
616 std::pair<MachineOperand *, unsigned> Src = Srcs[j];
617 if (Src.first->getReg() == AMDGPU::ALU_LITERAL_X)
618 Literals.insert(Src.second);
619 if (Literals.size() > 4)
621 if (Src.first->getReg() == AMDGPU::ALU_CONST)
622 Consts.push_back(Src.second);
623 if (AMDGPU::R600_KC0RegClass.contains(Src.first->getReg()) ||
624 AMDGPU::R600_KC1RegClass.contains(Src.first->getReg())) {
625 unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
626 unsigned Chan = RI.getHWRegChan(Src.first->getReg());
627 Consts.push_back((Index << 2) | Chan);
631 return fitsConstReadLimitations(Consts);
634 DFAPacketizer *R600InstrInfo::CreateTargetScheduleState(const TargetMachine *TM,
635 const ScheduleDAG *DAG) const {
636 const InstrItineraryData *II = TM->getInstrItineraryData();
637 return TM->getSubtarget<AMDGPUSubtarget>().createDFAPacketizer(II);
641 isPredicateSetter(unsigned Opcode) {
650 static MachineInstr *
651 findFirstPredicateSetterFrom(MachineBasicBlock &MBB,
652 MachineBasicBlock::iterator I) {
653 while (I != MBB.begin()) {
655 MachineInstr *MI = I;
656 if (isPredicateSetter(MI->getOpcode()))
664 bool isJump(unsigned Opcode) {
665 return Opcode == AMDGPU::JUMP || Opcode == AMDGPU::JUMP_COND;
668 static bool isBranch(unsigned Opcode) {
669 return Opcode == AMDGPU::BRANCH || Opcode == AMDGPU::BRANCH_COND_i32 ||
670 Opcode == AMDGPU::BRANCH_COND_f32;
674 R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
675 MachineBasicBlock *&TBB,
676 MachineBasicBlock *&FBB,
677 SmallVectorImpl<MachineOperand> &Cond,
678 bool AllowModify) const {
679 // Most of the following comes from the ARM implementation of AnalyzeBranch
681 // If the block has no terminators, it just falls into the block after it.
682 MachineBasicBlock::iterator I = MBB.end();
683 if (I == MBB.begin())
686 while (I->isDebugValue()) {
687 if (I == MBB.begin())
691 // AMDGPU::BRANCH* instructions are only available after isel and are not
693 if (isBranch(I->getOpcode()))
695 if (!isJump(static_cast<MachineInstr *>(I)->getOpcode())) {
699 // Get the last instruction in the block.
700 MachineInstr *LastInst = I;
702 // If there is only one terminator instruction, process it.
703 unsigned LastOpc = LastInst->getOpcode();
704 if (I == MBB.begin() ||
705 !isJump(static_cast<MachineInstr *>(--I)->getOpcode())) {
706 if (LastOpc == AMDGPU::JUMP) {
707 TBB = LastInst->getOperand(0).getMBB();
709 } else if (LastOpc == AMDGPU::JUMP_COND) {
710 MachineInstr *predSet = I;
711 while (!isPredicateSetter(predSet->getOpcode())) {
714 TBB = LastInst->getOperand(0).getMBB();
715 Cond.push_back(predSet->getOperand(1));
716 Cond.push_back(predSet->getOperand(2));
717 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
720 return true; // Can't handle indirect branch.
723 // Get the instruction before it if it is a terminator.
724 MachineInstr *SecondLastInst = I;
725 unsigned SecondLastOpc = SecondLastInst->getOpcode();
727 // If the block ends with a B and a Bcc, handle it.
728 if (SecondLastOpc == AMDGPU::JUMP_COND && LastOpc == AMDGPU::JUMP) {
729 MachineInstr *predSet = --I;
730 while (!isPredicateSetter(predSet->getOpcode())) {
733 TBB = SecondLastInst->getOperand(0).getMBB();
734 FBB = LastInst->getOperand(0).getMBB();
735 Cond.push_back(predSet->getOperand(1));
736 Cond.push_back(predSet->getOperand(2));
737 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
741 // Otherwise, can't handle this.
745 int R600InstrInfo::getBranchInstr(const MachineOperand &op) const {
746 const MachineInstr *MI = op.getParent();
748 switch (MI->getDesc().OpInfo->RegClass) {
749 default: // FIXME: fallthrough??
750 case AMDGPU::GPRI32RegClassID: return AMDGPU::BRANCH_COND_i32;
751 case AMDGPU::GPRF32RegClassID: return AMDGPU::BRANCH_COND_f32;
756 MachineBasicBlock::iterator FindLastAluClause(MachineBasicBlock &MBB) {
757 for (MachineBasicBlock::reverse_iterator It = MBB.rbegin(), E = MBB.rend();
759 if (It->getOpcode() == AMDGPU::CF_ALU ||
760 It->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE)
761 return llvm::prior(It.base());
767 R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
768 MachineBasicBlock *TBB,
769 MachineBasicBlock *FBB,
770 const SmallVectorImpl<MachineOperand> &Cond,
772 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
776 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB);
779 MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
780 assert(PredSet && "No previous predicate !");
781 addFlag(PredSet, 0, MO_FLAG_PUSH);
782 PredSet->getOperand(2).setImm(Cond[1].getImm());
784 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
786 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
787 MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
788 if (CfAlu == MBB.end())
790 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
791 CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
795 MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
796 assert(PredSet && "No previous predicate !");
797 addFlag(PredSet, 0, MO_FLAG_PUSH);
798 PredSet->getOperand(2).setImm(Cond[1].getImm());
799 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
801 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
802 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB);
803 MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
804 if (CfAlu == MBB.end())
806 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
807 CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
813 R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
815 // Note : we leave PRED* instructions there.
816 // They may be needed when predicating instructions.
818 MachineBasicBlock::iterator I = MBB.end();
820 if (I == MBB.begin()) {
824 switch (I->getOpcode()) {
827 case AMDGPU::JUMP_COND: {
828 MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
829 clearFlag(predSet, 0, MO_FLAG_PUSH);
830 I->eraseFromParent();
831 MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
832 if (CfAlu == MBB.end())
834 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
835 CfAlu->setDesc(get(AMDGPU::CF_ALU));
839 I->eraseFromParent();
844 if (I == MBB.begin()) {
848 switch (I->getOpcode()) {
849 // FIXME: only one case??
852 case AMDGPU::JUMP_COND: {
853 MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
854 clearFlag(predSet, 0, MO_FLAG_PUSH);
855 I->eraseFromParent();
856 MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
857 if (CfAlu == MBB.end())
859 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
860 CfAlu->setDesc(get(AMDGPU::CF_ALU));
864 I->eraseFromParent();
871 R600InstrInfo::isPredicated(const MachineInstr *MI) const {
872 int idx = MI->findFirstPredOperandIdx();
876 unsigned Reg = MI->getOperand(idx).getReg();
878 default: return false;
879 case AMDGPU::PRED_SEL_ONE:
880 case AMDGPU::PRED_SEL_ZERO:
881 case AMDGPU::PREDICATE_BIT:
887 R600InstrInfo::isPredicable(MachineInstr *MI) const {
888 // XXX: KILL* instructions can be predicated, but they must be the last
889 // instruction in a clause, so this means any instructions after them cannot
890 // be predicated. Until we have proper support for instruction clauses in the
891 // backend, we will mark KILL* instructions as unpredicable.
893 if (MI->getOpcode() == AMDGPU::KILLGT) {
895 } else if (MI->getOpcode() == AMDGPU::CF_ALU) {
896 // If the clause start in the middle of MBB then the MBB has more
897 // than a single clause, unable to predicate several clauses.
898 if (MI->getParent()->begin() != MachineBasicBlock::iterator(MI))
900 // TODO: We don't support KC merging atm
901 if (MI->getOperand(3).getImm() != 0 || MI->getOperand(4).getImm() != 0)
904 } else if (isVector(*MI)) {
907 return AMDGPUInstrInfo::isPredicable(MI);
913 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
915 unsigned ExtraPredCycles,
916 const BranchProbability &Probability) const{
921 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
923 unsigned ExtraTCycles,
924 MachineBasicBlock &FMBB,
926 unsigned ExtraFCycles,
927 const BranchProbability &Probability) const {
932 R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
934 const BranchProbability &Probability)
940 R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
941 MachineBasicBlock &FMBB) const {
947 R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
948 MachineOperand &MO = Cond[1];
949 switch (MO.getImm()) {
950 case OPCODE_IS_ZERO_INT:
951 MO.setImm(OPCODE_IS_NOT_ZERO_INT);
953 case OPCODE_IS_NOT_ZERO_INT:
954 MO.setImm(OPCODE_IS_ZERO_INT);
957 MO.setImm(OPCODE_IS_NOT_ZERO);
959 case OPCODE_IS_NOT_ZERO:
960 MO.setImm(OPCODE_IS_ZERO);
966 MachineOperand &MO2 = Cond[2];
967 switch (MO2.getReg()) {
968 case AMDGPU::PRED_SEL_ZERO:
969 MO2.setReg(AMDGPU::PRED_SEL_ONE);
971 case AMDGPU::PRED_SEL_ONE:
972 MO2.setReg(AMDGPU::PRED_SEL_ZERO);
981 R600InstrInfo::DefinesPredicate(MachineInstr *MI,
982 std::vector<MachineOperand> &Pred) const {
983 return isPredicateSetter(MI->getOpcode());
988 R600InstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
989 const SmallVectorImpl<MachineOperand> &Pred2) const {
995 R600InstrInfo::PredicateInstruction(MachineInstr *MI,
996 const SmallVectorImpl<MachineOperand> &Pred) const {
997 int PIdx = MI->findFirstPredOperandIdx();
999 if (MI->getOpcode() == AMDGPU::CF_ALU) {
1000 MI->getOperand(8).setImm(0);
1005 MachineOperand &PMO = MI->getOperand(PIdx);
1006 PMO.setReg(Pred[2].getReg());
1007 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1008 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
1015 unsigned int R600InstrInfo::getPredicationCost(const MachineInstr *) const {
1019 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1020 const MachineInstr *MI,
1021 unsigned *PredCost) const {
1027 int R600InstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
1028 const MachineRegisterInfo &MRI = MF.getRegInfo();
1029 const MachineFrameInfo *MFI = MF.getFrameInfo();
1032 if (MFI->getNumObjects() == 0) {
1036 if (MRI.livein_empty()) {
1040 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
1041 LE = MRI.livein_end();
1043 Offset = std::max(Offset,
1044 GET_REG_INDEX(RI.getEncodingValue(LI->first)));
1050 int R600InstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
1052 const MachineFrameInfo *MFI = MF.getFrameInfo();
1054 // Variable sized objects are not supported
1055 assert(!MFI->hasVarSizedObjects());
1057 if (MFI->getNumObjects() == 0) {
1061 Offset = TM.getFrameLowering()->getFrameIndexOffset(MF, -1);
1063 return getIndirectIndexBegin(MF) + Offset;
1066 std::vector<unsigned> R600InstrInfo::getIndirectReservedRegs(
1067 const MachineFunction &MF) const {
1068 const AMDGPUFrameLowering *TFL =
1069 static_cast<const AMDGPUFrameLowering*>(TM.getFrameLowering());
1070 std::vector<unsigned> Regs;
1072 unsigned StackWidth = TFL->getStackWidth(MF);
1073 int End = getIndirectIndexEnd(MF);
1079 for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) {
1080 unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
1081 Regs.push_back(SuperReg);
1082 for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
1083 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
1084 Regs.push_back(Reg);
1090 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex,
1091 unsigned Channel) const {
1092 // XXX: Remove when we support a stack width > 2
1093 assert(Channel == 0);
1097 const TargetRegisterClass *R600InstrInfo::getIndirectAddrRegClass() const {
1098 return &AMDGPU::R600_TReg32_XRegClass;
1101 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
1102 MachineBasicBlock::iterator I,
1103 unsigned ValueReg, unsigned Address,
1104 unsigned OffsetReg) const {
1105 unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
1106 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1107 AMDGPU::AR_X, OffsetReg);
1108 setImmOperand(MOVA, AMDGPU::OpName::write, 0);
1110 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1112 .addReg(AMDGPU::AR_X,
1113 RegState::Implicit | RegState::Kill);
1114 setImmOperand(Mov, AMDGPU::OpName::dst_rel, 1);
1118 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
1119 MachineBasicBlock::iterator I,
1120 unsigned ValueReg, unsigned Address,
1121 unsigned OffsetReg) const {
1122 unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
1123 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1126 setImmOperand(MOVA, AMDGPU::OpName::write, 0);
1127 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1130 .addReg(AMDGPU::AR_X,
1131 RegState::Implicit | RegState::Kill);
1132 setImmOperand(Mov, AMDGPU::OpName::src0_rel, 1);
1137 unsigned R600InstrInfo::getMaxAlusPerClause() const {
1141 MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB,
1142 MachineBasicBlock::iterator I,
1146 unsigned Src1Reg) const {
1147 MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
1151 MIB.addImm(0) // $update_exec_mask
1152 .addImm(0); // $update_predicate
1154 MIB.addImm(1) // $write
1156 .addImm(0) // $dst_rel
1157 .addImm(0) // $dst_clamp
1158 .addReg(Src0Reg) // $src0
1159 .addImm(0) // $src0_neg
1160 .addImm(0) // $src0_rel
1161 .addImm(0) // $src0_abs
1162 .addImm(-1); // $src0_sel
1165 MIB.addReg(Src1Reg) // $src1
1166 .addImm(0) // $src1_neg
1167 .addImm(0) // $src1_rel
1168 .addImm(0) // $src1_abs
1169 .addImm(-1); // $src1_sel
1172 //XXX: The r600g finalizer expects this to be 1, once we've moved the
1173 //scheduling to the backend, we can change the default to 0.
1174 MIB.addImm(1) // $last
1175 .addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
1176 .addImm(0) // $literal
1177 .addImm(0); // $bank_swizzle
1182 #define OPERAND_CASE(Label) \
1184 static const unsigned Ops[] = \
1194 static unsigned getSlotedOps(unsigned Op, unsigned Slot) {
1196 OPERAND_CASE(AMDGPU::OpName::update_exec_mask)
1197 OPERAND_CASE(AMDGPU::OpName::update_pred)
1198 OPERAND_CASE(AMDGPU::OpName::write)
1199 OPERAND_CASE(AMDGPU::OpName::omod)
1200 OPERAND_CASE(AMDGPU::OpName::dst_rel)
1201 OPERAND_CASE(AMDGPU::OpName::clamp)
1202 OPERAND_CASE(AMDGPU::OpName::src0)
1203 OPERAND_CASE(AMDGPU::OpName::src0_neg)
1204 OPERAND_CASE(AMDGPU::OpName::src0_rel)
1205 OPERAND_CASE(AMDGPU::OpName::src0_abs)
1206 OPERAND_CASE(AMDGPU::OpName::src0_sel)
1207 OPERAND_CASE(AMDGPU::OpName::src1)
1208 OPERAND_CASE(AMDGPU::OpName::src1_neg)
1209 OPERAND_CASE(AMDGPU::OpName::src1_rel)
1210 OPERAND_CASE(AMDGPU::OpName::src1_abs)
1211 OPERAND_CASE(AMDGPU::OpName::src1_sel)
1212 OPERAND_CASE(AMDGPU::OpName::pred_sel)
1214 llvm_unreachable("Wrong Operand");
1220 MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction(
1221 MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg)
1223 assert (MI->getOpcode() == AMDGPU::DOT_4 && "Not Implemented");
1225 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
1226 if (ST.getGeneration() <= AMDGPUSubtarget::R700)
1227 Opcode = AMDGPU::DOT4_r600;
1229 Opcode = AMDGPU::DOT4_eg;
1230 MachineBasicBlock::iterator I = MI;
1231 MachineOperand &Src0 = MI->getOperand(
1232 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src0, Slot)));
1233 MachineOperand &Src1 = MI->getOperand(
1234 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src1, Slot)));
1235 MachineInstr *MIB = buildDefaultInstruction(
1236 MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
1237 static const unsigned Operands[14] = {
1238 AMDGPU::OpName::update_exec_mask,
1239 AMDGPU::OpName::update_pred,
1240 AMDGPU::OpName::write,
1241 AMDGPU::OpName::omod,
1242 AMDGPU::OpName::dst_rel,
1243 AMDGPU::OpName::clamp,
1244 AMDGPU::OpName::src0_neg,
1245 AMDGPU::OpName::src0_rel,
1246 AMDGPU::OpName::src0_abs,
1247 AMDGPU::OpName::src0_sel,
1248 AMDGPU::OpName::src1_neg,
1249 AMDGPU::OpName::src1_rel,
1250 AMDGPU::OpName::src1_abs,
1251 AMDGPU::OpName::src1_sel,
1254 for (unsigned i = 0; i < 14; i++) {
1255 MachineOperand &MO = MI->getOperand(
1256 getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));
1257 assert (MO.isImm());
1258 setImmOperand(MIB, Operands[i], MO.getImm());
1260 MIB->getOperand(20).setImm(0);
1264 MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,
1265 MachineBasicBlock::iterator I,
1267 uint64_t Imm) const {
1268 MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg,
1269 AMDGPU::ALU_LITERAL_X);
1270 setImmOperand(MovImm, AMDGPU::OpName::literal, Imm);
1274 MachineInstr *R600InstrInfo::buildMovInstr(MachineBasicBlock *MBB,
1275 MachineBasicBlock::iterator I,
1276 unsigned DstReg, unsigned SrcReg) const {
1277 return buildDefaultInstruction(*MBB, I, AMDGPU::MOV, DstReg, SrcReg);
1280 int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const {
1281 return getOperandIdx(MI.getOpcode(), Op);
1284 int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const {
1285 return AMDGPU::getNamedOperandIdx(Opcode, Op);
1288 void R600InstrInfo::setImmOperand(MachineInstr *MI, unsigned Op,
1289 int64_t Imm) const {
1290 int Idx = getOperandIdx(*MI, Op);
1291 assert(Idx != -1 && "Operand not supported for this instruction.");
1292 assert(MI->getOperand(Idx).isImm());
1293 MI->getOperand(Idx).setImm(Imm);
1296 //===----------------------------------------------------------------------===//
1297 // Instruction flag getters/setters
1298 //===----------------------------------------------------------------------===//
1300 bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const {
1301 return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
1304 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr *MI, unsigned SrcIdx,
1305 unsigned Flag) const {
1306 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1309 // If we pass something other than the default value of Flag to this
1310 // function, it means we are want to set a flag on an instruction
1311 // that uses native encoding.
1312 assert(HAS_NATIVE_OPERANDS(TargetFlags));
1313 bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3;
1316 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::clamp);
1319 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::write);
1321 case MO_FLAG_NOT_LAST:
1323 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::last);
1327 case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_neg); break;
1328 case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_neg); break;
1329 case 2: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src2_neg); break;
1334 assert(!IsOP3 && "Cannot set absolute value modifier for OP3 "
1338 case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_abs); break;
1339 case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_abs); break;
1347 assert(FlagIndex != -1 && "Flag not supported for this instruction");
1349 FlagIndex = GET_FLAG_OPERAND_IDX(TargetFlags);
1350 assert(FlagIndex != 0 &&
1351 "Instruction flags not supported for this instruction");
1354 MachineOperand &FlagOp = MI->getOperand(FlagIndex);
1355 assert(FlagOp.isImm());
1359 void R600InstrInfo::addFlag(MachineInstr *MI, unsigned Operand,
1360 unsigned Flag) const {
1361 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1365 if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1366 MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1367 if (Flag == MO_FLAG_NOT_LAST) {
1368 clearFlag(MI, Operand, MO_FLAG_LAST);
1369 } else if (Flag == MO_FLAG_MASK) {
1370 clearFlag(MI, Operand, Flag);
1375 MachineOperand &FlagOp = getFlagOp(MI, Operand);
1376 FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
1380 void R600InstrInfo::clearFlag(MachineInstr *MI, unsigned Operand,
1381 unsigned Flag) const {
1382 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1383 if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1384 MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1387 MachineOperand &FlagOp = getFlagOp(MI);
1388 unsigned InstFlags = FlagOp.getImm();
1389 InstFlags &= ~(Flag << (NUM_MO_FLAGS * Operand));
1390 FlagOp.setImm(InstFlags);