1 //===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief R600 Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
15 #include "R600InstrInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "R600Defines.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #define GET_INSTRINFO_CTOR
27 #include "AMDGPUGenDFAPacketizer.inc"
31 R600InstrInfo::R600InstrInfo(AMDGPUTargetMachine &tm)
32 : AMDGPUInstrInfo(tm),
34 ST(tm.getSubtarget<AMDGPUSubtarget>())
37 const R600RegisterInfo &R600InstrInfo::getRegisterInfo() const {
41 bool R600InstrInfo::isTrig(const MachineInstr &MI) const {
42 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
45 bool R600InstrInfo::isVector(const MachineInstr &MI) const {
46 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
50 R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
51 MachineBasicBlock::iterator MI, DebugLoc DL,
52 unsigned DestReg, unsigned SrcReg,
54 unsigned VectorComponents = 0;
55 if (AMDGPU::R600_Reg128RegClass.contains(DestReg) &&
56 AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
58 } else if(AMDGPU::R600_Reg64RegClass.contains(DestReg) &&
59 AMDGPU::R600_Reg64RegClass.contains(SrcReg)) {
63 if (VectorComponents > 0) {
64 for (unsigned I = 0; I < VectorComponents; I++) {
65 unsigned SubRegIndex = RI.getSubRegFromChannel(I);
66 buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
67 RI.getSubReg(DestReg, SubRegIndex),
68 RI.getSubReg(SrcReg, SubRegIndex))
70 RegState::Define | RegState::Implicit);
73 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
75 NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0))
80 MachineInstr * R600InstrInfo::getMovImmInstr(MachineFunction *MF,
81 unsigned DstReg, int64_t Imm) const {
82 MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc());
83 MachineInstrBuilder MIB(*MF, MI);
84 MIB.addReg(DstReg, RegState::Define);
85 MIB.addReg(AMDGPU::ALU_LITERAL_X);
87 MIB.addReg(0); // PREDICATE_BIT
92 unsigned R600InstrInfo::getIEQOpcode() const {
93 return AMDGPU::SETE_INT;
96 bool R600InstrInfo::isMov(unsigned Opcode) const {
100 default: return false;
102 case AMDGPU::MOV_IMM_F32:
103 case AMDGPU::MOV_IMM_I32:
108 // Some instructions act as place holders to emulate operations that the GPU
109 // hardware does automatically. This function can be used to check if
110 // an opcode falls into this category.
111 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const {
113 default: return false;
119 bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
123 bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
125 default: return false;
126 case AMDGPU::CUBE_r600_pseudo:
127 case AMDGPU::CUBE_r600_real:
128 case AMDGPU::CUBE_eg_pseudo:
129 case AMDGPU::CUBE_eg_real:
134 bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
135 unsigned TargetFlags = get(Opcode).TSFlags;
137 return (TargetFlags & R600_InstFlag::ALU_INST);
140 bool R600InstrInfo::hasInstrModifiers(unsigned Opcode) const {
141 unsigned TargetFlags = get(Opcode).TSFlags;
143 return ((TargetFlags & R600_InstFlag::OP1) |
144 (TargetFlags & R600_InstFlag::OP2) |
145 (TargetFlags & R600_InstFlag::OP3));
148 bool R600InstrInfo::isLDSInstr(unsigned Opcode) const {
149 unsigned TargetFlags = get(Opcode).TSFlags;
151 return ((TargetFlags & R600_InstFlag::LDS_1A) |
152 (TargetFlags & R600_InstFlag::LDS_1A1D));
155 bool R600InstrInfo::isTransOnly(unsigned Opcode) const {
156 return (get(Opcode).TSFlags & R600_InstFlag::TRANS_ONLY);
159 bool R600InstrInfo::isTransOnly(const MachineInstr *MI) const {
160 return isTransOnly(MI->getOpcode());
163 bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
164 return ST.hasVertexCache() && IS_VTX(get(Opcode));
167 bool R600InstrInfo::usesVertexCache(const MachineInstr *MI) const {
168 const R600MachineFunctionInfo *MFI = MI->getParent()->getParent()->getInfo<R600MachineFunctionInfo>();
169 return MFI->ShaderType != ShaderType::COMPUTE && usesVertexCache(MI->getOpcode());
172 bool R600InstrInfo::usesTextureCache(unsigned Opcode) const {
173 return (!ST.hasVertexCache() && IS_VTX(get(Opcode))) || IS_TEX(get(Opcode));
176 bool R600InstrInfo::usesTextureCache(const MachineInstr *MI) const {
177 const R600MachineFunctionInfo *MFI = MI->getParent()->getParent()->getInfo<R600MachineFunctionInfo>();
178 return (MFI->ShaderType == ShaderType::COMPUTE && usesVertexCache(MI->getOpcode())) ||
179 usesTextureCache(MI->getOpcode());
182 bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const {
185 case AMDGPU::GROUP_BARRIER:
192 int R600InstrInfo::getSrcIdx(unsigned Opcode, unsigned SrcNum) const {
193 static const unsigned OpTable[] = {
194 AMDGPU::OpName::src0,
195 AMDGPU::OpName::src1,
200 return getOperandIdx(Opcode, OpTable[SrcNum]);
203 #define SRC_SEL_ROWS 11
204 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const {
205 static const unsigned SrcSelTable[SRC_SEL_ROWS][2] = {
206 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
207 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
208 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
209 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
210 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
211 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
212 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
213 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
214 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
215 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
216 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W}
219 for (unsigned i = 0; i < SRC_SEL_ROWS; ++i) {
220 if (getOperandIdx(Opcode, SrcSelTable[i][0]) == (int)SrcIdx) {
221 return getOperandIdx(Opcode, SrcSelTable[i][1]);
228 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
229 R600InstrInfo::getSrcs(MachineInstr *MI) const {
230 SmallVector<std::pair<MachineOperand *, int64_t>, 3> Result;
232 if (MI->getOpcode() == AMDGPU::DOT_4) {
233 static const unsigned OpTable[8][2] = {
234 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
235 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
236 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
237 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
238 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
239 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
240 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
241 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W},
244 for (unsigned j = 0; j < 8; j++) {
245 MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
247 unsigned Reg = MO.getReg();
248 if (Reg == AMDGPU::ALU_CONST) {
249 unsigned Sel = MI->getOperand(getOperandIdx(MI->getOpcode(),
250 OpTable[j][1])).getImm();
251 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Sel));
259 static const unsigned OpTable[3][2] = {
260 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
261 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
262 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
265 for (unsigned j = 0; j < 3; j++) {
266 int SrcIdx = getOperandIdx(MI->getOpcode(), OpTable[j][0]);
269 MachineOperand &MO = MI->getOperand(SrcIdx);
270 unsigned Reg = MI->getOperand(SrcIdx).getReg();
271 if (Reg == AMDGPU::ALU_CONST) {
272 unsigned Sel = MI->getOperand(
273 getOperandIdx(MI->getOpcode(), OpTable[j][1])).getImm();
274 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Sel));
277 if (Reg == AMDGPU::ALU_LITERAL_X) {
278 unsigned Imm = MI->getOperand(
279 getOperandIdx(MI->getOpcode(), AMDGPU::OpName::literal)).getImm();
280 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Imm));
283 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, 0));
288 std::vector<std::pair<int, unsigned> >
289 R600InstrInfo::ExtractSrcs(MachineInstr *MI,
290 const DenseMap<unsigned, unsigned> &PV,
291 unsigned &ConstCount) const {
293 const SmallVector<std::pair<MachineOperand *, int64_t>, 3> Srcs = getSrcs(MI);
294 const std::pair<int, unsigned> DummyPair(-1, 0);
295 std::vector<std::pair<int, unsigned> > Result;
297 for (unsigned n = Srcs.size(); i < n; ++i) {
298 unsigned Reg = Srcs[i].first->getReg();
299 unsigned Index = RI.getEncodingValue(Reg) & 0xff;
300 if (Reg == AMDGPU::OQAP) {
301 Result.push_back(std::pair<int, unsigned>(Index, 0));
303 if (PV.find(Reg) != PV.end()) {
304 // 255 is used to tells its a PS/PV reg
305 Result.push_back(std::pair<int, unsigned>(255, 0));
310 Result.push_back(DummyPair);
313 unsigned Chan = RI.getHWRegChan(Reg);
314 Result.push_back(std::pair<int, unsigned>(Index, Chan));
317 Result.push_back(DummyPair);
321 static std::vector<std::pair<int, unsigned> >
322 Swizzle(std::vector<std::pair<int, unsigned> > Src,
323 R600InstrInfo::BankSwizzle Swz) {
325 case R600InstrInfo::ALU_VEC_012_SCL_210:
327 case R600InstrInfo::ALU_VEC_021_SCL_122:
328 std::swap(Src[1], Src[2]);
330 case R600InstrInfo::ALU_VEC_102_SCL_221:
331 std::swap(Src[0], Src[1]);
333 case R600InstrInfo::ALU_VEC_120_SCL_212:
334 std::swap(Src[0], Src[1]);
335 std::swap(Src[0], Src[2]);
337 case R600InstrInfo::ALU_VEC_201:
338 std::swap(Src[0], Src[2]);
339 std::swap(Src[0], Src[1]);
341 case R600InstrInfo::ALU_VEC_210:
342 std::swap(Src[0], Src[2]);
349 getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) {
351 case R600InstrInfo::ALU_VEC_012_SCL_210: {
352 unsigned Cycles[3] = { 2, 1, 0};
355 case R600InstrInfo::ALU_VEC_021_SCL_122: {
356 unsigned Cycles[3] = { 1, 2, 2};
359 case R600InstrInfo::ALU_VEC_120_SCL_212: {
360 unsigned Cycles[3] = { 2, 1, 2};
363 case R600InstrInfo::ALU_VEC_102_SCL_221: {
364 unsigned Cycles[3] = { 2, 2, 1};
368 llvm_unreachable("Wrong Swizzle for Trans Slot");
373 /// returns how many MIs (whose inputs are represented by IGSrcs) can be packed
374 /// in the same Instruction Group while meeting read port limitations given a
375 /// Swz swizzle sequence.
376 unsigned R600InstrInfo::isLegalUpTo(
377 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
378 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
379 const std::vector<std::pair<int, unsigned> > &TransSrcs,
380 R600InstrInfo::BankSwizzle TransSwz) const {
382 memset(Vector, -1, sizeof(Vector));
383 for (unsigned i = 0, e = IGSrcs.size(); i < e; i++) {
384 const std::vector<std::pair<int, unsigned> > &Srcs =
385 Swizzle(IGSrcs[i], Swz[i]);
386 for (unsigned j = 0; j < 3; j++) {
387 const std::pair<int, unsigned> &Src = Srcs[j];
388 if (Src.first < 0 || Src.first == 255)
390 if (Src.first == GET_REG_INDEX(RI.getEncodingValue(AMDGPU::OQAP))) {
391 if (Swz[i] != R600InstrInfo::ALU_VEC_012_SCL_210 &&
392 Swz[i] != R600InstrInfo::ALU_VEC_021_SCL_122) {
393 // The value from output queue A (denoted by register OQAP) can
394 // only be fetched during the first cycle.
397 // OQAP does not count towards the normal read port restrictions
400 if (Vector[Src.second][j] < 0)
401 Vector[Src.second][j] = Src.first;
402 if (Vector[Src.second][j] != Src.first)
406 // Now check Trans Alu
407 for (unsigned i = 0, e = TransSrcs.size(); i < e; ++i) {
408 const std::pair<int, unsigned> &Src = TransSrcs[i];
409 unsigned Cycle = getTransSwizzle(TransSwz, i);
412 if (Src.first == 255)
414 if (Vector[Src.second][Cycle] < 0)
415 Vector[Src.second][Cycle] = Src.first;
416 if (Vector[Src.second][Cycle] != Src.first)
417 return IGSrcs.size() - 1;
419 return IGSrcs.size();
422 /// Given a swizzle sequence SwzCandidate and an index Idx, returns the next
423 /// (in lexicographic term) swizzle sequence assuming that all swizzles after
424 /// Idx can be skipped
426 NextPossibleSolution(
427 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
429 assert(Idx < SwzCandidate.size());
431 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210)
433 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) {
434 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210;
438 int NextSwizzle = SwzCandidate[ResetIdx] + 1;
439 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle;
443 /// Enumerate all possible Swizzle sequence to find one that can meet all
444 /// read port requirements.
445 bool R600InstrInfo::FindSwizzleForVectorSlot(
446 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
447 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
448 const std::vector<std::pair<int, unsigned> > &TransSrcs,
449 R600InstrInfo::BankSwizzle TransSwz) const {
450 unsigned ValidUpTo = 0;
452 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz);
453 if (ValidUpTo == IGSrcs.size())
455 } while (NextPossibleSolution(SwzCandidate, ValidUpTo));
459 /// Instructions in Trans slot can't read gpr at cycle 0 if they also read
460 /// a const, and can't read a gpr at cycle 1 if they read 2 const.
462 isConstCompatible(R600InstrInfo::BankSwizzle TransSwz,
463 const std::vector<std::pair<int, unsigned> > &TransOps,
464 unsigned ConstCount) {
465 for (unsigned i = 0, e = TransOps.size(); i < e; ++i) {
466 const std::pair<int, unsigned> &Src = TransOps[i];
467 unsigned Cycle = getTransSwizzle(TransSwz, i);
470 if (ConstCount > 0 && Cycle == 0)
472 if (ConstCount > 1 && Cycle == 1)
479 R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,
480 const DenseMap<unsigned, unsigned> &PV,
481 std::vector<BankSwizzle> &ValidSwizzle,
484 //Todo : support shared src0 - src1 operand
486 std::vector<std::vector<std::pair<int, unsigned> > > IGSrcs;
487 ValidSwizzle.clear();
489 BankSwizzle TransBS = ALU_VEC_012_SCL_210;
490 for (unsigned i = 0, e = IG.size(); i < e; ++i) {
491 IGSrcs.push_back(ExtractSrcs(IG[i], PV, ConstCount));
492 unsigned Op = getOperandIdx(IG[i]->getOpcode(),
493 AMDGPU::OpName::bank_swizzle);
494 ValidSwizzle.push_back( (R600InstrInfo::BankSwizzle)
495 IG[i]->getOperand(Op).getImm());
497 std::vector<std::pair<int, unsigned> > TransOps;
499 return FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps, TransBS);
501 TransOps = IGSrcs.back();
503 ValidSwizzle.pop_back();
505 static const R600InstrInfo::BankSwizzle TransSwz[] = {
511 for (unsigned i = 0; i < 4; i++) {
512 TransBS = TransSwz[i];
513 if (!isConstCompatible(TransBS, TransOps, ConstCount))
515 bool Result = FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps,
518 ValidSwizzle.push_back(TransBS);
528 R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts)
530 assert (Consts.size() <= 12 && "Too many operands in instructions group");
531 unsigned Pair1 = 0, Pair2 = 0;
532 for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
533 unsigned ReadConstHalf = Consts[i] & 2;
534 unsigned ReadConstIndex = Consts[i] & (~3);
535 unsigned ReadHalfConst = ReadConstIndex | ReadConstHalf;
537 Pair1 = ReadHalfConst;
540 if (Pair1 == ReadHalfConst)
543 Pair2 = ReadHalfConst;
546 if (Pair2 != ReadHalfConst)
553 R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs)
555 std::vector<unsigned> Consts;
556 SmallSet<int64_t, 4> Literals;
557 for (unsigned i = 0, n = MIs.size(); i < n; i++) {
558 MachineInstr *MI = MIs[i];
559 if (!isALUInstr(MI->getOpcode()))
562 const SmallVectorImpl<std::pair<MachineOperand *, int64_t> > &Srcs =
565 for (unsigned j = 0, e = Srcs.size(); j < e; j++) {
566 std::pair<MachineOperand *, unsigned> Src = Srcs[j];
567 if (Src.first->getReg() == AMDGPU::ALU_LITERAL_X)
568 Literals.insert(Src.second);
569 if (Literals.size() > 4)
571 if (Src.first->getReg() == AMDGPU::ALU_CONST)
572 Consts.push_back(Src.second);
573 if (AMDGPU::R600_KC0RegClass.contains(Src.first->getReg()) ||
574 AMDGPU::R600_KC1RegClass.contains(Src.first->getReg())) {
575 unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
576 unsigned Chan = RI.getHWRegChan(Src.first->getReg());
577 Consts.push_back((Index << 2) | Chan);
581 return fitsConstReadLimitations(Consts);
584 DFAPacketizer *R600InstrInfo::CreateTargetScheduleState(const TargetMachine *TM,
585 const ScheduleDAG *DAG) const {
586 const InstrItineraryData *II = TM->getInstrItineraryData();
587 return TM->getSubtarget<AMDGPUSubtarget>().createDFAPacketizer(II);
591 isPredicateSetter(unsigned Opcode) {
600 static MachineInstr *
601 findFirstPredicateSetterFrom(MachineBasicBlock &MBB,
602 MachineBasicBlock::iterator I) {
603 while (I != MBB.begin()) {
605 MachineInstr *MI = I;
606 if (isPredicateSetter(MI->getOpcode()))
614 bool isJump(unsigned Opcode) {
615 return Opcode == AMDGPU::JUMP || Opcode == AMDGPU::JUMP_COND;
619 R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
620 MachineBasicBlock *&TBB,
621 MachineBasicBlock *&FBB,
622 SmallVectorImpl<MachineOperand> &Cond,
623 bool AllowModify) const {
624 // Most of the following comes from the ARM implementation of AnalyzeBranch
626 // If the block has no terminators, it just falls into the block after it.
627 MachineBasicBlock::iterator I = MBB.end();
628 if (I == MBB.begin())
631 while (I->isDebugValue()) {
632 if (I == MBB.begin())
636 if (!isJump(static_cast<MachineInstr *>(I)->getOpcode())) {
640 // Get the last instruction in the block.
641 MachineInstr *LastInst = I;
643 // If there is only one terminator instruction, process it.
644 unsigned LastOpc = LastInst->getOpcode();
645 if (I == MBB.begin() ||
646 !isJump(static_cast<MachineInstr *>(--I)->getOpcode())) {
647 if (LastOpc == AMDGPU::JUMP) {
648 TBB = LastInst->getOperand(0).getMBB();
650 } else if (LastOpc == AMDGPU::JUMP_COND) {
651 MachineInstr *predSet = I;
652 while (!isPredicateSetter(predSet->getOpcode())) {
655 TBB = LastInst->getOperand(0).getMBB();
656 Cond.push_back(predSet->getOperand(1));
657 Cond.push_back(predSet->getOperand(2));
658 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
661 return true; // Can't handle indirect branch.
664 // Get the instruction before it if it is a terminator.
665 MachineInstr *SecondLastInst = I;
666 unsigned SecondLastOpc = SecondLastInst->getOpcode();
668 // If the block ends with a B and a Bcc, handle it.
669 if (SecondLastOpc == AMDGPU::JUMP_COND && LastOpc == AMDGPU::JUMP) {
670 MachineInstr *predSet = --I;
671 while (!isPredicateSetter(predSet->getOpcode())) {
674 TBB = SecondLastInst->getOperand(0).getMBB();
675 FBB = LastInst->getOperand(0).getMBB();
676 Cond.push_back(predSet->getOperand(1));
677 Cond.push_back(predSet->getOperand(2));
678 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
682 // Otherwise, can't handle this.
686 int R600InstrInfo::getBranchInstr(const MachineOperand &op) const {
687 const MachineInstr *MI = op.getParent();
689 switch (MI->getDesc().OpInfo->RegClass) {
690 default: // FIXME: fallthrough??
691 case AMDGPU::GPRI32RegClassID: return AMDGPU::BRANCH_COND_i32;
692 case AMDGPU::GPRF32RegClassID: return AMDGPU::BRANCH_COND_f32;
697 MachineBasicBlock::iterator FindLastAluClause(MachineBasicBlock &MBB) {
698 for (MachineBasicBlock::reverse_iterator It = MBB.rbegin(), E = MBB.rend();
700 if (It->getOpcode() == AMDGPU::CF_ALU ||
701 It->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE)
702 return llvm::prior(It.base());
708 R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
709 MachineBasicBlock *TBB,
710 MachineBasicBlock *FBB,
711 const SmallVectorImpl<MachineOperand> &Cond,
713 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
717 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB);
720 MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
721 assert(PredSet && "No previous predicate !");
722 addFlag(PredSet, 0, MO_FLAG_PUSH);
723 PredSet->getOperand(2).setImm(Cond[1].getImm());
725 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
727 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
728 MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
729 if (CfAlu == MBB.end())
731 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
732 CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
736 MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
737 assert(PredSet && "No previous predicate !");
738 addFlag(PredSet, 0, MO_FLAG_PUSH);
739 PredSet->getOperand(2).setImm(Cond[1].getImm());
740 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
742 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
743 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB);
744 MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
745 if (CfAlu == MBB.end())
747 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
748 CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
754 R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
756 // Note : we leave PRED* instructions there.
757 // They may be needed when predicating instructions.
759 MachineBasicBlock::iterator I = MBB.end();
761 if (I == MBB.begin()) {
765 switch (I->getOpcode()) {
768 case AMDGPU::JUMP_COND: {
769 MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
770 clearFlag(predSet, 0, MO_FLAG_PUSH);
771 I->eraseFromParent();
772 MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
773 if (CfAlu == MBB.end())
775 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
776 CfAlu->setDesc(get(AMDGPU::CF_ALU));
780 I->eraseFromParent();
785 if (I == MBB.begin()) {
789 switch (I->getOpcode()) {
790 // FIXME: only one case??
793 case AMDGPU::JUMP_COND: {
794 MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
795 clearFlag(predSet, 0, MO_FLAG_PUSH);
796 I->eraseFromParent();
797 MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
798 if (CfAlu == MBB.end())
800 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
801 CfAlu->setDesc(get(AMDGPU::CF_ALU));
805 I->eraseFromParent();
812 R600InstrInfo::isPredicated(const MachineInstr *MI) const {
813 int idx = MI->findFirstPredOperandIdx();
817 unsigned Reg = MI->getOperand(idx).getReg();
819 default: return false;
820 case AMDGPU::PRED_SEL_ONE:
821 case AMDGPU::PRED_SEL_ZERO:
822 case AMDGPU::PREDICATE_BIT:
828 R600InstrInfo::isPredicable(MachineInstr *MI) const {
829 // XXX: KILL* instructions can be predicated, but they must be the last
830 // instruction in a clause, so this means any instructions after them cannot
831 // be predicated. Until we have proper support for instruction clauses in the
832 // backend, we will mark KILL* instructions as unpredicable.
834 if (MI->getOpcode() == AMDGPU::KILLGT) {
836 } else if (MI->getOpcode() == AMDGPU::CF_ALU) {
837 // If the clause start in the middle of MBB then the MBB has more
838 // than a single clause, unable to predicate several clauses.
839 if (MI->getParent()->begin() != MachineBasicBlock::iterator(MI))
841 // TODO: We don't support KC merging atm
842 if (MI->getOperand(3).getImm() != 0 || MI->getOperand(4).getImm() != 0)
845 } else if (isVector(*MI)) {
848 return AMDGPUInstrInfo::isPredicable(MI);
854 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
856 unsigned ExtraPredCycles,
857 const BranchProbability &Probability) const{
862 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
864 unsigned ExtraTCycles,
865 MachineBasicBlock &FMBB,
867 unsigned ExtraFCycles,
868 const BranchProbability &Probability) const {
873 R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
875 const BranchProbability &Probability)
881 R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
882 MachineBasicBlock &FMBB) const {
888 R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
889 MachineOperand &MO = Cond[1];
890 switch (MO.getImm()) {
891 case OPCODE_IS_ZERO_INT:
892 MO.setImm(OPCODE_IS_NOT_ZERO_INT);
894 case OPCODE_IS_NOT_ZERO_INT:
895 MO.setImm(OPCODE_IS_ZERO_INT);
898 MO.setImm(OPCODE_IS_NOT_ZERO);
900 case OPCODE_IS_NOT_ZERO:
901 MO.setImm(OPCODE_IS_ZERO);
907 MachineOperand &MO2 = Cond[2];
908 switch (MO2.getReg()) {
909 case AMDGPU::PRED_SEL_ZERO:
910 MO2.setReg(AMDGPU::PRED_SEL_ONE);
912 case AMDGPU::PRED_SEL_ONE:
913 MO2.setReg(AMDGPU::PRED_SEL_ZERO);
922 R600InstrInfo::DefinesPredicate(MachineInstr *MI,
923 std::vector<MachineOperand> &Pred) const {
924 return isPredicateSetter(MI->getOpcode());
929 R600InstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
930 const SmallVectorImpl<MachineOperand> &Pred2) const {
936 R600InstrInfo::PredicateInstruction(MachineInstr *MI,
937 const SmallVectorImpl<MachineOperand> &Pred) const {
938 int PIdx = MI->findFirstPredOperandIdx();
940 if (MI->getOpcode() == AMDGPU::CF_ALU) {
941 MI->getOperand(8).setImm(0);
946 MachineOperand &PMO = MI->getOperand(PIdx);
947 PMO.setReg(Pred[2].getReg());
948 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
949 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
956 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
957 const MachineInstr *MI,
958 unsigned *PredCost) const {
964 int R600InstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
965 const MachineRegisterInfo &MRI = MF.getRegInfo();
966 const MachineFrameInfo *MFI = MF.getFrameInfo();
969 if (MFI->getNumObjects() == 0) {
973 if (MRI.livein_empty()) {
977 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
978 LE = MRI.livein_end();
980 Offset = std::max(Offset,
981 GET_REG_INDEX(RI.getEncodingValue(LI->first)));
987 int R600InstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
989 const MachineFrameInfo *MFI = MF.getFrameInfo();
991 // Variable sized objects are not supported
992 assert(!MFI->hasVarSizedObjects());
994 if (MFI->getNumObjects() == 0) {
998 Offset = TM.getFrameLowering()->getFrameIndexOffset(MF, -1);
1000 return getIndirectIndexBegin(MF) + Offset;
1003 std::vector<unsigned> R600InstrInfo::getIndirectReservedRegs(
1004 const MachineFunction &MF) const {
1005 const AMDGPUFrameLowering *TFL =
1006 static_cast<const AMDGPUFrameLowering*>(TM.getFrameLowering());
1007 std::vector<unsigned> Regs;
1009 unsigned StackWidth = TFL->getStackWidth(MF);
1010 int End = getIndirectIndexEnd(MF);
1016 for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) {
1017 unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
1018 Regs.push_back(SuperReg);
1019 for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
1020 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
1021 Regs.push_back(Reg);
1027 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex,
1028 unsigned Channel) const {
1029 // XXX: Remove when we support a stack width > 2
1030 assert(Channel == 0);
1034 const TargetRegisterClass * R600InstrInfo::getIndirectAddrStoreRegClass(
1035 unsigned SourceReg) const {
1036 return &AMDGPU::R600_TReg32RegClass;
1039 const TargetRegisterClass *R600InstrInfo::getIndirectAddrLoadRegClass() const {
1040 return &AMDGPU::TRegMemRegClass;
1043 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
1044 MachineBasicBlock::iterator I,
1045 unsigned ValueReg, unsigned Address,
1046 unsigned OffsetReg) const {
1047 unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
1048 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1049 AMDGPU::AR_X, OffsetReg);
1050 setImmOperand(MOVA, AMDGPU::OpName::write, 0);
1052 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1054 .addReg(AMDGPU::AR_X,
1055 RegState::Implicit | RegState::Kill);
1056 setImmOperand(Mov, AMDGPU::OpName::dst_rel, 1);
1060 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
1061 MachineBasicBlock::iterator I,
1062 unsigned ValueReg, unsigned Address,
1063 unsigned OffsetReg) const {
1064 unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
1065 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1068 setImmOperand(MOVA, AMDGPU::OpName::write, 0);
1069 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1072 .addReg(AMDGPU::AR_X,
1073 RegState::Implicit | RegState::Kill);
1074 setImmOperand(Mov, AMDGPU::OpName::src0_rel, 1);
1079 const TargetRegisterClass *R600InstrInfo::getSuperIndirectRegClass() const {
1080 return &AMDGPU::IndirectRegRegClass;
1083 unsigned R600InstrInfo::getMaxAlusPerClause() const {
1087 MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB,
1088 MachineBasicBlock::iterator I,
1092 unsigned Src1Reg) const {
1093 MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
1097 MIB.addImm(0) // $update_exec_mask
1098 .addImm(0); // $update_predicate
1100 MIB.addImm(1) // $write
1102 .addImm(0) // $dst_rel
1103 .addImm(0) // $dst_clamp
1104 .addReg(Src0Reg) // $src0
1105 .addImm(0) // $src0_neg
1106 .addImm(0) // $src0_rel
1107 .addImm(0) // $src0_abs
1108 .addImm(-1); // $src0_sel
1111 MIB.addReg(Src1Reg) // $src1
1112 .addImm(0) // $src1_neg
1113 .addImm(0) // $src1_rel
1114 .addImm(0) // $src1_abs
1115 .addImm(-1); // $src1_sel
1118 //XXX: The r600g finalizer expects this to be 1, once we've moved the
1119 //scheduling to the backend, we can change the default to 0.
1120 MIB.addImm(1) // $last
1121 .addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
1122 .addImm(0) // $literal
1123 .addImm(0); // $bank_swizzle
1128 #define OPERAND_CASE(Label) \
1130 static const unsigned Ops[] = \
1140 static unsigned getSlotedOps(unsigned Op, unsigned Slot) {
1142 OPERAND_CASE(AMDGPU::OpName::update_exec_mask)
1143 OPERAND_CASE(AMDGPU::OpName::update_pred)
1144 OPERAND_CASE(AMDGPU::OpName::write)
1145 OPERAND_CASE(AMDGPU::OpName::omod)
1146 OPERAND_CASE(AMDGPU::OpName::dst_rel)
1147 OPERAND_CASE(AMDGPU::OpName::clamp)
1148 OPERAND_CASE(AMDGPU::OpName::src0)
1149 OPERAND_CASE(AMDGPU::OpName::src0_neg)
1150 OPERAND_CASE(AMDGPU::OpName::src0_rel)
1151 OPERAND_CASE(AMDGPU::OpName::src0_abs)
1152 OPERAND_CASE(AMDGPU::OpName::src0_sel)
1153 OPERAND_CASE(AMDGPU::OpName::src1)
1154 OPERAND_CASE(AMDGPU::OpName::src1_neg)
1155 OPERAND_CASE(AMDGPU::OpName::src1_rel)
1156 OPERAND_CASE(AMDGPU::OpName::src1_abs)
1157 OPERAND_CASE(AMDGPU::OpName::src1_sel)
1158 OPERAND_CASE(AMDGPU::OpName::pred_sel)
1160 llvm_unreachable("Wrong Operand");
1166 MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction(
1167 MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg)
1169 assert (MI->getOpcode() == AMDGPU::DOT_4 && "Not Implemented");
1171 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
1172 if (ST.getGeneration() <= AMDGPUSubtarget::R700)
1173 Opcode = AMDGPU::DOT4_r600;
1175 Opcode = AMDGPU::DOT4_eg;
1176 MachineBasicBlock::iterator I = MI;
1177 MachineOperand &Src0 = MI->getOperand(
1178 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src0, Slot)));
1179 MachineOperand &Src1 = MI->getOperand(
1180 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src1, Slot)));
1181 MachineInstr *MIB = buildDefaultInstruction(
1182 MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
1183 static const unsigned Operands[14] = {
1184 AMDGPU::OpName::update_exec_mask,
1185 AMDGPU::OpName::update_pred,
1186 AMDGPU::OpName::write,
1187 AMDGPU::OpName::omod,
1188 AMDGPU::OpName::dst_rel,
1189 AMDGPU::OpName::clamp,
1190 AMDGPU::OpName::src0_neg,
1191 AMDGPU::OpName::src0_rel,
1192 AMDGPU::OpName::src0_abs,
1193 AMDGPU::OpName::src0_sel,
1194 AMDGPU::OpName::src1_neg,
1195 AMDGPU::OpName::src1_rel,
1196 AMDGPU::OpName::src1_abs,
1197 AMDGPU::OpName::src1_sel,
1200 for (unsigned i = 0; i < 14; i++) {
1201 MachineOperand &MO = MI->getOperand(
1202 getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));
1203 assert (MO.isImm());
1204 setImmOperand(MIB, Operands[i], MO.getImm());
1206 MIB->getOperand(20).setImm(0);
1210 MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,
1211 MachineBasicBlock::iterator I,
1213 uint64_t Imm) const {
1214 MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg,
1215 AMDGPU::ALU_LITERAL_X);
1216 setImmOperand(MovImm, AMDGPU::OpName::literal, Imm);
1220 int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const {
1221 return getOperandIdx(MI.getOpcode(), Op);
1224 int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const {
1225 return AMDGPU::getNamedOperandIdx(Opcode, Op);
1228 void R600InstrInfo::setImmOperand(MachineInstr *MI, unsigned Op,
1229 int64_t Imm) const {
1230 int Idx = getOperandIdx(*MI, Op);
1231 assert(Idx != -1 && "Operand not supported for this instruction.");
1232 assert(MI->getOperand(Idx).isImm());
1233 MI->getOperand(Idx).setImm(Imm);
1236 //===----------------------------------------------------------------------===//
1237 // Instruction flag getters/setters
1238 //===----------------------------------------------------------------------===//
1240 bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const {
1241 return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
1244 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr *MI, unsigned SrcIdx,
1245 unsigned Flag) const {
1246 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1249 // If we pass something other than the default value of Flag to this
1250 // function, it means we are want to set a flag on an instruction
1251 // that uses native encoding.
1252 assert(HAS_NATIVE_OPERANDS(TargetFlags));
1253 bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3;
1256 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::clamp);
1259 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::write);
1261 case MO_FLAG_NOT_LAST:
1263 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::last);
1267 case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_neg); break;
1268 case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_neg); break;
1269 case 2: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src2_neg); break;
1274 assert(!IsOP3 && "Cannot set absolute value modifier for OP3 "
1278 case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_abs); break;
1279 case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_abs); break;
1287 assert(FlagIndex != -1 && "Flag not supported for this instruction");
1289 FlagIndex = GET_FLAG_OPERAND_IDX(TargetFlags);
1290 assert(FlagIndex != 0 &&
1291 "Instruction flags not supported for this instruction");
1294 MachineOperand &FlagOp = MI->getOperand(FlagIndex);
1295 assert(FlagOp.isImm());
1299 void R600InstrInfo::addFlag(MachineInstr *MI, unsigned Operand,
1300 unsigned Flag) const {
1301 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1305 if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1306 MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1307 if (Flag == MO_FLAG_NOT_LAST) {
1308 clearFlag(MI, Operand, MO_FLAG_LAST);
1309 } else if (Flag == MO_FLAG_MASK) {
1310 clearFlag(MI, Operand, Flag);
1315 MachineOperand &FlagOp = getFlagOp(MI, Operand);
1316 FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
1320 void R600InstrInfo::clearFlag(MachineInstr *MI, unsigned Operand,
1321 unsigned Flag) const {
1322 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1323 if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1324 MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1327 MachineOperand &FlagOp = getFlagOp(MI);
1328 unsigned InstFlags = FlagOp.getImm();
1329 InstFlags &= ~(Flag << (NUM_MO_FLAGS * Operand));
1330 FlagOp.setImm(InstFlags);