1 //===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief R600 Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
15 #include "R600InstrInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "R600Defines.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #define GET_INSTRINFO_CTOR
27 #include "AMDGPUGenDFAPacketizer.inc"
31 R600InstrInfo::R600InstrInfo(AMDGPUTargetMachine &tm)
32 : AMDGPUInstrInfo(tm),
34 ST(tm.getSubtarget<AMDGPUSubtarget>())
37 const R600RegisterInfo &R600InstrInfo::getRegisterInfo() const {
41 bool R600InstrInfo::isTrig(const MachineInstr &MI) const {
42 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
45 bool R600InstrInfo::isVector(const MachineInstr &MI) const {
46 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
50 R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
51 MachineBasicBlock::iterator MI, DebugLoc DL,
52 unsigned DestReg, unsigned SrcReg,
54 unsigned VectorComponents = 0;
55 if (AMDGPU::R600_Reg128RegClass.contains(DestReg) &&
56 AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
58 } else if(AMDGPU::R600_Reg64RegClass.contains(DestReg) &&
59 AMDGPU::R600_Reg64RegClass.contains(SrcReg)) {
63 if (VectorComponents > 0) {
64 for (unsigned I = 0; I < VectorComponents; I++) {
65 unsigned SubRegIndex = RI.getSubRegFromChannel(I);
66 buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
67 RI.getSubReg(DestReg, SubRegIndex),
68 RI.getSubReg(SrcReg, SubRegIndex))
70 RegState::Define | RegState::Implicit);
73 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
75 NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0))
80 MachineInstr * R600InstrInfo::getMovImmInstr(MachineFunction *MF,
81 unsigned DstReg, int64_t Imm) const {
82 MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc());
83 MachineInstrBuilder MIB(*MF, MI);
84 MIB.addReg(DstReg, RegState::Define);
85 MIB.addReg(AMDGPU::ALU_LITERAL_X);
87 MIB.addReg(0); // PREDICATE_BIT
92 unsigned R600InstrInfo::getIEQOpcode() const {
93 return AMDGPU::SETE_INT;
96 bool R600InstrInfo::isMov(unsigned Opcode) const {
100 default: return false;
102 case AMDGPU::MOV_IMM_F32:
103 case AMDGPU::MOV_IMM_I32:
108 // Some instructions act as place holders to emulate operations that the GPU
109 // hardware does automatically. This function can be used to check if
110 // an opcode falls into this category.
111 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const {
113 default: return false;
119 bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
123 bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
125 default: return false;
126 case AMDGPU::CUBE_r600_pseudo:
127 case AMDGPU::CUBE_r600_real:
128 case AMDGPU::CUBE_eg_pseudo:
129 case AMDGPU::CUBE_eg_real:
134 bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
135 unsigned TargetFlags = get(Opcode).TSFlags;
137 return (TargetFlags & R600_InstFlag::ALU_INST);
140 bool R600InstrInfo::hasInstrModifiers(unsigned Opcode) const {
141 unsigned TargetFlags = get(Opcode).TSFlags;
143 return ((TargetFlags & R600_InstFlag::OP1) |
144 (TargetFlags & R600_InstFlag::OP2) |
145 (TargetFlags & R600_InstFlag::OP3));
148 bool R600InstrInfo::isLDSInstr(unsigned Opcode) const {
149 unsigned TargetFlags = get(Opcode).TSFlags;
151 return ((TargetFlags & R600_InstFlag::LDS_1A) |
152 (TargetFlags & R600_InstFlag::LDS_1A1D) |
153 (TargetFlags & R600_InstFlag::LDS_1A2D));
156 bool R600InstrInfo::isTransOnly(unsigned Opcode) const {
157 return (get(Opcode).TSFlags & R600_InstFlag::TRANS_ONLY);
160 bool R600InstrInfo::isTransOnly(const MachineInstr *MI) const {
161 return isTransOnly(MI->getOpcode());
164 bool R600InstrInfo::isExport(unsigned Opcode) const {
165 return (get(Opcode).TSFlags & R600_InstFlag::IS_EXPORT);
168 bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
169 return ST.hasVertexCache() && IS_VTX(get(Opcode));
172 bool R600InstrInfo::usesVertexCache(const MachineInstr *MI) const {
173 const R600MachineFunctionInfo *MFI = MI->getParent()->getParent()->getInfo<R600MachineFunctionInfo>();
174 return MFI->ShaderType != ShaderType::COMPUTE && usesVertexCache(MI->getOpcode());
177 bool R600InstrInfo::usesTextureCache(unsigned Opcode) const {
178 return (!ST.hasVertexCache() && IS_VTX(get(Opcode))) || IS_TEX(get(Opcode));
181 bool R600InstrInfo::usesTextureCache(const MachineInstr *MI) const {
182 const R600MachineFunctionInfo *MFI = MI->getParent()->getParent()->getInfo<R600MachineFunctionInfo>();
183 return (MFI->ShaderType == ShaderType::COMPUTE && usesVertexCache(MI->getOpcode())) ||
184 usesTextureCache(MI->getOpcode());
187 bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const {
190 case AMDGPU::GROUP_BARRIER:
197 int R600InstrInfo::getSrcIdx(unsigned Opcode, unsigned SrcNum) const {
198 static const unsigned OpTable[] = {
199 AMDGPU::OpName::src0,
200 AMDGPU::OpName::src1,
205 return getOperandIdx(Opcode, OpTable[SrcNum]);
208 #define SRC_SEL_ROWS 11
209 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const {
210 static const unsigned SrcSelTable[SRC_SEL_ROWS][2] = {
211 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
212 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
213 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
214 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
215 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
216 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
217 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
218 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
219 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
220 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
221 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W}
224 for (unsigned i = 0; i < SRC_SEL_ROWS; ++i) {
225 if (getOperandIdx(Opcode, SrcSelTable[i][0]) == (int)SrcIdx) {
226 return getOperandIdx(Opcode, SrcSelTable[i][1]);
233 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
234 R600InstrInfo::getSrcs(MachineInstr *MI) const {
235 SmallVector<std::pair<MachineOperand *, int64_t>, 3> Result;
237 if (MI->getOpcode() == AMDGPU::DOT_4) {
238 static const unsigned OpTable[8][2] = {
239 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
240 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
241 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
242 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
243 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
244 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
245 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
246 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W},
249 for (unsigned j = 0; j < 8; j++) {
250 MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
252 unsigned Reg = MO.getReg();
253 if (Reg == AMDGPU::ALU_CONST) {
254 unsigned Sel = MI->getOperand(getOperandIdx(MI->getOpcode(),
255 OpTable[j][1])).getImm();
256 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Sel));
264 static const unsigned OpTable[3][2] = {
265 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
266 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
267 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
270 for (unsigned j = 0; j < 3; j++) {
271 int SrcIdx = getOperandIdx(MI->getOpcode(), OpTable[j][0]);
274 MachineOperand &MO = MI->getOperand(SrcIdx);
275 unsigned Reg = MI->getOperand(SrcIdx).getReg();
276 if (Reg == AMDGPU::ALU_CONST) {
277 unsigned Sel = MI->getOperand(
278 getOperandIdx(MI->getOpcode(), OpTable[j][1])).getImm();
279 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Sel));
282 if (Reg == AMDGPU::ALU_LITERAL_X) {
283 unsigned Imm = MI->getOperand(
284 getOperandIdx(MI->getOpcode(), AMDGPU::OpName::literal)).getImm();
285 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Imm));
288 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, 0));
293 std::vector<std::pair<int, unsigned> >
294 R600InstrInfo::ExtractSrcs(MachineInstr *MI,
295 const DenseMap<unsigned, unsigned> &PV,
296 unsigned &ConstCount) const {
298 const SmallVector<std::pair<MachineOperand *, int64_t>, 3> Srcs = getSrcs(MI);
299 const std::pair<int, unsigned> DummyPair(-1, 0);
300 std::vector<std::pair<int, unsigned> > Result;
302 for (unsigned n = Srcs.size(); i < n; ++i) {
303 unsigned Reg = Srcs[i].first->getReg();
304 unsigned Index = RI.getEncodingValue(Reg) & 0xff;
305 if (Reg == AMDGPU::OQAP) {
306 Result.push_back(std::pair<int, unsigned>(Index, 0));
308 if (PV.find(Reg) != PV.end()) {
309 // 255 is used to tells its a PS/PV reg
310 Result.push_back(std::pair<int, unsigned>(255, 0));
315 Result.push_back(DummyPair);
318 unsigned Chan = RI.getHWRegChan(Reg);
319 Result.push_back(std::pair<int, unsigned>(Index, Chan));
322 Result.push_back(DummyPair);
326 static std::vector<std::pair<int, unsigned> >
327 Swizzle(std::vector<std::pair<int, unsigned> > Src,
328 R600InstrInfo::BankSwizzle Swz) {
330 case R600InstrInfo::ALU_VEC_012_SCL_210:
332 case R600InstrInfo::ALU_VEC_021_SCL_122:
333 std::swap(Src[1], Src[2]);
335 case R600InstrInfo::ALU_VEC_102_SCL_221:
336 std::swap(Src[0], Src[1]);
338 case R600InstrInfo::ALU_VEC_120_SCL_212:
339 std::swap(Src[0], Src[1]);
340 std::swap(Src[0], Src[2]);
342 case R600InstrInfo::ALU_VEC_201:
343 std::swap(Src[0], Src[2]);
344 std::swap(Src[0], Src[1]);
346 case R600InstrInfo::ALU_VEC_210:
347 std::swap(Src[0], Src[2]);
354 getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) {
356 case R600InstrInfo::ALU_VEC_012_SCL_210: {
357 unsigned Cycles[3] = { 2, 1, 0};
360 case R600InstrInfo::ALU_VEC_021_SCL_122: {
361 unsigned Cycles[3] = { 1, 2, 2};
364 case R600InstrInfo::ALU_VEC_120_SCL_212: {
365 unsigned Cycles[3] = { 2, 1, 2};
368 case R600InstrInfo::ALU_VEC_102_SCL_221: {
369 unsigned Cycles[3] = { 2, 2, 1};
373 llvm_unreachable("Wrong Swizzle for Trans Slot");
378 /// returns how many MIs (whose inputs are represented by IGSrcs) can be packed
379 /// in the same Instruction Group while meeting read port limitations given a
380 /// Swz swizzle sequence.
381 unsigned R600InstrInfo::isLegalUpTo(
382 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
383 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
384 const std::vector<std::pair<int, unsigned> > &TransSrcs,
385 R600InstrInfo::BankSwizzle TransSwz) const {
387 memset(Vector, -1, sizeof(Vector));
388 for (unsigned i = 0, e = IGSrcs.size(); i < e; i++) {
389 const std::vector<std::pair<int, unsigned> > &Srcs =
390 Swizzle(IGSrcs[i], Swz[i]);
391 for (unsigned j = 0; j < 3; j++) {
392 const std::pair<int, unsigned> &Src = Srcs[j];
393 if (Src.first < 0 || Src.first == 255)
395 if (Src.first == GET_REG_INDEX(RI.getEncodingValue(AMDGPU::OQAP))) {
396 if (Swz[i] != R600InstrInfo::ALU_VEC_012_SCL_210 &&
397 Swz[i] != R600InstrInfo::ALU_VEC_021_SCL_122) {
398 // The value from output queue A (denoted by register OQAP) can
399 // only be fetched during the first cycle.
402 // OQAP does not count towards the normal read port restrictions
405 if (Vector[Src.second][j] < 0)
406 Vector[Src.second][j] = Src.first;
407 if (Vector[Src.second][j] != Src.first)
411 // Now check Trans Alu
412 for (unsigned i = 0, e = TransSrcs.size(); i < e; ++i) {
413 const std::pair<int, unsigned> &Src = TransSrcs[i];
414 unsigned Cycle = getTransSwizzle(TransSwz, i);
417 if (Src.first == 255)
419 if (Vector[Src.second][Cycle] < 0)
420 Vector[Src.second][Cycle] = Src.first;
421 if (Vector[Src.second][Cycle] != Src.first)
422 return IGSrcs.size() - 1;
424 return IGSrcs.size();
427 /// Given a swizzle sequence SwzCandidate and an index Idx, returns the next
428 /// (in lexicographic term) swizzle sequence assuming that all swizzles after
429 /// Idx can be skipped
431 NextPossibleSolution(
432 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
434 assert(Idx < SwzCandidate.size());
436 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210)
438 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) {
439 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210;
443 int NextSwizzle = SwzCandidate[ResetIdx] + 1;
444 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle;
448 /// Enumerate all possible Swizzle sequence to find one that can meet all
449 /// read port requirements.
450 bool R600InstrInfo::FindSwizzleForVectorSlot(
451 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
452 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
453 const std::vector<std::pair<int, unsigned> > &TransSrcs,
454 R600InstrInfo::BankSwizzle TransSwz) const {
455 unsigned ValidUpTo = 0;
457 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz);
458 if (ValidUpTo == IGSrcs.size())
460 } while (NextPossibleSolution(SwzCandidate, ValidUpTo));
464 /// Instructions in Trans slot can't read gpr at cycle 0 if they also read
465 /// a const, and can't read a gpr at cycle 1 if they read 2 const.
467 isConstCompatible(R600InstrInfo::BankSwizzle TransSwz,
468 const std::vector<std::pair<int, unsigned> > &TransOps,
469 unsigned ConstCount) {
470 for (unsigned i = 0, e = TransOps.size(); i < e; ++i) {
471 const std::pair<int, unsigned> &Src = TransOps[i];
472 unsigned Cycle = getTransSwizzle(TransSwz, i);
475 if (ConstCount > 0 && Cycle == 0)
477 if (ConstCount > 1 && Cycle == 1)
484 R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,
485 const DenseMap<unsigned, unsigned> &PV,
486 std::vector<BankSwizzle> &ValidSwizzle,
489 //Todo : support shared src0 - src1 operand
491 std::vector<std::vector<std::pair<int, unsigned> > > IGSrcs;
492 ValidSwizzle.clear();
494 BankSwizzle TransBS = ALU_VEC_012_SCL_210;
495 for (unsigned i = 0, e = IG.size(); i < e; ++i) {
496 IGSrcs.push_back(ExtractSrcs(IG[i], PV, ConstCount));
497 unsigned Op = getOperandIdx(IG[i]->getOpcode(),
498 AMDGPU::OpName::bank_swizzle);
499 ValidSwizzle.push_back( (R600InstrInfo::BankSwizzle)
500 IG[i]->getOperand(Op).getImm());
502 std::vector<std::pair<int, unsigned> > TransOps;
504 return FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps, TransBS);
506 TransOps = IGSrcs.back();
508 ValidSwizzle.pop_back();
510 static const R600InstrInfo::BankSwizzle TransSwz[] = {
516 for (unsigned i = 0; i < 4; i++) {
517 TransBS = TransSwz[i];
518 if (!isConstCompatible(TransBS, TransOps, ConstCount))
520 bool Result = FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps,
523 ValidSwizzle.push_back(TransBS);
533 R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts)
535 assert (Consts.size() <= 12 && "Too many operands in instructions group");
536 unsigned Pair1 = 0, Pair2 = 0;
537 for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
538 unsigned ReadConstHalf = Consts[i] & 2;
539 unsigned ReadConstIndex = Consts[i] & (~3);
540 unsigned ReadHalfConst = ReadConstIndex | ReadConstHalf;
542 Pair1 = ReadHalfConst;
545 if (Pair1 == ReadHalfConst)
548 Pair2 = ReadHalfConst;
551 if (Pair2 != ReadHalfConst)
558 R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs)
560 std::vector<unsigned> Consts;
561 SmallSet<int64_t, 4> Literals;
562 for (unsigned i = 0, n = MIs.size(); i < n; i++) {
563 MachineInstr *MI = MIs[i];
564 if (!isALUInstr(MI->getOpcode()))
567 const SmallVectorImpl<std::pair<MachineOperand *, int64_t> > &Srcs =
570 for (unsigned j = 0, e = Srcs.size(); j < e; j++) {
571 std::pair<MachineOperand *, unsigned> Src = Srcs[j];
572 if (Src.first->getReg() == AMDGPU::ALU_LITERAL_X)
573 Literals.insert(Src.second);
574 if (Literals.size() > 4)
576 if (Src.first->getReg() == AMDGPU::ALU_CONST)
577 Consts.push_back(Src.second);
578 if (AMDGPU::R600_KC0RegClass.contains(Src.first->getReg()) ||
579 AMDGPU::R600_KC1RegClass.contains(Src.first->getReg())) {
580 unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
581 unsigned Chan = RI.getHWRegChan(Src.first->getReg());
582 Consts.push_back((Index << 2) | Chan);
586 return fitsConstReadLimitations(Consts);
589 DFAPacketizer *R600InstrInfo::CreateTargetScheduleState(const TargetMachine *TM,
590 const ScheduleDAG *DAG) const {
591 const InstrItineraryData *II = TM->getInstrItineraryData();
592 return TM->getSubtarget<AMDGPUSubtarget>().createDFAPacketizer(II);
596 isPredicateSetter(unsigned Opcode) {
605 static MachineInstr *
606 findFirstPredicateSetterFrom(MachineBasicBlock &MBB,
607 MachineBasicBlock::iterator I) {
608 while (I != MBB.begin()) {
610 MachineInstr *MI = I;
611 if (isPredicateSetter(MI->getOpcode()))
619 bool isJump(unsigned Opcode) {
620 return Opcode == AMDGPU::JUMP || Opcode == AMDGPU::JUMP_COND;
624 R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
625 MachineBasicBlock *&TBB,
626 MachineBasicBlock *&FBB,
627 SmallVectorImpl<MachineOperand> &Cond,
628 bool AllowModify) const {
629 // Most of the following comes from the ARM implementation of AnalyzeBranch
631 // If the block has no terminators, it just falls into the block after it.
632 MachineBasicBlock::iterator I = MBB.end();
633 if (I == MBB.begin())
636 while (I->isDebugValue()) {
637 if (I == MBB.begin())
641 if (!isJump(static_cast<MachineInstr *>(I)->getOpcode())) {
645 // Get the last instruction in the block.
646 MachineInstr *LastInst = I;
648 // If there is only one terminator instruction, process it.
649 unsigned LastOpc = LastInst->getOpcode();
650 if (I == MBB.begin() ||
651 !isJump(static_cast<MachineInstr *>(--I)->getOpcode())) {
652 if (LastOpc == AMDGPU::JUMP) {
653 TBB = LastInst->getOperand(0).getMBB();
655 } else if (LastOpc == AMDGPU::JUMP_COND) {
656 MachineInstr *predSet = I;
657 while (!isPredicateSetter(predSet->getOpcode())) {
660 TBB = LastInst->getOperand(0).getMBB();
661 Cond.push_back(predSet->getOperand(1));
662 Cond.push_back(predSet->getOperand(2));
663 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
666 return true; // Can't handle indirect branch.
669 // Get the instruction before it if it is a terminator.
670 MachineInstr *SecondLastInst = I;
671 unsigned SecondLastOpc = SecondLastInst->getOpcode();
673 // If the block ends with a B and a Bcc, handle it.
674 if (SecondLastOpc == AMDGPU::JUMP_COND && LastOpc == AMDGPU::JUMP) {
675 MachineInstr *predSet = --I;
676 while (!isPredicateSetter(predSet->getOpcode())) {
679 TBB = SecondLastInst->getOperand(0).getMBB();
680 FBB = LastInst->getOperand(0).getMBB();
681 Cond.push_back(predSet->getOperand(1));
682 Cond.push_back(predSet->getOperand(2));
683 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
687 // Otherwise, can't handle this.
691 int R600InstrInfo::getBranchInstr(const MachineOperand &op) const {
692 const MachineInstr *MI = op.getParent();
694 switch (MI->getDesc().OpInfo->RegClass) {
695 default: // FIXME: fallthrough??
696 case AMDGPU::GPRI32RegClassID: return AMDGPU::BRANCH_COND_i32;
697 case AMDGPU::GPRF32RegClassID: return AMDGPU::BRANCH_COND_f32;
702 MachineBasicBlock::iterator FindLastAluClause(MachineBasicBlock &MBB) {
703 for (MachineBasicBlock::reverse_iterator It = MBB.rbegin(), E = MBB.rend();
705 if (It->getOpcode() == AMDGPU::CF_ALU ||
706 It->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE)
707 return llvm::prior(It.base());
713 R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
714 MachineBasicBlock *TBB,
715 MachineBasicBlock *FBB,
716 const SmallVectorImpl<MachineOperand> &Cond,
718 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
722 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB);
725 MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
726 assert(PredSet && "No previous predicate !");
727 addFlag(PredSet, 0, MO_FLAG_PUSH);
728 PredSet->getOperand(2).setImm(Cond[1].getImm());
730 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
732 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
733 MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
734 if (CfAlu == MBB.end())
736 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
737 CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
741 MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
742 assert(PredSet && "No previous predicate !");
743 addFlag(PredSet, 0, MO_FLAG_PUSH);
744 PredSet->getOperand(2).setImm(Cond[1].getImm());
745 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
747 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
748 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB);
749 MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
750 if (CfAlu == MBB.end())
752 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
753 CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
759 R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
761 // Note : we leave PRED* instructions there.
762 // They may be needed when predicating instructions.
764 MachineBasicBlock::iterator I = MBB.end();
766 if (I == MBB.begin()) {
770 switch (I->getOpcode()) {
773 case AMDGPU::JUMP_COND: {
774 MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
775 clearFlag(predSet, 0, MO_FLAG_PUSH);
776 I->eraseFromParent();
777 MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
778 if (CfAlu == MBB.end())
780 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
781 CfAlu->setDesc(get(AMDGPU::CF_ALU));
785 I->eraseFromParent();
790 if (I == MBB.begin()) {
794 switch (I->getOpcode()) {
795 // FIXME: only one case??
798 case AMDGPU::JUMP_COND: {
799 MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
800 clearFlag(predSet, 0, MO_FLAG_PUSH);
801 I->eraseFromParent();
802 MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
803 if (CfAlu == MBB.end())
805 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
806 CfAlu->setDesc(get(AMDGPU::CF_ALU));
810 I->eraseFromParent();
817 R600InstrInfo::isPredicated(const MachineInstr *MI) const {
818 int idx = MI->findFirstPredOperandIdx();
822 unsigned Reg = MI->getOperand(idx).getReg();
824 default: return false;
825 case AMDGPU::PRED_SEL_ONE:
826 case AMDGPU::PRED_SEL_ZERO:
827 case AMDGPU::PREDICATE_BIT:
833 R600InstrInfo::isPredicable(MachineInstr *MI) const {
834 // XXX: KILL* instructions can be predicated, but they must be the last
835 // instruction in a clause, so this means any instructions after them cannot
836 // be predicated. Until we have proper support for instruction clauses in the
837 // backend, we will mark KILL* instructions as unpredicable.
839 if (MI->getOpcode() == AMDGPU::KILLGT) {
841 } else if (MI->getOpcode() == AMDGPU::CF_ALU) {
842 // If the clause start in the middle of MBB then the MBB has more
843 // than a single clause, unable to predicate several clauses.
844 if (MI->getParent()->begin() != MachineBasicBlock::iterator(MI))
846 // TODO: We don't support KC merging atm
847 if (MI->getOperand(3).getImm() != 0 || MI->getOperand(4).getImm() != 0)
850 } else if (isVector(*MI)) {
853 return AMDGPUInstrInfo::isPredicable(MI);
859 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
861 unsigned ExtraPredCycles,
862 const BranchProbability &Probability) const{
867 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
869 unsigned ExtraTCycles,
870 MachineBasicBlock &FMBB,
872 unsigned ExtraFCycles,
873 const BranchProbability &Probability) const {
878 R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
880 const BranchProbability &Probability)
886 R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
887 MachineBasicBlock &FMBB) const {
893 R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
894 MachineOperand &MO = Cond[1];
895 switch (MO.getImm()) {
896 case OPCODE_IS_ZERO_INT:
897 MO.setImm(OPCODE_IS_NOT_ZERO_INT);
899 case OPCODE_IS_NOT_ZERO_INT:
900 MO.setImm(OPCODE_IS_ZERO_INT);
903 MO.setImm(OPCODE_IS_NOT_ZERO);
905 case OPCODE_IS_NOT_ZERO:
906 MO.setImm(OPCODE_IS_ZERO);
912 MachineOperand &MO2 = Cond[2];
913 switch (MO2.getReg()) {
914 case AMDGPU::PRED_SEL_ZERO:
915 MO2.setReg(AMDGPU::PRED_SEL_ONE);
917 case AMDGPU::PRED_SEL_ONE:
918 MO2.setReg(AMDGPU::PRED_SEL_ZERO);
927 R600InstrInfo::DefinesPredicate(MachineInstr *MI,
928 std::vector<MachineOperand> &Pred) const {
929 return isPredicateSetter(MI->getOpcode());
934 R600InstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
935 const SmallVectorImpl<MachineOperand> &Pred2) const {
941 R600InstrInfo::PredicateInstruction(MachineInstr *MI,
942 const SmallVectorImpl<MachineOperand> &Pred) const {
943 int PIdx = MI->findFirstPredOperandIdx();
945 if (MI->getOpcode() == AMDGPU::CF_ALU) {
946 MI->getOperand(8).setImm(0);
951 MachineOperand &PMO = MI->getOperand(PIdx);
952 PMO.setReg(Pred[2].getReg());
953 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
954 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
961 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
962 const MachineInstr *MI,
963 unsigned *PredCost) const {
969 int R600InstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
970 const MachineRegisterInfo &MRI = MF.getRegInfo();
971 const MachineFrameInfo *MFI = MF.getFrameInfo();
974 if (MFI->getNumObjects() == 0) {
978 if (MRI.livein_empty()) {
982 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
983 LE = MRI.livein_end();
985 Offset = std::max(Offset,
986 GET_REG_INDEX(RI.getEncodingValue(LI->first)));
992 int R600InstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
994 const MachineFrameInfo *MFI = MF.getFrameInfo();
996 // Variable sized objects are not supported
997 assert(!MFI->hasVarSizedObjects());
999 if (MFI->getNumObjects() == 0) {
1003 Offset = TM.getFrameLowering()->getFrameIndexOffset(MF, -1);
1005 return getIndirectIndexBegin(MF) + Offset;
1008 std::vector<unsigned> R600InstrInfo::getIndirectReservedRegs(
1009 const MachineFunction &MF) const {
1010 const AMDGPUFrameLowering *TFL =
1011 static_cast<const AMDGPUFrameLowering*>(TM.getFrameLowering());
1012 std::vector<unsigned> Regs;
1014 unsigned StackWidth = TFL->getStackWidth(MF);
1015 int End = getIndirectIndexEnd(MF);
1021 for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) {
1022 unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
1023 Regs.push_back(SuperReg);
1024 for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
1025 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
1026 Regs.push_back(Reg);
1032 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex,
1033 unsigned Channel) const {
1034 // XXX: Remove when we support a stack width > 2
1035 assert(Channel == 0);
1039 const TargetRegisterClass * R600InstrInfo::getIndirectAddrStoreRegClass(
1040 unsigned SourceReg) const {
1041 return &AMDGPU::R600_TReg32RegClass;
1044 const TargetRegisterClass *R600InstrInfo::getIndirectAddrLoadRegClass() const {
1045 return &AMDGPU::TRegMemRegClass;
1048 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
1049 MachineBasicBlock::iterator I,
1050 unsigned ValueReg, unsigned Address,
1051 unsigned OffsetReg) const {
1052 unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
1053 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1054 AMDGPU::AR_X, OffsetReg);
1055 setImmOperand(MOVA, AMDGPU::OpName::write, 0);
1057 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1059 .addReg(AMDGPU::AR_X,
1060 RegState::Implicit | RegState::Kill);
1061 setImmOperand(Mov, AMDGPU::OpName::dst_rel, 1);
1065 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
1066 MachineBasicBlock::iterator I,
1067 unsigned ValueReg, unsigned Address,
1068 unsigned OffsetReg) const {
1069 unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
1070 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1073 setImmOperand(MOVA, AMDGPU::OpName::write, 0);
1074 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1077 .addReg(AMDGPU::AR_X,
1078 RegState::Implicit | RegState::Kill);
1079 setImmOperand(Mov, AMDGPU::OpName::src0_rel, 1);
1084 const TargetRegisterClass *R600InstrInfo::getSuperIndirectRegClass() const {
1085 return &AMDGPU::IndirectRegRegClass;
1088 unsigned R600InstrInfo::getMaxAlusPerClause() const {
1092 MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB,
1093 MachineBasicBlock::iterator I,
1097 unsigned Src1Reg) const {
1098 MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
1102 MIB.addImm(0) // $update_exec_mask
1103 .addImm(0); // $update_predicate
1105 MIB.addImm(1) // $write
1107 .addImm(0) // $dst_rel
1108 .addImm(0) // $dst_clamp
1109 .addReg(Src0Reg) // $src0
1110 .addImm(0) // $src0_neg
1111 .addImm(0) // $src0_rel
1112 .addImm(0) // $src0_abs
1113 .addImm(-1); // $src0_sel
1116 MIB.addReg(Src1Reg) // $src1
1117 .addImm(0) // $src1_neg
1118 .addImm(0) // $src1_rel
1119 .addImm(0) // $src1_abs
1120 .addImm(-1); // $src1_sel
1123 //XXX: The r600g finalizer expects this to be 1, once we've moved the
1124 //scheduling to the backend, we can change the default to 0.
1125 MIB.addImm(1) // $last
1126 .addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
1127 .addImm(0) // $literal
1128 .addImm(0); // $bank_swizzle
1133 #define OPERAND_CASE(Label) \
1135 static const unsigned Ops[] = \
1145 static unsigned getSlotedOps(unsigned Op, unsigned Slot) {
1147 OPERAND_CASE(AMDGPU::OpName::update_exec_mask)
1148 OPERAND_CASE(AMDGPU::OpName::update_pred)
1149 OPERAND_CASE(AMDGPU::OpName::write)
1150 OPERAND_CASE(AMDGPU::OpName::omod)
1151 OPERAND_CASE(AMDGPU::OpName::dst_rel)
1152 OPERAND_CASE(AMDGPU::OpName::clamp)
1153 OPERAND_CASE(AMDGPU::OpName::src0)
1154 OPERAND_CASE(AMDGPU::OpName::src0_neg)
1155 OPERAND_CASE(AMDGPU::OpName::src0_rel)
1156 OPERAND_CASE(AMDGPU::OpName::src0_abs)
1157 OPERAND_CASE(AMDGPU::OpName::src0_sel)
1158 OPERAND_CASE(AMDGPU::OpName::src1)
1159 OPERAND_CASE(AMDGPU::OpName::src1_neg)
1160 OPERAND_CASE(AMDGPU::OpName::src1_rel)
1161 OPERAND_CASE(AMDGPU::OpName::src1_abs)
1162 OPERAND_CASE(AMDGPU::OpName::src1_sel)
1163 OPERAND_CASE(AMDGPU::OpName::pred_sel)
1165 llvm_unreachable("Wrong Operand");
1171 MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction(
1172 MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg)
1174 assert (MI->getOpcode() == AMDGPU::DOT_4 && "Not Implemented");
1176 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
1177 if (ST.getGeneration() <= AMDGPUSubtarget::R700)
1178 Opcode = AMDGPU::DOT4_r600;
1180 Opcode = AMDGPU::DOT4_eg;
1181 MachineBasicBlock::iterator I = MI;
1182 MachineOperand &Src0 = MI->getOperand(
1183 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src0, Slot)));
1184 MachineOperand &Src1 = MI->getOperand(
1185 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src1, Slot)));
1186 MachineInstr *MIB = buildDefaultInstruction(
1187 MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
1188 static const unsigned Operands[14] = {
1189 AMDGPU::OpName::update_exec_mask,
1190 AMDGPU::OpName::update_pred,
1191 AMDGPU::OpName::write,
1192 AMDGPU::OpName::omod,
1193 AMDGPU::OpName::dst_rel,
1194 AMDGPU::OpName::clamp,
1195 AMDGPU::OpName::src0_neg,
1196 AMDGPU::OpName::src0_rel,
1197 AMDGPU::OpName::src0_abs,
1198 AMDGPU::OpName::src0_sel,
1199 AMDGPU::OpName::src1_neg,
1200 AMDGPU::OpName::src1_rel,
1201 AMDGPU::OpName::src1_abs,
1202 AMDGPU::OpName::src1_sel,
1205 for (unsigned i = 0; i < 14; i++) {
1206 MachineOperand &MO = MI->getOperand(
1207 getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));
1208 assert (MO.isImm());
1209 setImmOperand(MIB, Operands[i], MO.getImm());
1211 MIB->getOperand(20).setImm(0);
1215 MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,
1216 MachineBasicBlock::iterator I,
1218 uint64_t Imm) const {
1219 MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg,
1220 AMDGPU::ALU_LITERAL_X);
1221 setImmOperand(MovImm, AMDGPU::OpName::literal, Imm);
1225 int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const {
1226 return getOperandIdx(MI.getOpcode(), Op);
1229 int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const {
1230 return AMDGPU::getNamedOperandIdx(Opcode, Op);
1233 void R600InstrInfo::setImmOperand(MachineInstr *MI, unsigned Op,
1234 int64_t Imm) const {
1235 int Idx = getOperandIdx(*MI, Op);
1236 assert(Idx != -1 && "Operand not supported for this instruction.");
1237 assert(MI->getOperand(Idx).isImm());
1238 MI->getOperand(Idx).setImm(Imm);
1241 //===----------------------------------------------------------------------===//
1242 // Instruction flag getters/setters
1243 //===----------------------------------------------------------------------===//
1245 bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const {
1246 return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
1249 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr *MI, unsigned SrcIdx,
1250 unsigned Flag) const {
1251 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1254 // If we pass something other than the default value of Flag to this
1255 // function, it means we are want to set a flag on an instruction
1256 // that uses native encoding.
1257 assert(HAS_NATIVE_OPERANDS(TargetFlags));
1258 bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3;
1261 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::clamp);
1264 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::write);
1266 case MO_FLAG_NOT_LAST:
1268 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::last);
1272 case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_neg); break;
1273 case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_neg); break;
1274 case 2: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src2_neg); break;
1279 assert(!IsOP3 && "Cannot set absolute value modifier for OP3 "
1283 case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_abs); break;
1284 case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_abs); break;
1292 assert(FlagIndex != -1 && "Flag not supported for this instruction");
1294 FlagIndex = GET_FLAG_OPERAND_IDX(TargetFlags);
1295 assert(FlagIndex != 0 &&
1296 "Instruction flags not supported for this instruction");
1299 MachineOperand &FlagOp = MI->getOperand(FlagIndex);
1300 assert(FlagOp.isImm());
1304 void R600InstrInfo::addFlag(MachineInstr *MI, unsigned Operand,
1305 unsigned Flag) const {
1306 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1310 if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1311 MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1312 if (Flag == MO_FLAG_NOT_LAST) {
1313 clearFlag(MI, Operand, MO_FLAG_LAST);
1314 } else if (Flag == MO_FLAG_MASK) {
1315 clearFlag(MI, Operand, Flag);
1320 MachineOperand &FlagOp = getFlagOp(MI, Operand);
1321 FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
1325 void R600InstrInfo::clearFlag(MachineInstr *MI, unsigned Operand,
1326 unsigned Flag) const {
1327 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1328 if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1329 MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1332 MachineOperand &FlagOp = getFlagOp(MI);
1333 unsigned InstFlags = FlagOp.getImm();
1334 InstFlags &= ~(Flag << (NUM_MO_FLAGS * Operand));
1335 FlagOp.setImm(InstFlags);