1 //===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief R600 Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
15 #include "R600InstrInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "R600Defines.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "AMDGPUGenDFAPacketizer.inc"
31 R600InstrInfo::R600InstrInfo(const AMDGPUSubtarget &st)
32 : AMDGPUInstrInfo(st),
36 const R600RegisterInfo &R600InstrInfo::getRegisterInfo() const {
40 bool R600InstrInfo::isTrig(const MachineInstr &MI) const {
41 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
44 bool R600InstrInfo::isVector(const MachineInstr &MI) const {
45 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
49 R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MI, DebugLoc DL,
51 unsigned DestReg, unsigned SrcReg,
53 unsigned VectorComponents = 0;
54 if ((AMDGPU::R600_Reg128RegClass.contains(DestReg) ||
55 AMDGPU::R600_Reg128VerticalRegClass.contains(DestReg)) &&
56 (AMDGPU::R600_Reg128RegClass.contains(SrcReg) ||
57 AMDGPU::R600_Reg128VerticalRegClass.contains(SrcReg))) {
59 } else if((AMDGPU::R600_Reg64RegClass.contains(DestReg) ||
60 AMDGPU::R600_Reg64VerticalRegClass.contains(DestReg)) &&
61 (AMDGPU::R600_Reg64RegClass.contains(SrcReg) ||
62 AMDGPU::R600_Reg64VerticalRegClass.contains(SrcReg))) {
66 if (VectorComponents > 0) {
67 for (unsigned I = 0; I < VectorComponents; I++) {
68 unsigned SubRegIndex = RI.getSubRegFromChannel(I);
69 buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
70 RI.getSubReg(DestReg, SubRegIndex),
71 RI.getSubReg(SrcReg, SubRegIndex))
73 RegState::Define | RegState::Implicit);
76 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
78 NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0))
83 /// \returns true if \p MBBI can be moved into a new basic.
84 bool R600InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
85 MachineBasicBlock::iterator MBBI) const {
86 for (MachineInstr::const_mop_iterator I = MBBI->operands_begin(),
87 E = MBBI->operands_end(); I != E; ++I) {
88 if (I->isReg() && !TargetRegisterInfo::isVirtualRegister(I->getReg()) &&
89 I->isUse() && RI.isPhysRegLiveAcrossClauses(I->getReg()))
95 unsigned R600InstrInfo::getIEQOpcode() const {
96 return AMDGPU::SETE_INT;
99 bool R600InstrInfo::isMov(unsigned Opcode) const {
103 default: return false;
105 case AMDGPU::MOV_IMM_F32:
106 case AMDGPU::MOV_IMM_I32:
111 // Some instructions act as place holders to emulate operations that the GPU
112 // hardware does automatically. This function can be used to check if
113 // an opcode falls into this category.
114 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const {
116 default: return false;
122 bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
126 bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
128 default: return false;
129 case AMDGPU::CUBE_r600_pseudo:
130 case AMDGPU::CUBE_r600_real:
131 case AMDGPU::CUBE_eg_pseudo:
132 case AMDGPU::CUBE_eg_real:
137 bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
138 unsigned TargetFlags = get(Opcode).TSFlags;
140 return (TargetFlags & R600_InstFlag::ALU_INST);
143 bool R600InstrInfo::hasInstrModifiers(unsigned Opcode) const {
144 unsigned TargetFlags = get(Opcode).TSFlags;
146 return ((TargetFlags & R600_InstFlag::OP1) |
147 (TargetFlags & R600_InstFlag::OP2) |
148 (TargetFlags & R600_InstFlag::OP3));
151 bool R600InstrInfo::isLDSInstr(unsigned Opcode) const {
152 unsigned TargetFlags = get(Opcode).TSFlags;
154 return ((TargetFlags & R600_InstFlag::LDS_1A) |
155 (TargetFlags & R600_InstFlag::LDS_1A1D) |
156 (TargetFlags & R600_InstFlag::LDS_1A2D));
159 bool R600InstrInfo::isLDSNoRetInstr(unsigned Opcode) const {
160 return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) == -1;
163 bool R600InstrInfo::isLDSRetInstr(unsigned Opcode) const {
164 return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) != -1;
167 bool R600InstrInfo::canBeConsideredALU(const MachineInstr *MI) const {
168 if (isALUInstr(MI->getOpcode()))
170 if (isVector(*MI) || isCubeOp(MI->getOpcode()))
172 switch (MI->getOpcode()) {
174 case AMDGPU::INTERP_PAIR_XY:
175 case AMDGPU::INTERP_PAIR_ZW:
176 case AMDGPU::INTERP_VEC_LOAD:
185 bool R600InstrInfo::isTransOnly(unsigned Opcode) const {
186 if (ST.hasCaymanISA())
188 return (get(Opcode).getSchedClass() == AMDGPU::Sched::TransALU);
191 bool R600InstrInfo::isTransOnly(const MachineInstr *MI) const {
192 return isTransOnly(MI->getOpcode());
195 bool R600InstrInfo::isVectorOnly(unsigned Opcode) const {
196 return (get(Opcode).getSchedClass() == AMDGPU::Sched::VecALU);
199 bool R600InstrInfo::isVectorOnly(const MachineInstr *MI) const {
200 return isVectorOnly(MI->getOpcode());
203 bool R600InstrInfo::isExport(unsigned Opcode) const {
204 return (get(Opcode).TSFlags & R600_InstFlag::IS_EXPORT);
207 bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
208 return ST.hasVertexCache() && IS_VTX(get(Opcode));
211 bool R600InstrInfo::usesVertexCache(const MachineInstr *MI) const {
212 const MachineFunction *MF = MI->getParent()->getParent();
213 const R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
214 return MFI->getShaderType() != ShaderType::COMPUTE &&
215 usesVertexCache(MI->getOpcode());
218 bool R600InstrInfo::usesTextureCache(unsigned Opcode) const {
219 return (!ST.hasVertexCache() && IS_VTX(get(Opcode))) || IS_TEX(get(Opcode));
222 bool R600InstrInfo::usesTextureCache(const MachineInstr *MI) const {
223 const MachineFunction *MF = MI->getParent()->getParent();
224 const R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
225 return (MFI->getShaderType() == ShaderType::COMPUTE &&
226 usesVertexCache(MI->getOpcode())) ||
227 usesTextureCache(MI->getOpcode());
230 bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const {
233 case AMDGPU::GROUP_BARRIER:
240 bool R600InstrInfo::usesAddressRegister(MachineInstr *MI) const {
241 return MI->findRegisterUseOperandIdx(AMDGPU::AR_X) != -1;
244 bool R600InstrInfo::definesAddressRegister(MachineInstr *MI) const {
245 return MI->findRegisterDefOperandIdx(AMDGPU::AR_X) != -1;
248 bool R600InstrInfo::readsLDSSrcReg(const MachineInstr *MI) const {
249 if (!isALUInstr(MI->getOpcode())) {
252 for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
253 E = MI->operands_end(); I != E; ++I) {
254 if (!I->isReg() || !I->isUse() ||
255 TargetRegisterInfo::isVirtualRegister(I->getReg()))
258 if (AMDGPU::R600_LDS_SRC_REGRegClass.contains(I->getReg()))
264 int R600InstrInfo::getSrcIdx(unsigned Opcode, unsigned SrcNum) const {
265 static const unsigned OpTable[] = {
266 AMDGPU::OpName::src0,
267 AMDGPU::OpName::src1,
272 return getOperandIdx(Opcode, OpTable[SrcNum]);
275 #define SRC_SEL_ROWS 11
276 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const {
277 static const unsigned SrcSelTable[SRC_SEL_ROWS][2] = {
278 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
279 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
280 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
281 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
282 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
283 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
284 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
285 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
286 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
287 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
288 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W}
291 for (unsigned i = 0; i < SRC_SEL_ROWS; ++i) {
292 if (getOperandIdx(Opcode, SrcSelTable[i][0]) == (int)SrcIdx) {
293 return getOperandIdx(Opcode, SrcSelTable[i][1]);
300 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
301 R600InstrInfo::getSrcs(MachineInstr *MI) const {
302 SmallVector<std::pair<MachineOperand *, int64_t>, 3> Result;
304 if (MI->getOpcode() == AMDGPU::DOT_4) {
305 static const unsigned OpTable[8][2] = {
306 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
307 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
308 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
309 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
310 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
311 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
312 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
313 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W},
316 for (unsigned j = 0; j < 8; j++) {
317 MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
319 unsigned Reg = MO.getReg();
320 if (Reg == AMDGPU::ALU_CONST) {
321 unsigned Sel = MI->getOperand(getOperandIdx(MI->getOpcode(),
322 OpTable[j][1])).getImm();
323 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Sel));
331 static const unsigned OpTable[3][2] = {
332 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
333 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
334 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
337 for (unsigned j = 0; j < 3; j++) {
338 int SrcIdx = getOperandIdx(MI->getOpcode(), OpTable[j][0]);
341 MachineOperand &MO = MI->getOperand(SrcIdx);
342 unsigned Reg = MI->getOperand(SrcIdx).getReg();
343 if (Reg == AMDGPU::ALU_CONST) {
344 unsigned Sel = MI->getOperand(
345 getOperandIdx(MI->getOpcode(), OpTable[j][1])).getImm();
346 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Sel));
349 if (Reg == AMDGPU::ALU_LITERAL_X) {
350 unsigned Imm = MI->getOperand(
351 getOperandIdx(MI->getOpcode(), AMDGPU::OpName::literal)).getImm();
352 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Imm));
355 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, 0));
360 std::vector<std::pair<int, unsigned> >
361 R600InstrInfo::ExtractSrcs(MachineInstr *MI,
362 const DenseMap<unsigned, unsigned> &PV,
363 unsigned &ConstCount) const {
365 const SmallVector<std::pair<MachineOperand *, int64_t>, 3> Srcs = getSrcs(MI);
366 const std::pair<int, unsigned> DummyPair(-1, 0);
367 std::vector<std::pair<int, unsigned> > Result;
369 for (unsigned n = Srcs.size(); i < n; ++i) {
370 unsigned Reg = Srcs[i].first->getReg();
371 unsigned Index = RI.getEncodingValue(Reg) & 0xff;
372 if (Reg == AMDGPU::OQAP) {
373 Result.push_back(std::pair<int, unsigned>(Index, 0));
375 if (PV.find(Reg) != PV.end()) {
376 // 255 is used to tells its a PS/PV reg
377 Result.push_back(std::pair<int, unsigned>(255, 0));
382 Result.push_back(DummyPair);
385 unsigned Chan = RI.getHWRegChan(Reg);
386 Result.push_back(std::pair<int, unsigned>(Index, Chan));
389 Result.push_back(DummyPair);
393 static std::vector<std::pair<int, unsigned> >
394 Swizzle(std::vector<std::pair<int, unsigned> > Src,
395 R600InstrInfo::BankSwizzle Swz) {
396 if (Src[0] == Src[1])
399 case R600InstrInfo::ALU_VEC_012_SCL_210:
401 case R600InstrInfo::ALU_VEC_021_SCL_122:
402 std::swap(Src[1], Src[2]);
404 case R600InstrInfo::ALU_VEC_102_SCL_221:
405 std::swap(Src[0], Src[1]);
407 case R600InstrInfo::ALU_VEC_120_SCL_212:
408 std::swap(Src[0], Src[1]);
409 std::swap(Src[0], Src[2]);
411 case R600InstrInfo::ALU_VEC_201:
412 std::swap(Src[0], Src[2]);
413 std::swap(Src[0], Src[1]);
415 case R600InstrInfo::ALU_VEC_210:
416 std::swap(Src[0], Src[2]);
423 getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) {
425 case R600InstrInfo::ALU_VEC_012_SCL_210: {
426 unsigned Cycles[3] = { 2, 1, 0};
429 case R600InstrInfo::ALU_VEC_021_SCL_122: {
430 unsigned Cycles[3] = { 1, 2, 2};
433 case R600InstrInfo::ALU_VEC_120_SCL_212: {
434 unsigned Cycles[3] = { 2, 1, 2};
437 case R600InstrInfo::ALU_VEC_102_SCL_221: {
438 unsigned Cycles[3] = { 2, 2, 1};
442 llvm_unreachable("Wrong Swizzle for Trans Slot");
447 /// returns how many MIs (whose inputs are represented by IGSrcs) can be packed
448 /// in the same Instruction Group while meeting read port limitations given a
449 /// Swz swizzle sequence.
450 unsigned R600InstrInfo::isLegalUpTo(
451 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
452 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
453 const std::vector<std::pair<int, unsigned> > &TransSrcs,
454 R600InstrInfo::BankSwizzle TransSwz) const {
456 memset(Vector, -1, sizeof(Vector));
457 for (unsigned i = 0, e = IGSrcs.size(); i < e; i++) {
458 const std::vector<std::pair<int, unsigned> > &Srcs =
459 Swizzle(IGSrcs[i], Swz[i]);
460 for (unsigned j = 0; j < 3; j++) {
461 const std::pair<int, unsigned> &Src = Srcs[j];
462 if (Src.first < 0 || Src.first == 255)
464 if (Src.first == GET_REG_INDEX(RI.getEncodingValue(AMDGPU::OQAP))) {
465 if (Swz[i] != R600InstrInfo::ALU_VEC_012_SCL_210 &&
466 Swz[i] != R600InstrInfo::ALU_VEC_021_SCL_122) {
467 // The value from output queue A (denoted by register OQAP) can
468 // only be fetched during the first cycle.
471 // OQAP does not count towards the normal read port restrictions
474 if (Vector[Src.second][j] < 0)
475 Vector[Src.second][j] = Src.first;
476 if (Vector[Src.second][j] != Src.first)
480 // Now check Trans Alu
481 for (unsigned i = 0, e = TransSrcs.size(); i < e; ++i) {
482 const std::pair<int, unsigned> &Src = TransSrcs[i];
483 unsigned Cycle = getTransSwizzle(TransSwz, i);
486 if (Src.first == 255)
488 if (Vector[Src.second][Cycle] < 0)
489 Vector[Src.second][Cycle] = Src.first;
490 if (Vector[Src.second][Cycle] != Src.first)
491 return IGSrcs.size() - 1;
493 return IGSrcs.size();
496 /// Given a swizzle sequence SwzCandidate and an index Idx, returns the next
497 /// (in lexicographic term) swizzle sequence assuming that all swizzles after
498 /// Idx can be skipped
500 NextPossibleSolution(
501 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
503 assert(Idx < SwzCandidate.size());
505 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210)
507 for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) {
508 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210;
512 int NextSwizzle = SwzCandidate[ResetIdx] + 1;
513 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle;
517 /// Enumerate all possible Swizzle sequence to find one that can meet all
518 /// read port requirements.
519 bool R600InstrInfo::FindSwizzleForVectorSlot(
520 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
521 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
522 const std::vector<std::pair<int, unsigned> > &TransSrcs,
523 R600InstrInfo::BankSwizzle TransSwz) const {
524 unsigned ValidUpTo = 0;
526 ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz);
527 if (ValidUpTo == IGSrcs.size())
529 } while (NextPossibleSolution(SwzCandidate, ValidUpTo));
533 /// Instructions in Trans slot can't read gpr at cycle 0 if they also read
534 /// a const, and can't read a gpr at cycle 1 if they read 2 const.
536 isConstCompatible(R600InstrInfo::BankSwizzle TransSwz,
537 const std::vector<std::pair<int, unsigned> > &TransOps,
538 unsigned ConstCount) {
539 // TransALU can't read 3 constants
542 for (unsigned i = 0, e = TransOps.size(); i < e; ++i) {
543 const std::pair<int, unsigned> &Src = TransOps[i];
544 unsigned Cycle = getTransSwizzle(TransSwz, i);
547 if (ConstCount > 0 && Cycle == 0)
549 if (ConstCount > 1 && Cycle == 1)
556 R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,
557 const DenseMap<unsigned, unsigned> &PV,
558 std::vector<BankSwizzle> &ValidSwizzle,
561 //Todo : support shared src0 - src1 operand
563 std::vector<std::vector<std::pair<int, unsigned> > > IGSrcs;
564 ValidSwizzle.clear();
566 BankSwizzle TransBS = ALU_VEC_012_SCL_210;
567 for (unsigned i = 0, e = IG.size(); i < e; ++i) {
568 IGSrcs.push_back(ExtractSrcs(IG[i], PV, ConstCount));
569 unsigned Op = getOperandIdx(IG[i]->getOpcode(),
570 AMDGPU::OpName::bank_swizzle);
571 ValidSwizzle.push_back( (R600InstrInfo::BankSwizzle)
572 IG[i]->getOperand(Op).getImm());
574 std::vector<std::pair<int, unsigned> > TransOps;
576 return FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps, TransBS);
578 TransOps = IGSrcs.back();
580 ValidSwizzle.pop_back();
582 static const R600InstrInfo::BankSwizzle TransSwz[] = {
588 for (unsigned i = 0; i < 4; i++) {
589 TransBS = TransSwz[i];
590 if (!isConstCompatible(TransBS, TransOps, ConstCount))
592 bool Result = FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps,
595 ValidSwizzle.push_back(TransBS);
605 R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts)
607 assert (Consts.size() <= 12 && "Too many operands in instructions group");
608 unsigned Pair1 = 0, Pair2 = 0;
609 for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
610 unsigned ReadConstHalf = Consts[i] & 2;
611 unsigned ReadConstIndex = Consts[i] & (~3);
612 unsigned ReadHalfConst = ReadConstIndex | ReadConstHalf;
614 Pair1 = ReadHalfConst;
617 if (Pair1 == ReadHalfConst)
620 Pair2 = ReadHalfConst;
623 if (Pair2 != ReadHalfConst)
630 R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs)
632 std::vector<unsigned> Consts;
633 SmallSet<int64_t, 4> Literals;
634 for (unsigned i = 0, n = MIs.size(); i < n; i++) {
635 MachineInstr *MI = MIs[i];
636 if (!isALUInstr(MI->getOpcode()))
639 const SmallVectorImpl<std::pair<MachineOperand *, int64_t> > &Srcs =
642 for (unsigned j = 0, e = Srcs.size(); j < e; j++) {
643 std::pair<MachineOperand *, unsigned> Src = Srcs[j];
644 if (Src.first->getReg() == AMDGPU::ALU_LITERAL_X)
645 Literals.insert(Src.second);
646 if (Literals.size() > 4)
648 if (Src.first->getReg() == AMDGPU::ALU_CONST)
649 Consts.push_back(Src.second);
650 if (AMDGPU::R600_KC0RegClass.contains(Src.first->getReg()) ||
651 AMDGPU::R600_KC1RegClass.contains(Src.first->getReg())) {
652 unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
653 unsigned Chan = RI.getHWRegChan(Src.first->getReg());
654 Consts.push_back((Index << 2) | Chan);
658 return fitsConstReadLimitations(Consts);
661 DFAPacketizer *R600InstrInfo::CreateTargetScheduleState(const TargetMachine *TM,
662 const ScheduleDAG *DAG) const {
663 const InstrItineraryData *II = TM->getInstrItineraryData();
664 return TM->getSubtarget<AMDGPUSubtarget>().createDFAPacketizer(II);
668 isPredicateSetter(unsigned Opcode) {
677 static MachineInstr *
678 findFirstPredicateSetterFrom(MachineBasicBlock &MBB,
679 MachineBasicBlock::iterator I) {
680 while (I != MBB.begin()) {
682 MachineInstr *MI = I;
683 if (isPredicateSetter(MI->getOpcode()))
691 bool isJump(unsigned Opcode) {
692 return Opcode == AMDGPU::JUMP || Opcode == AMDGPU::JUMP_COND;
695 static bool isBranch(unsigned Opcode) {
696 return Opcode == AMDGPU::BRANCH || Opcode == AMDGPU::BRANCH_COND_i32 ||
697 Opcode == AMDGPU::BRANCH_COND_f32;
701 R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
702 MachineBasicBlock *&TBB,
703 MachineBasicBlock *&FBB,
704 SmallVectorImpl<MachineOperand> &Cond,
705 bool AllowModify) const {
706 // Most of the following comes from the ARM implementation of AnalyzeBranch
708 // If the block has no terminators, it just falls into the block after it.
709 MachineBasicBlock::iterator I = MBB.end();
710 if (I == MBB.begin())
713 while (I->isDebugValue()) {
714 if (I == MBB.begin())
718 // AMDGPU::BRANCH* instructions are only available after isel and are not
720 if (isBranch(I->getOpcode()))
722 if (!isJump(static_cast<MachineInstr *>(I)->getOpcode())) {
726 // Remove successive JUMP
727 while (I != MBB.begin() && std::prev(I)->getOpcode() == AMDGPU::JUMP) {
728 MachineBasicBlock::iterator PriorI = std::prev(I);
730 I->removeFromParent();
733 MachineInstr *LastInst = I;
735 // If there is only one terminator instruction, process it.
736 unsigned LastOpc = LastInst->getOpcode();
737 if (I == MBB.begin() ||
738 !isJump(static_cast<MachineInstr *>(--I)->getOpcode())) {
739 if (LastOpc == AMDGPU::JUMP) {
740 TBB = LastInst->getOperand(0).getMBB();
742 } else if (LastOpc == AMDGPU::JUMP_COND) {
743 MachineInstr *predSet = I;
744 while (!isPredicateSetter(predSet->getOpcode())) {
747 TBB = LastInst->getOperand(0).getMBB();
748 Cond.push_back(predSet->getOperand(1));
749 Cond.push_back(predSet->getOperand(2));
750 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
753 return true; // Can't handle indirect branch.
756 // Get the instruction before it if it is a terminator.
757 MachineInstr *SecondLastInst = I;
758 unsigned SecondLastOpc = SecondLastInst->getOpcode();
760 // If the block ends with a B and a Bcc, handle it.
761 if (SecondLastOpc == AMDGPU::JUMP_COND && LastOpc == AMDGPU::JUMP) {
762 MachineInstr *predSet = --I;
763 while (!isPredicateSetter(predSet->getOpcode())) {
766 TBB = SecondLastInst->getOperand(0).getMBB();
767 FBB = LastInst->getOperand(0).getMBB();
768 Cond.push_back(predSet->getOperand(1));
769 Cond.push_back(predSet->getOperand(2));
770 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
774 // Otherwise, can't handle this.
779 MachineBasicBlock::iterator FindLastAluClause(MachineBasicBlock &MBB) {
780 for (MachineBasicBlock::reverse_iterator It = MBB.rbegin(), E = MBB.rend();
782 if (It->getOpcode() == AMDGPU::CF_ALU ||
783 It->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE)
784 return std::prev(It.base());
790 R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
791 MachineBasicBlock *TBB,
792 MachineBasicBlock *FBB,
793 const SmallVectorImpl<MachineOperand> &Cond,
795 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
799 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB);
802 MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
803 assert(PredSet && "No previous predicate !");
804 addFlag(PredSet, 0, MO_FLAG_PUSH);
805 PredSet->getOperand(2).setImm(Cond[1].getImm());
807 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
809 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
810 MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
811 if (CfAlu == MBB.end())
813 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
814 CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
818 MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
819 assert(PredSet && "No previous predicate !");
820 addFlag(PredSet, 0, MO_FLAG_PUSH);
821 PredSet->getOperand(2).setImm(Cond[1].getImm());
822 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
824 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
825 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB);
826 MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
827 if (CfAlu == MBB.end())
829 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
830 CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE));
836 R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
838 // Note : we leave PRED* instructions there.
839 // They may be needed when predicating instructions.
841 MachineBasicBlock::iterator I = MBB.end();
843 if (I == MBB.begin()) {
847 switch (I->getOpcode()) {
850 case AMDGPU::JUMP_COND: {
851 MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
852 clearFlag(predSet, 0, MO_FLAG_PUSH);
853 I->eraseFromParent();
854 MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
855 if (CfAlu == MBB.end())
857 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
858 CfAlu->setDesc(get(AMDGPU::CF_ALU));
862 I->eraseFromParent();
867 if (I == MBB.begin()) {
871 switch (I->getOpcode()) {
872 // FIXME: only one case??
875 case AMDGPU::JUMP_COND: {
876 MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
877 clearFlag(predSet, 0, MO_FLAG_PUSH);
878 I->eraseFromParent();
879 MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
880 if (CfAlu == MBB.end())
882 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
883 CfAlu->setDesc(get(AMDGPU::CF_ALU));
887 I->eraseFromParent();
894 R600InstrInfo::isPredicated(const MachineInstr *MI) const {
895 int idx = MI->findFirstPredOperandIdx();
899 unsigned Reg = MI->getOperand(idx).getReg();
901 default: return false;
902 case AMDGPU::PRED_SEL_ONE:
903 case AMDGPU::PRED_SEL_ZERO:
904 case AMDGPU::PREDICATE_BIT:
910 R600InstrInfo::isPredicable(MachineInstr *MI) const {
911 // XXX: KILL* instructions can be predicated, but they must be the last
912 // instruction in a clause, so this means any instructions after them cannot
913 // be predicated. Until we have proper support for instruction clauses in the
914 // backend, we will mark KILL* instructions as unpredicable.
916 if (MI->getOpcode() == AMDGPU::KILLGT) {
918 } else if (MI->getOpcode() == AMDGPU::CF_ALU) {
919 // If the clause start in the middle of MBB then the MBB has more
920 // than a single clause, unable to predicate several clauses.
921 if (MI->getParent()->begin() != MachineBasicBlock::iterator(MI))
923 // TODO: We don't support KC merging atm
924 if (MI->getOperand(3).getImm() != 0 || MI->getOperand(4).getImm() != 0)
927 } else if (isVector(*MI)) {
930 return AMDGPUInstrInfo::isPredicable(MI);
936 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
938 unsigned ExtraPredCycles,
939 const BranchProbability &Probability) const{
944 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
946 unsigned ExtraTCycles,
947 MachineBasicBlock &FMBB,
949 unsigned ExtraFCycles,
950 const BranchProbability &Probability) const {
955 R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
957 const BranchProbability &Probability)
963 R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
964 MachineBasicBlock &FMBB) const {
970 R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
971 MachineOperand &MO = Cond[1];
972 switch (MO.getImm()) {
973 case OPCODE_IS_ZERO_INT:
974 MO.setImm(OPCODE_IS_NOT_ZERO_INT);
976 case OPCODE_IS_NOT_ZERO_INT:
977 MO.setImm(OPCODE_IS_ZERO_INT);
980 MO.setImm(OPCODE_IS_NOT_ZERO);
982 case OPCODE_IS_NOT_ZERO:
983 MO.setImm(OPCODE_IS_ZERO);
989 MachineOperand &MO2 = Cond[2];
990 switch (MO2.getReg()) {
991 case AMDGPU::PRED_SEL_ZERO:
992 MO2.setReg(AMDGPU::PRED_SEL_ONE);
994 case AMDGPU::PRED_SEL_ONE:
995 MO2.setReg(AMDGPU::PRED_SEL_ZERO);
1004 R600InstrInfo::DefinesPredicate(MachineInstr *MI,
1005 std::vector<MachineOperand> &Pred) const {
1006 return isPredicateSetter(MI->getOpcode());
1011 R600InstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
1012 const SmallVectorImpl<MachineOperand> &Pred2) const {
1018 R600InstrInfo::PredicateInstruction(MachineInstr *MI,
1019 const SmallVectorImpl<MachineOperand> &Pred) const {
1020 int PIdx = MI->findFirstPredOperandIdx();
1022 if (MI->getOpcode() == AMDGPU::CF_ALU) {
1023 MI->getOperand(8).setImm(0);
1027 if (MI->getOpcode() == AMDGPU::DOT_4) {
1028 MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_X))
1029 .setReg(Pred[2].getReg());
1030 MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_Y))
1031 .setReg(Pred[2].getReg());
1032 MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_Z))
1033 .setReg(Pred[2].getReg());
1034 MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_W))
1035 .setReg(Pred[2].getReg());
1036 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1037 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
1042 MachineOperand &PMO = MI->getOperand(PIdx);
1043 PMO.setReg(Pred[2].getReg());
1044 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1045 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
1052 unsigned int R600InstrInfo::getPredicationCost(const MachineInstr *) const {
1056 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1057 const MachineInstr *MI,
1058 unsigned *PredCost) const {
1064 bool R600InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
1066 switch(MI->getOpcode()) {
1067 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
1068 case AMDGPU::R600_EXTRACT_ELT_V2:
1069 case AMDGPU::R600_EXTRACT_ELT_V4:
1070 buildIndirectRead(MI->getParent(), MI, MI->getOperand(0).getReg(),
1071 RI.getHWRegIndex(MI->getOperand(1).getReg()), // Address
1072 MI->getOperand(2).getReg(),
1073 RI.getHWRegChan(MI->getOperand(1).getReg()));
1075 case AMDGPU::R600_INSERT_ELT_V2:
1076 case AMDGPU::R600_INSERT_ELT_V4:
1077 buildIndirectWrite(MI->getParent(), MI, MI->getOperand(2).getReg(), // Value
1078 RI.getHWRegIndex(MI->getOperand(1).getReg()), // Address
1079 MI->getOperand(3).getReg(), // Offset
1080 RI.getHWRegChan(MI->getOperand(1).getReg())); // Channel
1083 MI->eraseFromParent();
1087 void R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved,
1088 const MachineFunction &MF) const {
1089 const AMDGPUFrameLowering *TFL =
1090 static_cast<const AMDGPUFrameLowering*>(
1091 MF.getTarget().getFrameLowering());
1093 unsigned StackWidth = TFL->getStackWidth(MF);
1094 int End = getIndirectIndexEnd(MF);
1099 for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) {
1100 unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
1101 Reserved.set(SuperReg);
1102 for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
1103 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
1109 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex,
1110 unsigned Channel) const {
1111 // XXX: Remove when we support a stack width > 2
1112 assert(Channel == 0);
1116 const TargetRegisterClass *R600InstrInfo::getIndirectAddrRegClass() const {
1117 return &AMDGPU::R600_TReg32_XRegClass;
1120 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
1121 MachineBasicBlock::iterator I,
1122 unsigned ValueReg, unsigned Address,
1123 unsigned OffsetReg) const {
1124 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0);
1127 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
1128 MachineBasicBlock::iterator I,
1129 unsigned ValueReg, unsigned Address,
1131 unsigned AddrChan) const {
1134 default: llvm_unreachable("Invalid Channel");
1135 case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break;
1136 case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break;
1137 case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break;
1138 case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address); break;
1140 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1141 AMDGPU::AR_X, OffsetReg);
1142 setImmOperand(MOVA, AMDGPU::OpName::write, 0);
1144 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1146 .addReg(AMDGPU::AR_X,
1147 RegState::Implicit | RegState::Kill);
1148 setImmOperand(Mov, AMDGPU::OpName::dst_rel, 1);
1152 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
1153 MachineBasicBlock::iterator I,
1154 unsigned ValueReg, unsigned Address,
1155 unsigned OffsetReg) const {
1156 return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0);
1159 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
1160 MachineBasicBlock::iterator I,
1161 unsigned ValueReg, unsigned Address,
1163 unsigned AddrChan) const {
1166 default: llvm_unreachable("Invalid Channel");
1167 case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break;
1168 case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break;
1169 case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break;
1170 case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address); break;
1172 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
1175 setImmOperand(MOVA, AMDGPU::OpName::write, 0);
1176 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
1179 .addReg(AMDGPU::AR_X,
1180 RegState::Implicit | RegState::Kill);
1181 setImmOperand(Mov, AMDGPU::OpName::src0_rel, 1);
1186 unsigned R600InstrInfo::getMaxAlusPerClause() const {
1190 MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB,
1191 MachineBasicBlock::iterator I,
1195 unsigned Src1Reg) const {
1196 MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
1200 MIB.addImm(0) // $update_exec_mask
1201 .addImm(0); // $update_predicate
1203 MIB.addImm(1) // $write
1205 .addImm(0) // $dst_rel
1206 .addImm(0) // $dst_clamp
1207 .addReg(Src0Reg) // $src0
1208 .addImm(0) // $src0_neg
1209 .addImm(0) // $src0_rel
1210 .addImm(0) // $src0_abs
1211 .addImm(-1); // $src0_sel
1214 MIB.addReg(Src1Reg) // $src1
1215 .addImm(0) // $src1_neg
1216 .addImm(0) // $src1_rel
1217 .addImm(0) // $src1_abs
1218 .addImm(-1); // $src1_sel
1221 //XXX: The r600g finalizer expects this to be 1, once we've moved the
1222 //scheduling to the backend, we can change the default to 0.
1223 MIB.addImm(1) // $last
1224 .addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
1225 .addImm(0) // $literal
1226 .addImm(0); // $bank_swizzle
1231 #define OPERAND_CASE(Label) \
1233 static const unsigned Ops[] = \
1243 static unsigned getSlotedOps(unsigned Op, unsigned Slot) {
1245 OPERAND_CASE(AMDGPU::OpName::update_exec_mask)
1246 OPERAND_CASE(AMDGPU::OpName::update_pred)
1247 OPERAND_CASE(AMDGPU::OpName::write)
1248 OPERAND_CASE(AMDGPU::OpName::omod)
1249 OPERAND_CASE(AMDGPU::OpName::dst_rel)
1250 OPERAND_CASE(AMDGPU::OpName::clamp)
1251 OPERAND_CASE(AMDGPU::OpName::src0)
1252 OPERAND_CASE(AMDGPU::OpName::src0_neg)
1253 OPERAND_CASE(AMDGPU::OpName::src0_rel)
1254 OPERAND_CASE(AMDGPU::OpName::src0_abs)
1255 OPERAND_CASE(AMDGPU::OpName::src0_sel)
1256 OPERAND_CASE(AMDGPU::OpName::src1)
1257 OPERAND_CASE(AMDGPU::OpName::src1_neg)
1258 OPERAND_CASE(AMDGPU::OpName::src1_rel)
1259 OPERAND_CASE(AMDGPU::OpName::src1_abs)
1260 OPERAND_CASE(AMDGPU::OpName::src1_sel)
1261 OPERAND_CASE(AMDGPU::OpName::pred_sel)
1263 llvm_unreachable("Wrong Operand");
1269 MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction(
1270 MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg)
1272 assert (MI->getOpcode() == AMDGPU::DOT_4 && "Not Implemented");
1274 if (ST.getGeneration() <= AMDGPUSubtarget::R700)
1275 Opcode = AMDGPU::DOT4_r600;
1277 Opcode = AMDGPU::DOT4_eg;
1278 MachineBasicBlock::iterator I = MI;
1279 MachineOperand &Src0 = MI->getOperand(
1280 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src0, Slot)));
1281 MachineOperand &Src1 = MI->getOperand(
1282 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src1, Slot)));
1283 MachineInstr *MIB = buildDefaultInstruction(
1284 MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
1285 static const unsigned Operands[14] = {
1286 AMDGPU::OpName::update_exec_mask,
1287 AMDGPU::OpName::update_pred,
1288 AMDGPU::OpName::write,
1289 AMDGPU::OpName::omod,
1290 AMDGPU::OpName::dst_rel,
1291 AMDGPU::OpName::clamp,
1292 AMDGPU::OpName::src0_neg,
1293 AMDGPU::OpName::src0_rel,
1294 AMDGPU::OpName::src0_abs,
1295 AMDGPU::OpName::src0_sel,
1296 AMDGPU::OpName::src1_neg,
1297 AMDGPU::OpName::src1_rel,
1298 AMDGPU::OpName::src1_abs,
1299 AMDGPU::OpName::src1_sel,
1302 MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
1303 getSlotedOps(AMDGPU::OpName::pred_sel, Slot)));
1304 MIB->getOperand(getOperandIdx(Opcode, AMDGPU::OpName::pred_sel))
1305 .setReg(MO.getReg());
1307 for (unsigned i = 0; i < 14; i++) {
1308 MachineOperand &MO = MI->getOperand(
1309 getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));
1310 assert (MO.isImm());
1311 setImmOperand(MIB, Operands[i], MO.getImm());
1313 MIB->getOperand(20).setImm(0);
1317 MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,
1318 MachineBasicBlock::iterator I,
1320 uint64_t Imm) const {
1321 MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg,
1322 AMDGPU::ALU_LITERAL_X);
1323 setImmOperand(MovImm, AMDGPU::OpName::literal, Imm);
1327 MachineInstr *R600InstrInfo::buildMovInstr(MachineBasicBlock *MBB,
1328 MachineBasicBlock::iterator I,
1329 unsigned DstReg, unsigned SrcReg) const {
1330 return buildDefaultInstruction(*MBB, I, AMDGPU::MOV, DstReg, SrcReg);
1333 int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const {
1334 return getOperandIdx(MI.getOpcode(), Op);
1337 int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const {
1338 return AMDGPU::getNamedOperandIdx(Opcode, Op);
1341 void R600InstrInfo::setImmOperand(MachineInstr *MI, unsigned Op,
1342 int64_t Imm) const {
1343 int Idx = getOperandIdx(*MI, Op);
1344 assert(Idx != -1 && "Operand not supported for this instruction.");
1345 assert(MI->getOperand(Idx).isImm());
1346 MI->getOperand(Idx).setImm(Imm);
1349 //===----------------------------------------------------------------------===//
1350 // Instruction flag getters/setters
1351 //===----------------------------------------------------------------------===//
1353 bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const {
1354 return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
1357 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr *MI, unsigned SrcIdx,
1358 unsigned Flag) const {
1359 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1362 // If we pass something other than the default value of Flag to this
1363 // function, it means we are want to set a flag on an instruction
1364 // that uses native encoding.
1365 assert(HAS_NATIVE_OPERANDS(TargetFlags));
1366 bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3;
1369 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::clamp);
1372 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::write);
1374 case MO_FLAG_NOT_LAST:
1376 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::last);
1380 case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_neg); break;
1381 case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_neg); break;
1382 case 2: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src2_neg); break;
1387 assert(!IsOP3 && "Cannot set absolute value modifier for OP3 "
1391 case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_abs); break;
1392 case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_abs); break;
1400 assert(FlagIndex != -1 && "Flag not supported for this instruction");
1402 FlagIndex = GET_FLAG_OPERAND_IDX(TargetFlags);
1403 assert(FlagIndex != 0 &&
1404 "Instruction flags not supported for this instruction");
1407 MachineOperand &FlagOp = MI->getOperand(FlagIndex);
1408 assert(FlagOp.isImm());
1412 void R600InstrInfo::addFlag(MachineInstr *MI, unsigned Operand,
1413 unsigned Flag) const {
1414 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1418 if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1419 MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1420 if (Flag == MO_FLAG_NOT_LAST) {
1421 clearFlag(MI, Operand, MO_FLAG_LAST);
1422 } else if (Flag == MO_FLAG_MASK) {
1423 clearFlag(MI, Operand, Flag);
1428 MachineOperand &FlagOp = getFlagOp(MI, Operand);
1429 FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
1433 void R600InstrInfo::clearFlag(MachineInstr *MI, unsigned Operand,
1434 unsigned Flag) const {
1435 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1436 if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1437 MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1440 MachineOperand &FlagOp = getFlagOp(MI);
1441 unsigned InstFlags = FlagOp.getImm();
1442 InstFlags &= ~(Flag << (NUM_MO_FLAGS * Operand));
1443 FlagOp.setImm(InstFlags);