1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for R600InstrInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef R600INSTRUCTIONINFO_H_
16 #define R600INSTRUCTIONINFO_H_
18 #include "AMDGPUInstrInfo.h"
20 #include "R600Defines.h"
21 #include "R600RegisterInfo.h"
26 class AMDGPUTargetMachine;
29 class MachineFunction;
31 class MachineInstrBuilder;
33 class R600InstrInfo : public AMDGPUInstrInfo {
35 const R600RegisterInfo RI;
36 const AMDGPUSubtarget &ST;
38 int getBranchInstr(const MachineOperand &op) const;
41 explicit R600InstrInfo(AMDGPUTargetMachine &tm);
43 const R600RegisterInfo &getRegisterInfo() const;
44 virtual void copyPhysReg(MachineBasicBlock &MBB,
45 MachineBasicBlock::iterator MI, DebugLoc DL,
46 unsigned DestReg, unsigned SrcReg,
49 bool isTrig(const MachineInstr &MI) const;
50 bool isPlaceHolderOpcode(unsigned opcode) const;
51 bool isReductionOp(unsigned opcode) const;
52 bool isCubeOp(unsigned opcode) const;
54 /// \returns true if this \p Opcode represents an ALU instruction.
55 bool isALUInstr(unsigned Opcode) const;
57 bool usesVertexCache(unsigned Opcode) const;
58 bool usesVertexCache(const MachineInstr *MI) const;
59 bool usesTextureCache(unsigned Opcode) const;
60 bool usesTextureCache(const MachineInstr *MI) const;
62 bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
63 bool canBundle(const std::vector<MachineInstr *> &) const;
65 /// \breif Vector instructions are instructions that must fill all
66 /// instruction slots within an instruction group.
67 bool isVector(const MachineInstr &MI) const;
69 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
72 virtual unsigned getIEQOpcode() const;
73 virtual bool isMov(unsigned Opcode) const;
75 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
76 const ScheduleDAG *DAG) const;
78 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
80 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
81 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
83 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
85 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
87 bool isPredicated(const MachineInstr *MI) const;
89 bool isPredicable(MachineInstr *MI) const;
92 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
93 const BranchProbability &Probability) const;
95 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
96 unsigned ExtraPredCycles,
97 const BranchProbability &Probability) const ;
100 isProfitableToIfCvt(MachineBasicBlock &TMBB,
101 unsigned NumTCycles, unsigned ExtraTCycles,
102 MachineBasicBlock &FMBB,
103 unsigned NumFCycles, unsigned ExtraFCycles,
104 const BranchProbability &Probability) const;
106 bool DefinesPredicate(MachineInstr *MI,
107 std::vector<MachineOperand> &Pred) const;
109 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
110 const SmallVectorImpl<MachineOperand> &Pred2) const;
112 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
113 MachineBasicBlock &FMBB) const;
115 bool PredicateInstruction(MachineInstr *MI,
116 const SmallVectorImpl<MachineOperand> &Pred) const;
118 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
119 const MachineInstr *MI,
120 unsigned *PredCost = 0) const;
122 virtual int getInstrLatency(const InstrItineraryData *ItinData,
123 SDNode *Node) const { return 1;}
125 /// \returns a list of all the registers that may be accesed using indirect
127 std::vector<unsigned> getIndirectReservedRegs(const MachineFunction &MF) const;
129 virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
131 virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
134 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
135 unsigned Channel) const;
137 virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
138 unsigned SourceReg) const;
140 virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
142 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
143 MachineBasicBlock::iterator I,
144 unsigned ValueReg, unsigned Address,
145 unsigned OffsetReg) const;
147 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
148 MachineBasicBlock::iterator I,
149 unsigned ValueReg, unsigned Address,
150 unsigned OffsetReg) const;
152 virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
154 unsigned getMaxAlusPerClause() const;
156 ///buildDefaultInstruction - This function returns a MachineInstr with
157 /// all the instruction modifiers initialized to their default values.
158 /// You can use this function to avoid manually specifying each instruction
159 /// modifier operand when building a new instruction.
161 /// \returns a MachineInstr with all the instruction modifiers initialized
162 /// to their default values.
163 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
164 MachineBasicBlock::iterator I,
168 unsigned Src1Reg = 0) const;
170 MachineInstr *buildMovImm(MachineBasicBlock &BB,
171 MachineBasicBlock::iterator I,
175 /// \brief Get the index of Op in the MachineInstr.
177 /// \returns -1 if the Instruction does not contain the specified \p Op.
178 int getOperandIdx(const MachineInstr &MI, R600Operands::Ops Op) const;
180 /// \brief Get the index of \p Op for the given Opcode.
182 /// \returns -1 if the Instruction does not contain the specified \p Op.
183 int getOperandIdx(unsigned Opcode, R600Operands::Ops Op) const;
185 /// \brief Helper function for setting instruction flag values.
186 void setImmOperand(MachineInstr *MI, R600Operands::Ops Op, int64_t Imm) const;
188 /// \returns true if this instruction has an operand for storing target flags.
189 bool hasFlagOperand(const MachineInstr &MI) const;
191 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
192 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
194 ///\brief Determine if the specified \p Flag is set on this \p Operand.
195 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
197 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
198 /// \param Flag The flag being set.
200 /// \returns the operand containing the flags for this instruction.
201 MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
202 unsigned Flag = 0) const;
204 /// \brief Clear the specified flag on the instruction.
205 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
208 } // End llvm namespace
210 #endif // R600INSTRINFO_H_