1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for R600InstrInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef R600INSTRUCTIONINFO_H_
16 #define R600INSTRUCTIONINFO_H_
18 #include "AMDGPUInstrInfo.h"
19 #include "R600Defines.h"
20 #include "R600RegisterInfo.h"
25 class AMDGPUTargetMachine;
28 class MachineFunction;
30 class MachineInstrBuilder;
32 class R600InstrInfo : public AMDGPUInstrInfo {
34 const R600RegisterInfo RI;
35 const AMDGPUSubtarget &ST;
37 int getBranchInstr(const MachineOperand &op) const;
38 std::vector<std::pair<int, unsigned> >
39 ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const;
43 ALU_VEC_012_SCL_210 = 0,
51 explicit R600InstrInfo(AMDGPUTargetMachine &tm);
53 const R600RegisterInfo &getRegisterInfo() const;
54 virtual void copyPhysReg(MachineBasicBlock &MBB,
55 MachineBasicBlock::iterator MI, DebugLoc DL,
56 unsigned DestReg, unsigned SrcReg,
59 bool isTrig(const MachineInstr &MI) const;
60 bool isPlaceHolderOpcode(unsigned opcode) const;
61 bool isReductionOp(unsigned opcode) const;
62 bool isCubeOp(unsigned opcode) const;
64 /// \returns true if this \p Opcode represents an ALU instruction.
65 bool isALUInstr(unsigned Opcode) const;
66 bool hasInstrModifiers(unsigned Opcode) const;
67 bool isLDSInstr(unsigned Opcode) const;
69 bool isTransOnly(unsigned Opcode) const;
70 bool isTransOnly(const MachineInstr *MI) const;
71 bool isVectorOnly(unsigned Opcode) const;
72 bool isVectorOnly(const MachineInstr *MI) const;
73 bool isExport(unsigned Opcode) const;
75 bool usesVertexCache(unsigned Opcode) const;
76 bool usesVertexCache(const MachineInstr *MI) const;
77 bool usesTextureCache(unsigned Opcode) const;
78 bool usesTextureCache(const MachineInstr *MI) const;
80 bool mustBeLastInClause(unsigned Opcode) const;
82 /// \returns The operand index for the given source number. Legal values
83 /// for SrcNum are 0, 1, and 2.
84 int getSrcIdx(unsigned Opcode, unsigned SrcNum) const;
85 /// \returns The operand Index for the Sel operand given an index to one
86 /// of the instruction's src operands.
87 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
89 /// \returns a pair for each src of an ALU instructions.
90 /// The first member of a pair is the register id.
91 /// If register is ALU_CONST, second member is SEL.
92 /// If register is ALU_LITERAL, second member is IMM.
93 /// Otherwise, second member value is undefined.
94 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
95 getSrcs(MachineInstr *MI) const;
98 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
99 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
100 const std::vector<std::pair<int, unsigned> > &TransSrcs,
101 R600InstrInfo::BankSwizzle TransSwz) const;
103 bool FindSwizzleForVectorSlot(
104 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
105 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
106 const std::vector<std::pair<int, unsigned> > &TransSrcs,
107 R600InstrInfo::BankSwizzle TransSwz) const;
109 /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
110 /// returns true and the first (in lexical order) BankSwizzle affectation
111 /// starting from the one already provided in the Instruction Group MIs that
112 /// fits Read Port limitations in BS if available. Otherwise returns false
113 /// and undefined content in BS.
114 /// isLastAluTrans should be set if the last Alu of MIs will be executed on
115 /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
116 /// apply to the last instruction.
117 /// PV holds GPR to PV registers in the Instruction Group MIs.
118 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
119 const DenseMap<unsigned, unsigned> &PV,
120 std::vector<BankSwizzle> &BS,
121 bool isLastAluTrans) const;
123 /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
124 /// from KCache bank on R700+. This function check if MI set in input meet
126 bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
127 /// Same but using const index set instead of MI set.
128 bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
130 /// \breif Vector instructions are instructions that must fill all
131 /// instruction slots within an instruction group.
132 bool isVector(const MachineInstr &MI) const;
134 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
137 virtual unsigned getIEQOpcode() const;
138 virtual bool isMov(unsigned Opcode) const;
140 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
141 const ScheduleDAG *DAG) const;
143 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
145 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
146 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
148 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
150 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
152 bool isPredicated(const MachineInstr *MI) const;
154 bool isPredicable(MachineInstr *MI) const;
157 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
158 const BranchProbability &Probability) const;
160 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
161 unsigned ExtraPredCycles,
162 const BranchProbability &Probability) const ;
165 isProfitableToIfCvt(MachineBasicBlock &TMBB,
166 unsigned NumTCycles, unsigned ExtraTCycles,
167 MachineBasicBlock &FMBB,
168 unsigned NumFCycles, unsigned ExtraFCycles,
169 const BranchProbability &Probability) const;
171 bool DefinesPredicate(MachineInstr *MI,
172 std::vector<MachineOperand> &Pred) const;
174 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
175 const SmallVectorImpl<MachineOperand> &Pred2) const;
177 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
178 MachineBasicBlock &FMBB) const;
180 bool PredicateInstruction(MachineInstr *MI,
181 const SmallVectorImpl<MachineOperand> &Pred) const;
183 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
184 const MachineInstr *MI,
185 unsigned *PredCost = 0) const;
187 virtual int getInstrLatency(const InstrItineraryData *ItinData,
188 SDNode *Node) const { return 1;}
190 /// \returns a list of all the registers that may be accesed using indirect
192 std::vector<unsigned> getIndirectReservedRegs(const MachineFunction &MF) const;
194 virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
196 virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
199 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
200 unsigned Channel) const;
202 virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
203 unsigned SourceReg) const;
205 virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
207 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
208 MachineBasicBlock::iterator I,
209 unsigned ValueReg, unsigned Address,
210 unsigned OffsetReg) const;
212 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
213 MachineBasicBlock::iterator I,
214 unsigned ValueReg, unsigned Address,
215 unsigned OffsetReg) const;
217 virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
219 unsigned getMaxAlusPerClause() const;
221 ///buildDefaultInstruction - This function returns a MachineInstr with
222 /// all the instruction modifiers initialized to their default values.
223 /// You can use this function to avoid manually specifying each instruction
224 /// modifier operand when building a new instruction.
226 /// \returns a MachineInstr with all the instruction modifiers initialized
227 /// to their default values.
228 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
229 MachineBasicBlock::iterator I,
233 unsigned Src1Reg = 0) const;
235 MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
238 unsigned DstReg) const;
240 MachineInstr *buildMovImm(MachineBasicBlock &BB,
241 MachineBasicBlock::iterator I,
245 /// \brief Get the index of Op in the MachineInstr.
247 /// \returns -1 if the Instruction does not contain the specified \p Op.
248 int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
250 /// \brief Get the index of \p Op for the given Opcode.
252 /// \returns -1 if the Instruction does not contain the specified \p Op.
253 int getOperandIdx(unsigned Opcode, unsigned Op) const;
255 /// \brief Helper function for setting instruction flag values.
256 void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const;
258 /// \returns true if this instruction has an operand for storing target flags.
259 bool hasFlagOperand(const MachineInstr &MI) const;
261 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
262 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
264 ///\brief Determine if the specified \p Flag is set on this \p Operand.
265 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
267 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
268 /// \param Flag The flag being set.
270 /// \returns the operand containing the flags for this instruction.
271 MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
272 unsigned Flag = 0) const;
274 /// \brief Clear the specified flag on the instruction.
275 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
280 int getLDSNoRetOp(uint16_t Opcode);
282 } //End namespace AMDGPU
284 } // End llvm namespace
286 #endif // R600INSTRINFO_H_