1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for R600InstrInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef R600INSTRUCTIONINFO_H_
16 #define R600INSTRUCTIONINFO_H_
19 #include "AMDGPUInstrInfo.h"
20 #include "R600Defines.h"
21 #include "R600RegisterInfo.h"
27 class AMDGPUTargetMachine;
30 class MachineFunction;
32 class MachineInstrBuilder;
34 class R600InstrInfo : public AMDGPUInstrInfo {
36 const R600RegisterInfo RI;
38 int getBranchInstr(const MachineOperand &op) const;
41 explicit R600InstrInfo(AMDGPUTargetMachine &tm);
43 const R600RegisterInfo &getRegisterInfo() const;
44 virtual void copyPhysReg(MachineBasicBlock &MBB,
45 MachineBasicBlock::iterator MI, DebugLoc DL,
46 unsigned DestReg, unsigned SrcReg,
49 bool isTrig(const MachineInstr &MI) const;
50 bool isPlaceHolderOpcode(unsigned opcode) const;
51 bool isReductionOp(unsigned opcode) const;
52 bool isCubeOp(unsigned opcode) const;
54 /// \returns true if this \p Opcode represents an ALU instruction.
55 bool isALUInstr(unsigned Opcode) const;
57 /// \breif Vector instructions are instructions that must fill all
58 /// instruction slots within an instruction group.
59 bool isVector(const MachineInstr &MI) const;
61 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
64 virtual unsigned getIEQOpcode() const;
65 virtual bool isMov(unsigned Opcode) const;
67 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
68 const ScheduleDAG *DAG) const;
70 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
72 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
73 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
75 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
77 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
79 bool isPredicated(const MachineInstr *MI) const;
81 bool isPredicable(MachineInstr *MI) const;
84 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
85 const BranchProbability &Probability) const;
87 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
88 unsigned ExtraPredCycles,
89 const BranchProbability &Probability) const ;
92 isProfitableToIfCvt(MachineBasicBlock &TMBB,
93 unsigned NumTCycles, unsigned ExtraTCycles,
94 MachineBasicBlock &FMBB,
95 unsigned NumFCycles, unsigned ExtraFCycles,
96 const BranchProbability &Probability) const;
98 bool DefinesPredicate(MachineInstr *MI,
99 std::vector<MachineOperand> &Pred) const;
101 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
102 const SmallVectorImpl<MachineOperand> &Pred2) const;
104 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
105 MachineBasicBlock &FMBB) const;
107 bool PredicateInstruction(MachineInstr *MI,
108 const SmallVectorImpl<MachineOperand> &Pred) const;
110 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
111 const MachineInstr *MI,
112 unsigned *PredCost = 0) const;
114 virtual int getInstrLatency(const InstrItineraryData *ItinData,
115 SDNode *Node) const { return 1;}
117 /// You can use this function to avoid manually specifying each instruction
118 /// modifier operand when building a new instruction.
120 /// \returns a MachineInstr with all the instruction modifiers initialized
121 /// to their default values.
122 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
123 MachineBasicBlock::iterator I,
127 unsigned Src1Reg = 0) const;
129 MachineInstr *buildMovImm(MachineBasicBlock &BB,
130 MachineBasicBlock::iterator I,
134 /// \brief Get the index of Op in the MachineInstr.
136 /// \returns -1 if the Instruction does not contain the specified \p Op.
137 int getOperandIdx(const MachineInstr &MI, R600Operands::Ops Op) const;
139 /// \brief Get the index of \p Op for the given Opcode.
141 /// \returns -1 if the Instruction does not contain the specified \p Op.
142 int getOperandIdx(unsigned Opcode, R600Operands::Ops Op) const;
144 /// \brief Helper function for setting instruction flag values.
145 void setImmOperand(MachineInstr *MI, R600Operands::Ops Op, int64_t Imm) const;
147 /// \returns true if this instruction has an operand for storing target flags.
148 bool hasFlagOperand(const MachineInstr &MI) const;
150 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
151 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
153 ///\brief Determine if the specified \p Flag is set on this \p Operand.
154 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
156 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
157 /// \param Flag The flag being set.
159 /// \returns the operand containing the flags for this instruction.
160 MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
161 unsigned Flag = 0) const;
163 /// \brief Clear the specified flag on the instruction.
164 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
167 } // End llvm namespace
169 #endif // R600INSTRINFO_H_