1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for R600InstrInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef R600INSTRUCTIONINFO_H_
16 #define R600INSTRUCTIONINFO_H_
18 #include "AMDGPUInstrInfo.h"
19 #include "R600Defines.h"
20 #include "R600RegisterInfo.h"
25 class AMDGPUTargetMachine;
28 class MachineFunction;
30 class MachineInstrBuilder;
32 class R600InstrInfo : public AMDGPUInstrInfo {
34 const R600RegisterInfo RI;
35 const AMDGPUSubtarget &ST;
37 int getBranchInstr(const MachineOperand &op) const;
38 std::vector<std::pair<int, unsigned> >
39 ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const;
43 ALU_VEC_012_SCL_210 = 0,
51 explicit R600InstrInfo(AMDGPUTargetMachine &tm);
53 const R600RegisterInfo &getRegisterInfo() const override;
54 void copyPhysReg(MachineBasicBlock &MBB,
55 MachineBasicBlock::iterator MI, DebugLoc DL,
56 unsigned DestReg, unsigned SrcReg,
57 bool KillSrc) const override;
58 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
59 MachineBasicBlock::iterator MBBI) const override;
61 bool isTrig(const MachineInstr &MI) const;
62 bool isPlaceHolderOpcode(unsigned opcode) const;
63 bool isReductionOp(unsigned opcode) const;
64 bool isCubeOp(unsigned opcode) const;
66 /// \returns true if this \p Opcode represents an ALU instruction.
67 bool isALUInstr(unsigned Opcode) const;
68 bool hasInstrModifiers(unsigned Opcode) const;
69 bool isLDSInstr(unsigned Opcode) const;
70 bool isLDSNoRetInstr(unsigned Opcode) const;
71 bool isLDSRetInstr(unsigned Opcode) const;
73 /// \returns true if this \p Opcode represents an ALU instruction or an
74 /// instruction that will be lowered in ExpandSpecialInstrs Pass.
75 bool canBeConsideredALU(const MachineInstr *MI) const;
77 bool isTransOnly(unsigned Opcode) const;
78 bool isTransOnly(const MachineInstr *MI) const;
79 bool isVectorOnly(unsigned Opcode) const;
80 bool isVectorOnly(const MachineInstr *MI) const;
81 bool isExport(unsigned Opcode) const;
83 bool usesVertexCache(unsigned Opcode) const;
84 bool usesVertexCache(const MachineInstr *MI) const;
85 bool usesTextureCache(unsigned Opcode) const;
86 bool usesTextureCache(const MachineInstr *MI) const;
88 bool mustBeLastInClause(unsigned Opcode) const;
89 bool usesAddressRegister(MachineInstr *MI) const;
90 bool definesAddressRegister(MachineInstr *MI) const;
91 bool readsLDSSrcReg(const MachineInstr *MI) const;
93 /// \returns The operand index for the given source number. Legal values
94 /// for SrcNum are 0, 1, and 2.
95 int getSrcIdx(unsigned Opcode, unsigned SrcNum) const;
96 /// \returns The operand Index for the Sel operand given an index to one
97 /// of the instruction's src operands.
98 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
100 /// \returns a pair for each src of an ALU instructions.
101 /// The first member of a pair is the register id.
102 /// If register is ALU_CONST, second member is SEL.
103 /// If register is ALU_LITERAL, second member is IMM.
104 /// Otherwise, second member value is undefined.
105 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
106 getSrcs(MachineInstr *MI) const;
108 unsigned isLegalUpTo(
109 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
110 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
111 const std::vector<std::pair<int, unsigned> > &TransSrcs,
112 R600InstrInfo::BankSwizzle TransSwz) const;
114 bool FindSwizzleForVectorSlot(
115 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
116 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
117 const std::vector<std::pair<int, unsigned> > &TransSrcs,
118 R600InstrInfo::BankSwizzle TransSwz) const;
120 /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
121 /// returns true and the first (in lexical order) BankSwizzle affectation
122 /// starting from the one already provided in the Instruction Group MIs that
123 /// fits Read Port limitations in BS if available. Otherwise returns false
124 /// and undefined content in BS.
125 /// isLastAluTrans should be set if the last Alu of MIs will be executed on
126 /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
127 /// apply to the last instruction.
128 /// PV holds GPR to PV registers in the Instruction Group MIs.
129 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
130 const DenseMap<unsigned, unsigned> &PV,
131 std::vector<BankSwizzle> &BS,
132 bool isLastAluTrans) const;
134 /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
135 /// from KCache bank on R700+. This function check if MI set in input meet
137 bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
138 /// Same but using const index set instead of MI set.
139 bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
141 /// \brief Vector instructions are instructions that must fill all
142 /// instruction slots within an instruction group.
143 bool isVector(const MachineInstr &MI) const;
145 unsigned getIEQOpcode() const override;
146 bool isMov(unsigned Opcode) const override;
148 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
149 const ScheduleDAG *DAG) const override;
151 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
153 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
154 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override;
156 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const override;
158 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
160 bool isPredicated(const MachineInstr *MI) const override;
162 bool isPredicable(MachineInstr *MI) const override;
165 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
166 const BranchProbability &Probability) const override;
168 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
169 unsigned ExtraPredCycles,
170 const BranchProbability &Probability) const override ;
173 isProfitableToIfCvt(MachineBasicBlock &TMBB,
174 unsigned NumTCycles, unsigned ExtraTCycles,
175 MachineBasicBlock &FMBB,
176 unsigned NumFCycles, unsigned ExtraFCycles,
177 const BranchProbability &Probability) const override;
179 bool DefinesPredicate(MachineInstr *MI,
180 std::vector<MachineOperand> &Pred) const override;
182 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
183 const SmallVectorImpl<MachineOperand> &Pred2) const override;
185 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
186 MachineBasicBlock &FMBB) const override;
188 bool PredicateInstruction(MachineInstr *MI,
189 const SmallVectorImpl<MachineOperand> &Pred) const override;
191 unsigned int getPredicationCost(const MachineInstr *) const override;
193 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
194 const MachineInstr *MI,
195 unsigned *PredCost = nullptr) const override;
197 int getInstrLatency(const InstrItineraryData *ItinData,
198 SDNode *Node) const override { return 1;}
200 /// \brief Reserve the registers that may be accesed using indirect addressing.
201 void reserveIndirectRegisters(BitVector &Reserved,
202 const MachineFunction &MF) const;
204 unsigned calculateIndirectAddress(unsigned RegIndex,
205 unsigned Channel) const override;
207 const TargetRegisterClass *getIndirectAddrRegClass() const override;
209 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
210 MachineBasicBlock::iterator I,
211 unsigned ValueReg, unsigned Address,
212 unsigned OffsetReg) const override;
214 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
215 MachineBasicBlock::iterator I,
216 unsigned ValueReg, unsigned Address,
217 unsigned OffsetReg) const override;
219 unsigned getMaxAlusPerClause() const;
221 ///buildDefaultInstruction - This function returns a MachineInstr with
222 /// all the instruction modifiers initialized to their default values.
223 /// You can use this function to avoid manually specifying each instruction
224 /// modifier operand when building a new instruction.
226 /// \returns a MachineInstr with all the instruction modifiers initialized
227 /// to their default values.
228 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
229 MachineBasicBlock::iterator I,
233 unsigned Src1Reg = 0) const;
235 MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
238 unsigned DstReg) const;
240 MachineInstr *buildMovImm(MachineBasicBlock &BB,
241 MachineBasicBlock::iterator I,
245 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
246 MachineBasicBlock::iterator I,
247 unsigned DstReg, unsigned SrcReg) const override;
249 /// \brief Get the index of Op in the MachineInstr.
251 /// \returns -1 if the Instruction does not contain the specified \p Op.
252 int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
254 /// \brief Get the index of \p Op for the given Opcode.
256 /// \returns -1 if the Instruction does not contain the specified \p Op.
257 int getOperandIdx(unsigned Opcode, unsigned Op) const;
259 /// \brief Helper function for setting instruction flag values.
260 void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const;
262 /// \returns true if this instruction has an operand for storing target flags.
263 bool hasFlagOperand(const MachineInstr &MI) const;
265 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
266 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
268 ///\brief Determine if the specified \p Flag is set on this \p Operand.
269 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
271 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
272 /// \param Flag The flag being set.
274 /// \returns the operand containing the flags for this instruction.
275 MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
276 unsigned Flag = 0) const;
278 /// \brief Clear the specified flag on the instruction.
279 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
284 int getLDSNoRetOp(uint16_t Opcode);
286 } //End namespace AMDGPU
288 } // End llvm namespace
290 #endif // R600INSTRINFO_H_