1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for R600InstrInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef R600INSTRUCTIONINFO_H_
16 #define R600INSTRUCTIONINFO_H_
18 #include "AMDGPUInstrInfo.h"
20 #include "R600Defines.h"
21 #include "R600RegisterInfo.h"
26 class AMDGPUTargetMachine;
29 class MachineFunction;
31 class MachineInstrBuilder;
33 class R600InstrInfo : public AMDGPUInstrInfo {
35 const R600RegisterInfo RI;
36 const AMDGPUSubtarget &ST;
38 int getBranchInstr(const MachineOperand &op) const;
41 explicit R600InstrInfo(AMDGPUTargetMachine &tm);
43 const R600RegisterInfo &getRegisterInfo() const;
44 virtual void copyPhysReg(MachineBasicBlock &MBB,
45 MachineBasicBlock::iterator MI, DebugLoc DL,
46 unsigned DestReg, unsigned SrcReg,
49 bool isTrig(const MachineInstr &MI) const;
50 bool isPlaceHolderOpcode(unsigned opcode) const;
51 bool isReductionOp(unsigned opcode) const;
52 bool isCubeOp(unsigned opcode) const;
54 /// \returns true if this \p Opcode represents an ALU instruction.
55 bool isALUInstr(unsigned Opcode) const;
57 bool isTransOnly(unsigned Opcode) const;
58 bool isTransOnly(const MachineInstr *MI) const;
60 bool usesVertexCache(unsigned Opcode) const;
61 bool usesVertexCache(const MachineInstr *MI) const;
62 bool usesTextureCache(unsigned Opcode) const;
63 bool usesTextureCache(const MachineInstr *MI) const;
65 bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
66 bool canBundle(const std::vector<MachineInstr *> &) const;
68 /// \breif Vector instructions are instructions that must fill all
69 /// instruction slots within an instruction group.
70 bool isVector(const MachineInstr &MI) const;
72 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
75 virtual unsigned getIEQOpcode() const;
76 virtual bool isMov(unsigned Opcode) const;
78 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
79 const ScheduleDAG *DAG) const;
81 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
83 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
84 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
86 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
88 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
90 bool isPredicated(const MachineInstr *MI) const;
92 bool isPredicable(MachineInstr *MI) const;
95 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
96 const BranchProbability &Probability) const;
98 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
99 unsigned ExtraPredCycles,
100 const BranchProbability &Probability) const ;
103 isProfitableToIfCvt(MachineBasicBlock &TMBB,
104 unsigned NumTCycles, unsigned ExtraTCycles,
105 MachineBasicBlock &FMBB,
106 unsigned NumFCycles, unsigned ExtraFCycles,
107 const BranchProbability &Probability) const;
109 bool DefinesPredicate(MachineInstr *MI,
110 std::vector<MachineOperand> &Pred) const;
112 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
113 const SmallVectorImpl<MachineOperand> &Pred2) const;
115 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
116 MachineBasicBlock &FMBB) const;
118 bool PredicateInstruction(MachineInstr *MI,
119 const SmallVectorImpl<MachineOperand> &Pred) const;
121 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
122 const MachineInstr *MI,
123 unsigned *PredCost = 0) const;
125 virtual int getInstrLatency(const InstrItineraryData *ItinData,
126 SDNode *Node) const { return 1;}
128 /// \returns a list of all the registers that may be accesed using indirect
130 std::vector<unsigned> getIndirectReservedRegs(const MachineFunction &MF) const;
132 virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
134 virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
137 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
138 unsigned Channel) const;
140 virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
141 unsigned SourceReg) const;
143 virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
145 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
146 MachineBasicBlock::iterator I,
147 unsigned ValueReg, unsigned Address,
148 unsigned OffsetReg) const;
150 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
151 MachineBasicBlock::iterator I,
152 unsigned ValueReg, unsigned Address,
153 unsigned OffsetReg) const;
155 virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
157 unsigned getMaxAlusPerClause() const;
159 ///buildDefaultInstruction - This function returns a MachineInstr with
160 /// all the instruction modifiers initialized to their default values.
161 /// You can use this function to avoid manually specifying each instruction
162 /// modifier operand when building a new instruction.
164 /// \returns a MachineInstr with all the instruction modifiers initialized
165 /// to their default values.
166 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
167 MachineBasicBlock::iterator I,
171 unsigned Src1Reg = 0) const;
173 MachineInstr *buildMovImm(MachineBasicBlock &BB,
174 MachineBasicBlock::iterator I,
178 /// \brief Get the index of Op in the MachineInstr.
180 /// \returns -1 if the Instruction does not contain the specified \p Op.
181 int getOperandIdx(const MachineInstr &MI, R600Operands::Ops Op) const;
183 /// \brief Get the index of \p Op for the given Opcode.
185 /// \returns -1 if the Instruction does not contain the specified \p Op.
186 int getOperandIdx(unsigned Opcode, R600Operands::Ops Op) const;
188 /// \brief Helper function for setting instruction flag values.
189 void setImmOperand(MachineInstr *MI, R600Operands::Ops Op, int64_t Imm) const;
191 /// \returns true if this instruction has an operand for storing target flags.
192 bool hasFlagOperand(const MachineInstr &MI) const;
194 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
195 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
197 ///\brief Determine if the specified \p Flag is set on this \p Operand.
198 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
200 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
201 /// \param Flag The flag being set.
203 /// \returns the operand containing the flags for this instruction.
204 MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
205 unsigned Flag = 0) const;
207 /// \brief Clear the specified flag on the instruction.
208 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
211 } // End llvm namespace
213 #endif // R600INSTRINFO_H_