1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for R600InstrInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef R600INSTRUCTIONINFO_H_
16 #define R600INSTRUCTIONINFO_H_
18 #include "AMDGPUInstrInfo.h"
20 #include "R600Defines.h"
21 #include "R600RegisterInfo.h"
26 class AMDGPUTargetMachine;
29 class MachineFunction;
31 class MachineInstrBuilder;
33 class R600InstrInfo : public AMDGPUInstrInfo {
35 const R600RegisterInfo RI;
36 const AMDGPUSubtarget &ST;
38 int getBranchInstr(const MachineOperand &op) const;
39 std::vector<std::pair<int, unsigned> >
40 ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV) const;
52 explicit R600InstrInfo(AMDGPUTargetMachine &tm);
54 const R600RegisterInfo &getRegisterInfo() const;
55 virtual void copyPhysReg(MachineBasicBlock &MBB,
56 MachineBasicBlock::iterator MI, DebugLoc DL,
57 unsigned DestReg, unsigned SrcReg,
60 bool isTrig(const MachineInstr &MI) const;
61 bool isPlaceHolderOpcode(unsigned opcode) const;
62 bool isReductionOp(unsigned opcode) const;
63 bool isCubeOp(unsigned opcode) const;
65 /// \returns true if this \p Opcode represents an ALU instruction.
66 bool isALUInstr(unsigned Opcode) const;
68 bool isTransOnly(unsigned Opcode) const;
69 bool isTransOnly(const MachineInstr *MI) const;
71 bool usesVertexCache(unsigned Opcode) const;
72 bool usesVertexCache(const MachineInstr *MI) const;
73 bool usesTextureCache(unsigned Opcode) const;
74 bool usesTextureCache(const MachineInstr *MI) const;
76 /// \returns a pair for each src of an ALU instructions.
77 /// The first member of a pair is the register id.
78 /// If register is ALU_CONST, second member is SEL.
79 /// If register is ALU_LITERAL, second member is IMM.
80 /// Otherwise, second member value is undefined.
81 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
82 getSrcs(MachineInstr *MI) const;
84 /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
85 /// returns true and the first (in lexical order) BankSwizzle affectation
86 /// starting from the one already provided in the Instruction Group MIs that
87 /// fits Read Port limitations in BS if available. Otherwise returns false
88 /// and undefined content in BS.
89 /// PV holds GPR to PV registers in the Instruction Group MIs.
90 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
91 const DenseMap<unsigned, unsigned> &PV,
92 std::vector<BankSwizzle> &BS) const;
93 bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
94 bool canBundle(const std::vector<MachineInstr *> &) const;
96 /// \breif Vector instructions are instructions that must fill all
97 /// instruction slots within an instruction group.
98 bool isVector(const MachineInstr &MI) const;
100 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
103 virtual unsigned getIEQOpcode() const;
104 virtual bool isMov(unsigned Opcode) const;
106 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
107 const ScheduleDAG *DAG) const;
109 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
111 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
112 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
114 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
116 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
118 bool isPredicated(const MachineInstr *MI) const;
120 bool isPredicable(MachineInstr *MI) const;
123 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
124 const BranchProbability &Probability) const;
126 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
127 unsigned ExtraPredCycles,
128 const BranchProbability &Probability) const ;
131 isProfitableToIfCvt(MachineBasicBlock &TMBB,
132 unsigned NumTCycles, unsigned ExtraTCycles,
133 MachineBasicBlock &FMBB,
134 unsigned NumFCycles, unsigned ExtraFCycles,
135 const BranchProbability &Probability) const;
137 bool DefinesPredicate(MachineInstr *MI,
138 std::vector<MachineOperand> &Pred) const;
140 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
141 const SmallVectorImpl<MachineOperand> &Pred2) const;
143 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
144 MachineBasicBlock &FMBB) const;
146 bool PredicateInstruction(MachineInstr *MI,
147 const SmallVectorImpl<MachineOperand> &Pred) const;
149 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
150 const MachineInstr *MI,
151 unsigned *PredCost = 0) const;
153 virtual int getInstrLatency(const InstrItineraryData *ItinData,
154 SDNode *Node) const { return 1;}
156 /// \returns a list of all the registers that may be accesed using indirect
158 std::vector<unsigned> getIndirectReservedRegs(const MachineFunction &MF) const;
160 virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
162 virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
165 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
166 unsigned Channel) const;
168 virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
169 unsigned SourceReg) const;
171 virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
173 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
174 MachineBasicBlock::iterator I,
175 unsigned ValueReg, unsigned Address,
176 unsigned OffsetReg) const;
178 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
179 MachineBasicBlock::iterator I,
180 unsigned ValueReg, unsigned Address,
181 unsigned OffsetReg) const;
183 virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
185 unsigned getMaxAlusPerClause() const;
187 ///buildDefaultInstruction - This function returns a MachineInstr with
188 /// all the instruction modifiers initialized to their default values.
189 /// You can use this function to avoid manually specifying each instruction
190 /// modifier operand when building a new instruction.
192 /// \returns a MachineInstr with all the instruction modifiers initialized
193 /// to their default values.
194 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
195 MachineBasicBlock::iterator I,
199 unsigned Src1Reg = 0) const;
201 MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
204 unsigned DstReg) const;
206 MachineInstr *buildMovImm(MachineBasicBlock &BB,
207 MachineBasicBlock::iterator I,
211 /// \brief Get the index of Op in the MachineInstr.
213 /// \returns -1 if the Instruction does not contain the specified \p Op.
214 int getOperandIdx(const MachineInstr &MI, R600Operands::Ops Op) const;
216 /// \brief Get the index of \p Op for the given Opcode.
218 /// \returns -1 if the Instruction does not contain the specified \p Op.
219 int getOperandIdx(unsigned Opcode, R600Operands::Ops Op) const;
221 /// \brief Helper function for setting instruction flag values.
222 void setImmOperand(MachineInstr *MI, R600Operands::Ops Op, int64_t Imm) const;
224 /// \returns true if this instruction has an operand for storing target flags.
225 bool hasFlagOperand(const MachineInstr &MI) const;
227 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
228 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
230 ///\brief Determine if the specified \p Flag is set on this \p Operand.
231 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
233 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
234 /// \param Flag The flag being set.
236 /// \returns the operand containing the flags for this instruction.
237 MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
238 unsigned Flag = 0) const;
240 /// \brief Clear the specified flag on the instruction.
241 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
244 } // End llvm namespace
246 #endif // R600INSTRINFO_H_