1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for R600InstrInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef R600INSTRUCTIONINFO_H_
16 #define R600INSTRUCTIONINFO_H_
18 #include "AMDGPUInstrInfo.h"
19 #include "R600Defines.h"
20 #include "R600RegisterInfo.h"
25 class AMDGPUTargetMachine;
28 class MachineFunction;
30 class MachineInstrBuilder;
32 class R600InstrInfo : public AMDGPUInstrInfo {
34 const R600RegisterInfo RI;
35 const AMDGPUSubtarget &ST;
37 int getBranchInstr(const MachineOperand &op) const;
38 std::vector<std::pair<int, unsigned> >
39 ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const;
43 ALU_VEC_012_SCL_210 = 0,
51 explicit R600InstrInfo(AMDGPUTargetMachine &tm);
53 const R600RegisterInfo &getRegisterInfo() const;
54 virtual void copyPhysReg(MachineBasicBlock &MBB,
55 MachineBasicBlock::iterator MI, DebugLoc DL,
56 unsigned DestReg, unsigned SrcReg,
59 bool isTrig(const MachineInstr &MI) const;
60 bool isPlaceHolderOpcode(unsigned opcode) const;
61 bool isReductionOp(unsigned opcode) const;
62 bool isCubeOp(unsigned opcode) const;
64 /// \returns true if this \p Opcode represents an ALU instruction.
65 bool isALUInstr(unsigned Opcode) const;
66 bool hasInstrModifiers(unsigned Opcode) const;
67 bool isLDSInstr(unsigned Opcode) const;
69 /// \returns true if this \p Opcode represents an ALU instruction or an
70 /// instruction that will be lowered in ExpandSpecialInstrs Pass.
71 bool canBeConsideredALU(const MachineInstr *MI) const;
73 bool isTransOnly(unsigned Opcode) const;
74 bool isTransOnly(const MachineInstr *MI) const;
75 bool isVectorOnly(unsigned Opcode) const;
76 bool isVectorOnly(const MachineInstr *MI) const;
77 bool isExport(unsigned Opcode) const;
79 bool usesVertexCache(unsigned Opcode) const;
80 bool usesVertexCache(const MachineInstr *MI) const;
81 bool usesTextureCache(unsigned Opcode) const;
82 bool usesTextureCache(const MachineInstr *MI) const;
84 bool mustBeLastInClause(unsigned Opcode) const;
85 bool readsLDSSrcReg(const MachineInstr *MI) const;
87 /// \returns The operand index for the given source number. Legal values
88 /// for SrcNum are 0, 1, and 2.
89 int getSrcIdx(unsigned Opcode, unsigned SrcNum) const;
90 /// \returns The operand Index for the Sel operand given an index to one
91 /// of the instruction's src operands.
92 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
94 /// \returns a pair for each src of an ALU instructions.
95 /// The first member of a pair is the register id.
96 /// If register is ALU_CONST, second member is SEL.
97 /// If register is ALU_LITERAL, second member is IMM.
98 /// Otherwise, second member value is undefined.
99 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
100 getSrcs(MachineInstr *MI) const;
102 unsigned isLegalUpTo(
103 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
104 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
105 const std::vector<std::pair<int, unsigned> > &TransSrcs,
106 R600InstrInfo::BankSwizzle TransSwz) const;
108 bool FindSwizzleForVectorSlot(
109 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
110 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
111 const std::vector<std::pair<int, unsigned> > &TransSrcs,
112 R600InstrInfo::BankSwizzle TransSwz) const;
114 /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
115 /// returns true and the first (in lexical order) BankSwizzle affectation
116 /// starting from the one already provided in the Instruction Group MIs that
117 /// fits Read Port limitations in BS if available. Otherwise returns false
118 /// and undefined content in BS.
119 /// isLastAluTrans should be set if the last Alu of MIs will be executed on
120 /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
121 /// apply to the last instruction.
122 /// PV holds GPR to PV registers in the Instruction Group MIs.
123 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
124 const DenseMap<unsigned, unsigned> &PV,
125 std::vector<BankSwizzle> &BS,
126 bool isLastAluTrans) const;
128 /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
129 /// from KCache bank on R700+. This function check if MI set in input meet
131 bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
132 /// Same but using const index set instead of MI set.
133 bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
135 /// \breif Vector instructions are instructions that must fill all
136 /// instruction slots within an instruction group.
137 bool isVector(const MachineInstr &MI) const;
139 virtual unsigned getIEQOpcode() const;
140 virtual bool isMov(unsigned Opcode) const;
142 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
143 const ScheduleDAG *DAG) const;
145 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
147 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
148 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
150 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
152 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
154 bool isPredicated(const MachineInstr *MI) const;
156 bool isPredicable(MachineInstr *MI) const;
159 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
160 const BranchProbability &Probability) const;
162 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
163 unsigned ExtraPredCycles,
164 const BranchProbability &Probability) const ;
167 isProfitableToIfCvt(MachineBasicBlock &TMBB,
168 unsigned NumTCycles, unsigned ExtraTCycles,
169 MachineBasicBlock &FMBB,
170 unsigned NumFCycles, unsigned ExtraFCycles,
171 const BranchProbability &Probability) const;
173 bool DefinesPredicate(MachineInstr *MI,
174 std::vector<MachineOperand> &Pred) const;
176 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
177 const SmallVectorImpl<MachineOperand> &Pred2) const;
179 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
180 MachineBasicBlock &FMBB) const;
182 bool PredicateInstruction(MachineInstr *MI,
183 const SmallVectorImpl<MachineOperand> &Pred) const;
185 unsigned int getPredicationCost(const MachineInstr *) const;
187 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
188 const MachineInstr *MI,
189 unsigned *PredCost = 0) const;
191 virtual int getInstrLatency(const InstrItineraryData *ItinData,
192 SDNode *Node) const { return 1;}
194 /// \returns a list of all the registers that may be accesed using indirect
196 std::vector<unsigned> getIndirectReservedRegs(const MachineFunction &MF) const;
198 virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
200 virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
203 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
204 unsigned Channel) const;
206 virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
207 unsigned SourceReg) const;
209 virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
211 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
212 MachineBasicBlock::iterator I,
213 unsigned ValueReg, unsigned Address,
214 unsigned OffsetReg) const;
216 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
217 MachineBasicBlock::iterator I,
218 unsigned ValueReg, unsigned Address,
219 unsigned OffsetReg) const;
221 virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
223 unsigned getMaxAlusPerClause() const;
225 ///buildDefaultInstruction - This function returns a MachineInstr with
226 /// all the instruction modifiers initialized to their default values.
227 /// You can use this function to avoid manually specifying each instruction
228 /// modifier operand when building a new instruction.
230 /// \returns a MachineInstr with all the instruction modifiers initialized
231 /// to their default values.
232 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
233 MachineBasicBlock::iterator I,
237 unsigned Src1Reg = 0) const;
239 MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
242 unsigned DstReg) const;
244 MachineInstr *buildMovImm(MachineBasicBlock &BB,
245 MachineBasicBlock::iterator I,
249 /// \brief Get the index of Op in the MachineInstr.
251 /// \returns -1 if the Instruction does not contain the specified \p Op.
252 int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
254 /// \brief Get the index of \p Op for the given Opcode.
256 /// \returns -1 if the Instruction does not contain the specified \p Op.
257 int getOperandIdx(unsigned Opcode, unsigned Op) const;
259 /// \brief Helper function for setting instruction flag values.
260 void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const;
262 /// \returns true if this instruction has an operand for storing target flags.
263 bool hasFlagOperand(const MachineInstr &MI) const;
265 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
266 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
268 ///\brief Determine if the specified \p Flag is set on this \p Operand.
269 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
271 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
272 /// \param Flag The flag being set.
274 /// \returns the operand containing the flags for this instruction.
275 MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
276 unsigned Flag = 0) const;
278 /// \brief Clear the specified flag on the instruction.
279 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
284 int getLDSNoRetOp(uint16_t Opcode);
286 } //End namespace AMDGPU
288 } // End llvm namespace
290 #endif // R600INSTRINFO_H_