1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for R600InstrInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef R600INSTRUCTIONINFO_H_
16 #define R600INSTRUCTIONINFO_H_
18 #include "AMDGPUInstrInfo.h"
19 #include "R600Defines.h"
20 #include "R600RegisterInfo.h"
25 class AMDGPUTargetMachine;
28 class MachineFunction;
30 class MachineInstrBuilder;
32 class R600InstrInfo : public AMDGPUInstrInfo {
34 const R600RegisterInfo RI;
35 const AMDGPUSubtarget &ST;
37 int getBranchInstr(const MachineOperand &op) const;
38 std::vector<std::pair<int, unsigned> >
39 ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const;
43 ALU_VEC_012_SCL_210 = 0,
51 explicit R600InstrInfo(AMDGPUTargetMachine &tm);
53 const R600RegisterInfo &getRegisterInfo() const;
54 virtual void copyPhysReg(MachineBasicBlock &MBB,
55 MachineBasicBlock::iterator MI, DebugLoc DL,
56 unsigned DestReg, unsigned SrcReg,
59 bool isTrig(const MachineInstr &MI) const;
60 bool isPlaceHolderOpcode(unsigned opcode) const;
61 bool isReductionOp(unsigned opcode) const;
62 bool isCubeOp(unsigned opcode) const;
64 /// \returns true if this \p Opcode represents an ALU instruction.
65 bool isALUInstr(unsigned Opcode) const;
66 bool hasInstrModifiers(unsigned Opcode) const;
67 bool isLDSInstr(unsigned Opcode) const;
69 bool isTransOnly(unsigned Opcode) const;
70 bool isTransOnly(const MachineInstr *MI) const;
71 bool isVectorOnly(unsigned Opcode) const;
72 bool isVectorOnly(const MachineInstr *MI) const;
73 bool isExport(unsigned Opcode) const;
75 bool usesVertexCache(unsigned Opcode) const;
76 bool usesVertexCache(const MachineInstr *MI) const;
77 bool usesTextureCache(unsigned Opcode) const;
78 bool usesTextureCache(const MachineInstr *MI) const;
80 bool mustBeLastInClause(unsigned Opcode) const;
81 bool readsLDSSrcReg(const MachineInstr *MI) const;
83 /// \returns The operand index for the given source number. Legal values
84 /// for SrcNum are 0, 1, and 2.
85 int getSrcIdx(unsigned Opcode, unsigned SrcNum) const;
86 /// \returns The operand Index for the Sel operand given an index to one
87 /// of the instruction's src operands.
88 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
90 /// \returns a pair for each src of an ALU instructions.
91 /// The first member of a pair is the register id.
92 /// If register is ALU_CONST, second member is SEL.
93 /// If register is ALU_LITERAL, second member is IMM.
94 /// Otherwise, second member value is undefined.
95 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
96 getSrcs(MachineInstr *MI) const;
99 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
100 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
101 const std::vector<std::pair<int, unsigned> > &TransSrcs,
102 R600InstrInfo::BankSwizzle TransSwz) const;
104 bool FindSwizzleForVectorSlot(
105 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
106 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
107 const std::vector<std::pair<int, unsigned> > &TransSrcs,
108 R600InstrInfo::BankSwizzle TransSwz) const;
110 /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
111 /// returns true and the first (in lexical order) BankSwizzle affectation
112 /// starting from the one already provided in the Instruction Group MIs that
113 /// fits Read Port limitations in BS if available. Otherwise returns false
114 /// and undefined content in BS.
115 /// isLastAluTrans should be set if the last Alu of MIs will be executed on
116 /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
117 /// apply to the last instruction.
118 /// PV holds GPR to PV registers in the Instruction Group MIs.
119 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
120 const DenseMap<unsigned, unsigned> &PV,
121 std::vector<BankSwizzle> &BS,
122 bool isLastAluTrans) const;
124 /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
125 /// from KCache bank on R700+. This function check if MI set in input meet
127 bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
128 /// Same but using const index set instead of MI set.
129 bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
131 /// \breif Vector instructions are instructions that must fill all
132 /// instruction slots within an instruction group.
133 bool isVector(const MachineInstr &MI) const;
135 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
138 virtual unsigned getIEQOpcode() const;
139 virtual bool isMov(unsigned Opcode) const;
141 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
142 const ScheduleDAG *DAG) const;
144 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
146 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
147 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
149 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
151 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
153 bool isPredicated(const MachineInstr *MI) const;
155 bool isPredicable(MachineInstr *MI) const;
158 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
159 const BranchProbability &Probability) const;
161 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
162 unsigned ExtraPredCycles,
163 const BranchProbability &Probability) const ;
166 isProfitableToIfCvt(MachineBasicBlock &TMBB,
167 unsigned NumTCycles, unsigned ExtraTCycles,
168 MachineBasicBlock &FMBB,
169 unsigned NumFCycles, unsigned ExtraFCycles,
170 const BranchProbability &Probability) const;
172 bool DefinesPredicate(MachineInstr *MI,
173 std::vector<MachineOperand> &Pred) const;
175 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
176 const SmallVectorImpl<MachineOperand> &Pred2) const;
178 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
179 MachineBasicBlock &FMBB) const;
181 bool PredicateInstruction(MachineInstr *MI,
182 const SmallVectorImpl<MachineOperand> &Pred) const;
184 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
185 const MachineInstr *MI,
186 unsigned *PredCost = 0) const;
188 virtual int getInstrLatency(const InstrItineraryData *ItinData,
189 SDNode *Node) const { return 1;}
191 /// \returns a list of all the registers that may be accesed using indirect
193 std::vector<unsigned> getIndirectReservedRegs(const MachineFunction &MF) const;
195 virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
197 virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
200 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
201 unsigned Channel) const;
203 virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
204 unsigned SourceReg) const;
206 virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
208 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
209 MachineBasicBlock::iterator I,
210 unsigned ValueReg, unsigned Address,
211 unsigned OffsetReg) const;
213 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
214 MachineBasicBlock::iterator I,
215 unsigned ValueReg, unsigned Address,
216 unsigned OffsetReg) const;
218 virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
220 unsigned getMaxAlusPerClause() const;
222 ///buildDefaultInstruction - This function returns a MachineInstr with
223 /// all the instruction modifiers initialized to their default values.
224 /// You can use this function to avoid manually specifying each instruction
225 /// modifier operand when building a new instruction.
227 /// \returns a MachineInstr with all the instruction modifiers initialized
228 /// to their default values.
229 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
230 MachineBasicBlock::iterator I,
234 unsigned Src1Reg = 0) const;
236 MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
239 unsigned DstReg) const;
241 MachineInstr *buildMovImm(MachineBasicBlock &BB,
242 MachineBasicBlock::iterator I,
246 /// \brief Get the index of Op in the MachineInstr.
248 /// \returns -1 if the Instruction does not contain the specified \p Op.
249 int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
251 /// \brief Get the index of \p Op for the given Opcode.
253 /// \returns -1 if the Instruction does not contain the specified \p Op.
254 int getOperandIdx(unsigned Opcode, unsigned Op) const;
256 /// \brief Helper function for setting instruction flag values.
257 void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const;
259 /// \returns true if this instruction has an operand for storing target flags.
260 bool hasFlagOperand(const MachineInstr &MI) const;
262 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
263 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
265 ///\brief Determine if the specified \p Flag is set on this \p Operand.
266 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
268 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
269 /// \param Flag The flag being set.
271 /// \returns the operand containing the flags for this instruction.
272 MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
273 unsigned Flag = 0) const;
275 /// \brief Clear the specified flag on the instruction.
276 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
281 int getLDSNoRetOp(uint16_t Opcode);
283 } //End namespace AMDGPU
285 } // End llvm namespace
287 #endif // R600INSTRINFO_H_