1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // R600 Tablegen instruction definitions
12 //===----------------------------------------------------------------------===//
14 include "R600Intrinsics.td"
16 class InstR600 <dag outs, dag ins, string asm, list<dag> pattern,
18 : AMDGPUInst <outs, ins, asm, pattern> {
25 bits<2> FlagOperandIdx = 0;
28 bit HasNativeOperands = 0;
32 let Namespace = "AMDGPU";
33 let OutOperandList = outs;
34 let InOperandList = ins;
36 let Pattern = pattern;
39 let TSFlags{0} = TransOnly;
40 let TSFlags{4} = Trig;
43 // Vector instructions are instructions that must fill all slots in an
45 let TSFlags{6} = isVector;
46 let TSFlags{8-7} = FlagOperandIdx;
47 let TSFlags{9} = HasNativeOperands;
48 let TSFlags{10} = Op1;
49 let TSFlags{11} = Op2;
50 let TSFlags{12} = VTXInst;
51 let TSFlags{13} = TEXInst;
54 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
55 InstR600 <outs, ins, asm, pattern, NullALU> {
57 let Namespace = "AMDGPU";
60 def MEMxi : Operand<iPTR> {
61 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
62 let PrintMethod = "printMemOperand";
65 def MEMrr : Operand<iPTR> {
66 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
69 // Operands for non-registers
71 class InstFlag<string PM = "printOperand", int Default = 0>
72 : OperandWithDefaultOps <i32, (ops (i32 Default))> {
76 // src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers
77 def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> {
78 let PrintMethod = "printSel";
80 def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> {
81 let PrintMethod = "printBankSwizzle";
84 def LITERAL : InstFlag<"printLiteral">;
86 def WRITE : InstFlag <"printWrite", 1>;
87 def OMOD : InstFlag <"printOMOD">;
88 def REL : InstFlag <"printRel">;
89 def CLAMP : InstFlag <"printClamp">;
90 def NEG : InstFlag <"printNeg">;
91 def ABS : InstFlag <"printAbs">;
92 def UEM : InstFlag <"printUpdateExecMask">;
93 def UP : InstFlag <"printUpdatePred">;
95 // XXX: The r600g finalizer in Mesa expects last to be one in most cases.
96 // Once we start using the packetizer in this backend we should have this
98 def LAST : InstFlag<"printLast", 1>;
100 def FRAMEri : Operand<iPTR> {
101 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index);
104 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
105 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
106 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
107 def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>;
108 def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>;
109 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
111 class R600ALU_Word0 {
112 field bits<32> Word0;
120 bits<3> index_mode = 0;
124 bits<9> src0_sel = src0{8-0};
125 bits<2> src0_chan = src0{10-9};
126 bits<9> src1_sel = src1{8-0};
127 bits<2> src1_chan = src1{10-9};
129 let Word0{8-0} = src0_sel;
130 let Word0{9} = src0_rel;
131 let Word0{11-10} = src0_chan;
132 let Word0{12} = src0_neg;
133 let Word0{21-13} = src1_sel;
134 let Word0{22} = src1_rel;
135 let Word0{24-23} = src1_chan;
136 let Word0{25} = src1_neg;
137 let Word0{28-26} = index_mode;
138 let Word0{30-29} = pred_sel;
139 let Word0{31} = last;
142 class R600ALU_Word1 {
143 field bits<32> Word1;
146 bits<3> bank_swizzle;
150 bits<7> dst_sel = dst{6-0};
151 bits<2> dst_chan = dst{10-9};
153 let Word1{20-18} = bank_swizzle;
154 let Word1{27-21} = dst_sel;
155 let Word1{28} = dst_rel;
156 let Word1{30-29} = dst_chan;
157 let Word1{31} = clamp;
160 class R600ALU_Word1_OP2 <bits<11> alu_inst> : R600ALU_Word1{
164 bits<1> update_exec_mask;
169 let Word1{0} = src0_abs;
170 let Word1{1} = src1_abs;
171 let Word1{2} = update_exec_mask;
172 let Word1{3} = update_pred;
173 let Word1{4} = write;
174 let Word1{6-5} = omod;
175 let Word1{17-7} = alu_inst;
178 class R600ALU_Word1_OP3 <bits<5> alu_inst> : R600ALU_Word1{
184 bits<9> src2_sel = src2{8-0};
185 bits<2> src2_chan = src2{10-9};
187 let Word1{8-0} = src2_sel;
188 let Word1{9} = src2_rel;
189 let Word1{11-10} = src2_chan;
190 let Word1{12} = src2_neg;
191 let Word1{17-13} = alu_inst;
195 field bits<32> Word0;
199 bits<1> FETCH_WHOLE_QUAD;
203 bits<6> MEGA_FETCH_COUNT;
205 let Word0{4-0} = VC_INST;
206 let Word0{6-5} = FETCH_TYPE;
207 let Word0{7} = FETCH_WHOLE_QUAD;
208 let Word0{15-8} = BUFFER_ID;
209 let Word0{22-16} = SRC_GPR;
210 let Word0{23} = SRC_REL;
211 let Word0{25-24} = SRC_SEL_X;
212 let Word0{31-26} = MEGA_FETCH_COUNT;
215 class VTX_WORD1_GPR {
216 field bits<32> Word1;
223 bits<1> USE_CONST_FIELDS;
225 bits<2> NUM_FORMAT_ALL;
226 bits<1> FORMAT_COMP_ALL;
227 bits<1> SRF_MODE_ALL;
229 let Word1{6-0} = DST_GPR;
230 let Word1{7} = DST_REL;
231 let Word1{8} = 0; // Reserved
232 let Word1{11-9} = DST_SEL_X;
233 let Word1{14-12} = DST_SEL_Y;
234 let Word1{17-15} = DST_SEL_Z;
235 let Word1{20-18} = DST_SEL_W;
236 let Word1{21} = USE_CONST_FIELDS;
237 let Word1{27-22} = DATA_FORMAT;
238 let Word1{29-28} = NUM_FORMAT_ALL;
239 let Word1{30} = FORMAT_COMP_ALL;
240 let Word1{31} = SRF_MODE_ALL;
244 field bits<32> Word0;
248 bits<1> FETCH_WHOLE_QUAD;
253 bits<2> RESOURCE_INDEX_MODE;
254 bits<2> SAMPLER_INDEX_MODE;
256 let Word0{4-0} = TEX_INST;
257 let Word0{6-5} = INST_MOD;
258 let Word0{7} = FETCH_WHOLE_QUAD;
259 let Word0{15-8} = RESOURCE_ID;
260 let Word0{22-16} = SRC_GPR;
261 let Word0{23} = SRC_REL;
262 let Word0{24} = ALT_CONST;
263 let Word0{26-25} = RESOURCE_INDEX_MODE;
264 let Word0{28-27} = SAMPLER_INDEX_MODE;
268 field bits<32> Word1;
277 bits<1> COORD_TYPE_X;
278 bits<1> COORD_TYPE_Y;
279 bits<1> COORD_TYPE_Z;
280 bits<1> COORD_TYPE_W;
282 let Word1{6-0} = DST_GPR;
283 let Word1{7} = DST_REL;
284 let Word1{11-9} = DST_SEL_X;
285 let Word1{14-12} = DST_SEL_Y;
286 let Word1{17-15} = DST_SEL_Z;
287 let Word1{20-18} = DST_SEL_W;
288 let Word1{27-21} = LOD_BIAS;
289 let Word1{28} = COORD_TYPE_X;
290 let Word1{29} = COORD_TYPE_Y;
291 let Word1{30} = COORD_TYPE_Z;
292 let Word1{31} = COORD_TYPE_W;
296 field bits<32> Word2;
307 let Word2{4-0} = OFFSET_X;
308 let Word2{9-5} = OFFSET_Y;
309 let Word2{14-10} = OFFSET_Z;
310 let Word2{19-15} = SAMPLER_ID;
311 let Word2{22-20} = SRC_SEL_X;
312 let Word2{25-23} = SRC_SEL_Y;
313 let Word2{28-26} = SRC_SEL_Z;
314 let Word2{31-29} = SRC_SEL_W;
318 XXX: R600 subtarget uses a slightly different encoding than the other
319 subtargets. We currently handle this in R600MCCodeEmitter, but we may
320 want to use these instruction classes in the future.
322 class R600ALU_Word1_OP2_r600 : R600ALU_Word1_OP2 {
327 let Inst{37} = fog_merge;
328 let Inst{39-38} = omod;
329 let Inst{49-40} = alu_inst;
332 class R600ALU_Word1_OP2_r700 : R600ALU_Word1_OP2 {
336 let Inst{38-37} = omod;
337 let Inst{49-39} = alu_inst;
341 def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
345 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
347 // Class for instructions with only one source register.
348 // If you add new ins to this instruction, make sure they are listed before
349 // $literal, because the backend currently assumes that the last operand is
350 // a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in
351 // R600Defines.h, R600InstrInfo::buildDefaultInstruction(),
352 // and R600InstrInfo::getOperandIdx().
353 class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
354 InstrItinClass itin = AnyALU> :
355 InstR600 <(outs R600_Reg32:$dst),
356 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
357 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
358 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
359 BANK_SWIZZLE:$bank_swizzle),
360 !strconcat(" ", opName,
361 "$last$clamp $dst$write$dst_rel$omod, "
362 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
363 "$pred_sel $bank_swizzle"),
367 R600ALU_Word1_OP2 <inst> {
373 let update_exec_mask = 0;
375 let HasNativeOperands = 1;
377 let DisableEncoding = "$literal";
379 let Inst{31-0} = Word0;
380 let Inst{63-32} = Word1;
383 class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
384 InstrItinClass itin = AnyALU> :
385 R600_1OP <inst, opName,
386 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))]
389 // If you add our change the operands for R600_2OP instructions, you must
390 // also update the R600Op2OperandIndex::ROI enum in R600Defines.h,
391 // R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx().
392 class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
393 InstrItinClass itin = AnyALU> :
394 InstR600 <(outs R600_Reg32:$dst),
395 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
396 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
397 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
398 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
399 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
400 BANK_SWIZZLE:$bank_swizzle),
401 !strconcat(" ", opName,
402 "$last$clamp $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
403 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
404 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
405 "$pred_sel $bank_swizzle"),
409 R600ALU_Word1_OP2 <inst> {
411 let HasNativeOperands = 1;
413 let DisableEncoding = "$literal";
415 let Inst{31-0} = Word0;
416 let Inst{63-32} = Word1;
419 class R600_2OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
420 InstrItinClass itim = AnyALU> :
421 R600_2OP <inst, opName,
422 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
426 // If you add our change the operands for R600_3OP instructions, you must
427 // also update the R600Op3OperandIndex::ROI enum in R600Defines.h,
428 // R600InstrInfo::buildDefaultInstruction(), and
429 // R600InstrInfo::getOperandIdx().
430 class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
431 InstrItinClass itin = AnyALU> :
432 InstR600 <(outs R600_Reg32:$dst),
433 (ins REL:$dst_rel, CLAMP:$clamp,
434 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
435 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
436 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,
437 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
438 BANK_SWIZZLE:$bank_swizzle),
439 !strconcat(" ", opName, "$last$clamp $dst$dst_rel, "
440 "$src0_neg$src0$src0_rel, "
441 "$src1_neg$src1$src1_rel, "
442 "$src2_neg$src2$src2_rel, "
448 R600ALU_Word1_OP3<inst>{
450 let HasNativeOperands = 1;
451 let DisableEncoding = "$literal";
454 let Inst{31-0} = Word0;
455 let Inst{63-32} = Word1;
458 class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern,
459 InstrItinClass itin = VecALU> :
460 InstR600 <(outs R600_Reg32:$dst),
466 class R600_TEX <bits<11> inst, string opName, list<dag> pattern,
467 InstrItinClass itin = AnyALU> :
468 InstR600 <(outs R600_Reg128:$DST_GPR),
469 (ins R600_Reg128:$SRC_GPR, i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID, i32imm:$textureTarget),
470 !strconcat(opName, "$DST_GPR, $SRC_GPR, $RESOURCE_ID, $SAMPLER_ID, $textureTarget"),
472 itin>, TEX_WORD0, TEX_WORD1, TEX_WORD2 {
473 let Inst{31-0} = Word0;
474 let Inst{63-32} = Word1;
476 let TEX_INST = inst{4-0};
486 let FETCH_WHOLE_QUAD = 0;
488 let SAMPLER_INDEX_MODE = 0;
489 let RESOURCE_INDEX_MODE = 0;
491 let COORD_TYPE_X = 0;
492 let COORD_TYPE_Y = 0;
493 let COORD_TYPE_Z = 0;
494 let COORD_TYPE_W = 0;
499 } // End mayLoad = 1, mayStore = 0, hasSideEffects = 0
501 def TEX_SHADOW : PatLeaf<
503 [{uint32_t TType = (uint32_t)N->getZExtValue();
504 return (TType >= 6 && TType <= 8) || (TType >= 11 && TType <= 13);
508 def TEX_RECT : PatLeaf<
510 [{uint32_t TType = (uint32_t)N->getZExtValue();
515 def TEX_ARRAY : PatLeaf<
517 [{uint32_t TType = (uint32_t)N->getZExtValue();
518 return TType == 9 || TType == 10 || TType == 15 || TType == 16;
522 def TEX_SHADOW_ARRAY : PatLeaf<
524 [{uint32_t TType = (uint32_t)N->getZExtValue();
525 return TType == 11 || TType == 12 || TType == 17;
529 class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
530 dag ins, string asm, list<dag> pattern> :
531 InstR600ISA <outs, ins, asm, pattern> {
548 // CF_ALLOC_EXPORT_WORD0_RAT
549 let Inst{3-0} = rat_id;
550 let Inst{9-4} = rat_inst;
551 let Inst{10} = 0; // Reserved
552 let Inst{12-11} = RIM;
553 let Inst{14-13} = TYPE;
554 let Inst{21-15} = RW_GPR;
555 let Inst{22} = RW_REL;
556 let Inst{29-23} = INDEX_GPR;
557 let Inst{31-30} = ELEM_SIZE;
559 // CF_ALLOC_EXPORT_WORD1_BUF
560 let Inst{43-32} = ARRAY_SIZE;
561 let Inst{47-44} = COMP_MASK;
562 let Inst{51-48} = BURST_COUNT;
565 let Inst{61-54} = cf_inst;
567 let Inst{63} = BARRIER;
570 class LoadParamFrag <PatFrag load_type> : PatFrag <
571 (ops node:$ptr), (load_type node:$ptr),
572 [{ return isParamLoad(dyn_cast<LoadSDNode>(N)); }]
575 def load_param : LoadParamFrag<load>;
576 def load_param_zexti8 : LoadParamFrag<zextloadi8>;
577 def load_param_zexti16 : LoadParamFrag<zextloadi16>;
579 def isR600 : Predicate<"Subtarget.device()"
580 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX">;
581 def isR700 : Predicate<"Subtarget.device()"
582 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX &&"
583 "Subtarget.device()->getDeviceFlag()"
584 ">= OCL_DEVICE_RV710">;
585 def isEG : Predicate<
586 "Subtarget.device()->getGeneration() >= AMDGPUDeviceInfo::HD5XXX && "
587 "Subtarget.device()->getGeneration() < AMDGPUDeviceInfo::HD7XXX && "
588 "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">;
590 def isCayman : Predicate<"Subtarget.device()"
591 "->getDeviceFlag() == OCL_DEVICE_CAYMAN">;
592 def isEGorCayman : Predicate<"Subtarget.device()"
593 "->getGeneration() == AMDGPUDeviceInfo::HD5XXX"
594 "|| Subtarget.device()->getGeneration() =="
595 "AMDGPUDeviceInfo::HD6XXX">;
597 def isR600toCayman : Predicate<
598 "Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX">;
600 //===----------------------------------------------------------------------===//
602 //===----------------------------------------------------------------------===//
604 def INTERP_PAIR_XY : AMDGPUShaderInst <
605 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1),
606 (ins i32imm:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
607 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
610 def INTERP_PAIR_ZW : AMDGPUShaderInst <
611 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1),
612 (ins i32imm:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
613 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",
616 def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS",
617 SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>,
621 //===----------------------------------------------------------------------===//
622 // Interpolation Instructions
623 //===----------------------------------------------------------------------===//
625 def INTERP_VEC_LOAD : AMDGPUShaderInst <
626 (outs R600_Reg128:$dst),
628 "INTERP_LOAD $src0 : $dst",
631 def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> {
632 let bank_swizzle = 5;
635 def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> {
636 let bank_swizzle = 5;
639 def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>;
641 //===----------------------------------------------------------------------===//
642 // Export Instructions
643 //===----------------------------------------------------------------------===//
645 def ExportType : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
647 def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType,
648 [SDNPHasChain, SDNPSideEffect]>;
651 field bits<32> Word0;
658 let Word0{12-0} = arraybase;
659 let Word0{14-13} = type;
660 let Word0{21-15} = gpr;
661 let Word0{22} = 0; // RW_REL
662 let Word0{29-23} = 0; // INDEX_GPR
663 let Word0{31-30} = elem_size;
666 class ExportSwzWord1 {
667 field bits<32> Word1;
676 let Word1{2-0} = sw_x;
677 let Word1{5-3} = sw_y;
678 let Word1{8-6} = sw_z;
679 let Word1{11-9} = sw_w;
682 class ExportBufWord1 {
683 field bits<32> Word1;
690 let Word1{11-0} = arraySize;
691 let Word1{15-12} = compMask;
694 multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
695 def : Pat<(int_R600_store_pixel_depth R600_Reg32:$reg),
697 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
698 0, 61, 0, 7, 7, 7, cf_inst, 0)
701 def : Pat<(int_R600_store_pixel_stencil R600_Reg32:$reg),
703 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
704 0, 61, 7, 0, 7, 7, cf_inst, 0)
707 def : Pat<(int_R600_store_dummy (i32 imm:$type)),
709 (v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0)
712 def : Pat<(int_R600_store_dummy 1),
714 (v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0)
717 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
718 (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)),
719 (ExportInst R600_Reg128:$src, imm:$type, imm:$base,
720 imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0)
725 multiclass SteamOutputExportPattern<Instruction ExportInst,
726 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> {
728 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
729 (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)),
730 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
731 4095, imm:$mask, buf0inst, 0)>;
733 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
734 (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)),
735 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
736 4095, imm:$mask, buf1inst, 0)>;
738 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
739 (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)),
740 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
741 4095, imm:$mask, buf2inst, 0)>;
743 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
744 (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)),
745 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
746 4095, imm:$mask, buf3inst, 0)>;
749 // Export Instructions should not be duplicated by TailDuplication pass
750 // (which assumes that duplicable instruction are affected by exec mask)
751 let usesCustomInserter = 1, isNotDuplicable = 1 in {
753 class ExportSwzInst : InstR600ISA<(
755 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
756 i32imm:$sw_x, i32imm:$sw_y, i32imm:$sw_z, i32imm:$sw_w, i32imm:$inst,
758 !strconcat("EXPORT", " $gpr"),
759 []>, ExportWord0, ExportSwzWord1 {
761 let Inst{31-0} = Word0;
762 let Inst{63-32} = Word1;
765 } // End usesCustomInserter = 1
767 class ExportBufInst : InstR600ISA<(
769 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
770 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop),
771 !strconcat("EXPORT", " $gpr"),
772 []>, ExportWord0, ExportBufWord1 {
774 let Inst{31-0} = Word0;
775 let Inst{63-32} = Word1;
778 //===----------------------------------------------------------------------===//
779 // Control Flow Instructions
780 //===----------------------------------------------------------------------===//
783 field bits<32> Word0;
786 bits<4> KCACHE_BANK0;
787 bits<4> KCACHE_BANK1;
788 bits<2> KCACHE_MODE0;
790 let Word0{21-0} = ADDR;
791 let Word0{25-22} = KCACHE_BANK0;
792 let Word0{29-26} = KCACHE_BANK1;
793 let Word0{31-30} = KCACHE_MODE0;
797 field bits<32> Word1;
799 bits<2> KCACHE_MODE1;
800 bits<8> KCACHE_ADDR0;
801 bits<8> KCACHE_ADDR1;
805 bits<1> WHOLE_QUAD_MODE;
808 let Word1{1-0} = KCACHE_MODE1;
809 let Word1{9-2} = KCACHE_ADDR0;
810 let Word1{17-10} = KCACHE_ADDR1;
811 let Word1{24-18} = COUNT;
812 let Word1{25} = ALT_CONST;
813 let Word1{29-26} = CF_INST;
814 let Word1{30} = WHOLE_QUAD_MODE;
815 let Word1{31} = BARRIER;
818 def KCACHE : InstFlag<"printKCache">;
820 class ALU_CLAUSE<bits<4> inst, string OpName> : AMDGPUInst <(outs),
821 (ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1,
822 KCACHE:$KCACHE_MODE0, KCACHE:$KCACHE_MODE1,
823 i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1,
825 !strconcat(OpName, " $COUNT, @$ADDR, "
826 "KC0[$KCACHE_MODE0], KC1[$KCACHE_MODE1]"),
827 [] >, CF_ALU_WORD0, CF_ALU_WORD1 {
832 let WHOLE_QUAD_MODE = 0;
835 let Inst{31-0} = Word0;
836 let Inst{63-32} = Word1;
839 class CF_WORD0_R600 {
840 field bits<32> Word0;
847 class CF_WORD1_R600 {
848 field bits<32> Word1;
856 bits<1> END_OF_PROGRAM;
857 bits<1> VALID_PIXEL_MODE;
859 bits<1> WHOLE_QUAD_MODE;
862 let Word1{2-0} = POP_COUNT;
863 let Word1{7-3} = CF_CONST;
864 let Word1{9-8} = COND;
865 let Word1{12-10} = COUNT;
866 let Word1{18-13} = CALL_COUNT;
867 let Word1{19} = COUNT_3;
868 let Word1{21} = END_OF_PROGRAM;
869 let Word1{22} = VALID_PIXEL_MODE;
870 let Word1{29-23} = CF_INST;
871 let Word1{30} = WHOLE_QUAD_MODE;
872 let Word1{31} = BARRIER;
875 class CF_CLAUSE_R600 <bits<7> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
876 ins, AsmPrint, [] >, CF_WORD0_R600, CF_WORD1_R600 {
882 let VALID_PIXEL_MODE = 0;
886 let END_OF_PROGRAM = 0;
887 let WHOLE_QUAD_MODE = 0;
889 let Inst{31-0} = Word0;
890 let Inst{63-32} = Word1;
894 field bits<32> Word0;
897 bits<3> JUMPTABLE_SEL;
899 let Word0{23-0} = ADDR;
900 let Word0{26-24} = JUMPTABLE_SEL;
904 field bits<32> Word1;
910 bits<1> VALID_PIXEL_MODE;
911 bits<1> END_OF_PROGRAM;
915 let Word1{2-0} = POP_COUNT;
916 let Word1{7-3} = CF_CONST;
917 let Word1{9-8} = COND;
918 let Word1{15-10} = COUNT;
919 let Word1{20} = VALID_PIXEL_MODE;
920 let Word1{21} = END_OF_PROGRAM;
921 let Word1{29-22} = CF_INST;
922 let Word1{31} = BARRIER;
925 class CF_CLAUSE_EG <bits<8> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
926 ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG {
931 let JUMPTABLE_SEL = 0;
933 let VALID_PIXEL_MODE = 0;
935 let END_OF_PROGRAM = 0;
937 let Inst{31-0} = Word0;
938 let Inst{63-32} = Word1;
941 def CF_ALU : ALU_CLAUSE<8, "ALU">;
942 def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">;
944 def FETCH_CLAUSE : AMDGPUInst <(outs),
945 (ins i32imm:$addr), "Fetch clause starting at $addr:", [] > {
951 def ALU_CLAUSE : AMDGPUInst <(outs),
952 (ins i32imm:$addr), "ALU clause starting at $addr:", [] > {
958 def LITERALS : AMDGPUInst <(outs),
959 (ins LITERAL:$literal1, LITERAL:$literal2), "$literal1, $literal2", [] > {
964 let Inst{31-0} = literal1;
965 let Inst{63-32} = literal2;
968 def PAD : AMDGPUInst <(outs), (ins), "PAD", [] > {
972 let Predicates = [isR600toCayman] in {
974 //===----------------------------------------------------------------------===//
975 // Common Instructions R600, R700, Evergreen, Cayman
976 //===----------------------------------------------------------------------===//
978 def ADD : R600_2OP_Helper <0x0, "ADD", fadd>;
979 // Non-IEEE MUL: 0 * anything = 0
980 def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE", int_AMDGPU_mul>;
981 def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>;
982 def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax>;
983 def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin>;
985 // For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
986 // so some of the instruction names don't match the asm string.
987 // XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
988 def SETE : R600_2OP <
990 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_EQ))]
995 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_GT))]
1000 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_GE))]
1003 def SNE : R600_2OP <
1005 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_NE))]
1008 def SETE_DX10 : R600_2OP <
1010 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_EQ))]
1013 def SETGT_DX10 : R600_2OP <
1015 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_GT))]
1018 def SETGE_DX10 : R600_2OP <
1020 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_GE))]
1023 def SETNE_DX10 : R600_2OP <
1025 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_NE))]
1028 def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>;
1029 def TRUNC : R600_1OP_Helper <0x11, "TRUNC", int_AMDGPU_trunc>;
1030 def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;
1031 def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>;
1032 def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>;
1034 def MOV : R600_1OP <0x19, "MOV", []>;
1036 let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in {
1038 class MOV_IMM <ValueType vt, Operand immType> : AMDGPUInst <
1039 (outs R600_Reg32:$dst),
1045 } // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1
1047 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
1050 (MOV_IMM_I32 imm:$val)
1053 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
1056 (MOV_IMM_F32 fpimm:$val)
1059 def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>;
1060 def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>;
1061 def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>;
1062 def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>;
1064 let hasSideEffects = 1 in {
1066 def KILLGT : R600_2OP <0x2D, "KILLGT", []>;
1068 } // end hasSideEffects
1070 def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>;
1071 def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>;
1072 def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>;
1073 def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>;
1074 def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>;
1075 def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>;
1076 def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", AMDGPUsmax>;
1077 def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", AMDGPUsmin>;
1078 def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", AMDGPUumax>;
1079 def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", AMDGPUumin>;
1081 def SETE_INT : R600_2OP <
1083 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETEQ))]
1086 def SETGT_INT : R600_2OP <
1088 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGT))]
1091 def SETGE_INT : R600_2OP <
1093 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))]
1096 def SETNE_INT : R600_2OP <
1098 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETNE))]
1101 def SETGT_UINT : R600_2OP <
1103 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGT))]
1106 def SETGE_UINT : R600_2OP <
1108 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGE))]
1111 def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>;
1112 def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>;
1113 def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>;
1114 def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>;
1116 def CNDE_INT : R600_3OP <
1118 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_EQ))]
1121 def CNDGE_INT : R600_3OP <
1123 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_GE))]
1126 def CNDGT_INT : R600_3OP <
1128 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_GT))]
1131 //===----------------------------------------------------------------------===//
1132 // Texture instructions
1133 //===----------------------------------------------------------------------===//
1135 def TEX_LD : R600_TEX <
1137 [(set v4f32:$DST_GPR, (int_AMDGPU_txf v4f32:$SRC_GPR,
1138 imm:$OFFSET_X, imm:$OFFSET_Y, imm:$OFFSET_Z, imm:$RESOURCE_ID,
1139 imm:$SAMPLER_ID, imm:$textureTarget))]
1141 let AsmString = "TEX_LD $DST_GPR, $SRC_GPR, $OFFSET_X, $OFFSET_Y, $OFFSET_Z,"
1142 "$RESOURCE_ID, $SAMPLER_ID, $textureTarget";
1143 let InOperandList = (ins R600_Reg128:$SRC_GPR, i32imm:$OFFSET_X,
1144 i32imm:$OFFSET_Y, i32imm:$OFFSET_Z, i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID,
1145 i32imm:$textureTarget);
1148 def TEX_GET_TEXTURE_RESINFO : R600_TEX <
1149 0x04, "TEX_GET_TEXTURE_RESINFO",
1150 [(set v4f32:$DST_GPR, (int_AMDGPU_txq v4f32:$SRC_GPR,
1151 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1154 def TEX_GET_GRADIENTS_H : R600_TEX <
1155 0x07, "TEX_GET_GRADIENTS_H",
1156 [(set v4f32:$DST_GPR, (int_AMDGPU_ddx v4f32:$SRC_GPR,
1157 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1160 def TEX_GET_GRADIENTS_V : R600_TEX <
1161 0x08, "TEX_GET_GRADIENTS_V",
1162 [(set v4f32:$DST_GPR, (int_AMDGPU_ddy v4f32:$SRC_GPR,
1163 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1166 def TEX_SET_GRADIENTS_H : R600_TEX <
1167 0x0B, "TEX_SET_GRADIENTS_H",
1171 def TEX_SET_GRADIENTS_V : R600_TEX <
1172 0x0C, "TEX_SET_GRADIENTS_V",
1176 def TEX_SAMPLE : R600_TEX <
1178 [(set v4f32:$DST_GPR, (int_AMDGPU_tex v4f32:$SRC_GPR,
1179 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1182 def TEX_SAMPLE_C : R600_TEX <
1183 0x18, "TEX_SAMPLE_C",
1184 [(set v4f32:$DST_GPR, (int_AMDGPU_tex v4f32:$SRC_GPR,
1185 imm:$RESOURCE_ID, imm:$SAMPLER_ID, TEX_SHADOW:$textureTarget))]
1188 def TEX_SAMPLE_L : R600_TEX <
1189 0x11, "TEX_SAMPLE_L",
1190 [(set v4f32:$DST_GPR, (int_AMDGPU_txl v4f32:$SRC_GPR,
1191 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1194 def TEX_SAMPLE_C_L : R600_TEX <
1195 0x19, "TEX_SAMPLE_C_L",
1196 [(set v4f32:$DST_GPR, (int_AMDGPU_txl v4f32:$SRC_GPR,
1197 imm:$RESOURCE_ID, imm:$SAMPLER_ID, TEX_SHADOW:$textureTarget))]
1200 def TEX_SAMPLE_LB : R600_TEX <
1201 0x12, "TEX_SAMPLE_LB",
1202 [(set v4f32:$DST_GPR, (int_AMDGPU_txb v4f32:$SRC_GPR,
1203 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1206 def TEX_SAMPLE_C_LB : R600_TEX <
1207 0x1A, "TEX_SAMPLE_C_LB",
1208 [(set v4f32:$DST_GPR, (int_AMDGPU_txb v4f32:$SRC_GPR,
1209 imm:$RESOURCE_ID, imm:$SAMPLER_ID, TEX_SHADOW:$textureTarget))]
1212 def TEX_SAMPLE_G : R600_TEX <
1213 0x14, "TEX_SAMPLE_G",
1217 def TEX_SAMPLE_C_G : R600_TEX <
1218 0x1C, "TEX_SAMPLE_C_G",
1222 //===----------------------------------------------------------------------===//
1223 // Helper classes for common instructions
1224 //===----------------------------------------------------------------------===//
1226 class MUL_LIT_Common <bits<5> inst> : R600_3OP <
1231 class MULADD_Common <bits<5> inst> : R600_3OP <
1236 class MULADD_IEEE_Common <bits<5> inst> : R600_3OP <
1237 inst, "MULADD_IEEE",
1238 [(set f32:$dst, (fadd (fmul f32:$src0, f32:$src1), f32:$src2))]
1241 class CNDE_Common <bits<5> inst> : R600_3OP <
1243 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_EQ))]
1246 class CNDGT_Common <bits<5> inst> : R600_3OP <
1248 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_GT))]
1251 class CNDGE_Common <bits<5> inst> : R600_3OP <
1253 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_GE))]
1256 multiclass DOT4_Common <bits<11> inst> {
1258 def _pseudo : R600_REDUCTION <inst,
1259 (ins R600_Reg128:$src0, R600_Reg128:$src1),
1260 "DOT4 $dst $src0, $src1",
1261 [(set f32:$dst, (int_AMDGPU_dp4 v4f32:$src0, v4f32:$src1))]
1264 def _real : R600_2OP <inst, "DOT4", []>;
1267 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
1268 multiclass CUBE_Common <bits<11> inst> {
1270 def _pseudo : InstR600 <
1271 (outs R600_Reg128:$dst),
1272 (ins R600_Reg128:$src),
1274 [(set v4f32:$dst, (int_AMDGPU_cube v4f32:$src))],
1280 def _real : R600_2OP <inst, "CUBE", []>;
1282 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
1284 class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1285 inst, "EXP_IEEE", fexp2
1288 let Itinerary = TransALU;
1291 class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper <
1292 inst, "FLT_TO_INT", fp_to_sint
1295 let Itinerary = TransALU;
1298 class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1299 inst, "INT_TO_FLT", sint_to_fp
1302 let Itinerary = TransALU;
1305 class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1306 inst, "FLT_TO_UINT", fp_to_uint
1309 let Itinerary = TransALU;
1312 class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1313 inst, "UINT_TO_FLT", uint_to_fp
1316 let Itinerary = TransALU;
1319 class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <
1320 inst, "LOG_CLAMPED", []
1323 class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1324 inst, "LOG_IEEE", flog2
1327 let Itinerary = TransALU;
1330 class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>;
1331 class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>;
1332 class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>;
1333 class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper <
1334 inst, "MULHI_INT", mulhs
1337 let Itinerary = TransALU;
1339 class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper <
1340 inst, "MULHI", mulhu
1343 let Itinerary = TransALU;
1345 class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper <
1346 inst, "MULLO_INT", mul
1349 let Itinerary = TransALU;
1351 class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []> {
1353 let Itinerary = TransALU;
1356 class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <
1357 inst, "RECIP_CLAMPED", []
1360 let Itinerary = TransALU;
1363 class RECIP_IEEE_Common <bits<11> inst> : R600_1OP <
1364 inst, "RECIP_IEEE", [(set f32:$dst, (fdiv FP_ONE, f32:$src0))]
1367 let Itinerary = TransALU;
1370 class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1371 inst, "RECIP_UINT", AMDGPUurecip
1374 let Itinerary = TransALU;
1377 class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper <
1378 inst, "RECIPSQRT_CLAMPED", int_AMDGPU_rsq
1381 let Itinerary = TransALU;
1384 class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP <
1385 inst, "RECIPSQRT_IEEE", []
1388 let Itinerary = TransALU;
1391 class SIN_Common <bits<11> inst> : R600_1OP <
1395 let Itinerary = TransALU;
1398 class COS_Common <bits<11> inst> : R600_1OP <
1402 let Itinerary = TransALU;
1405 //===----------------------------------------------------------------------===//
1406 // Helper patterns for complex intrinsics
1407 //===----------------------------------------------------------------------===//
1409 multiclass DIV_Common <InstR600 recip_ieee> {
1411 (int_AMDGPU_div f32:$src0, f32:$src1),
1412 (MUL_IEEE $src0, (recip_ieee $src1))
1416 (fdiv f32:$src0, f32:$src1),
1417 (MUL_IEEE $src0, (recip_ieee $src1))
1421 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee>
1423 (int_TGSI_lit_z f32:$src_x, f32:$src_y, f32:$src_w),
1424 (exp_ieee (mul_lit (log_clamped (MAX $src_y, (f32 ZERO))), $src_w, $src_x))
1427 //===----------------------------------------------------------------------===//
1428 // R600 / R700 Instructions
1429 //===----------------------------------------------------------------------===//
1431 let Predicates = [isR600] in {
1433 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
1434 def MULADD_r600 : MULADD_Common<0x10>;
1435 def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>;
1436 def CNDE_r600 : CNDE_Common<0x18>;
1437 def CNDGT_r600 : CNDGT_Common<0x19>;
1438 def CNDGE_r600 : CNDGE_Common<0x1A>;
1439 defm DOT4_r600 : DOT4_Common<0x50>;
1440 defm CUBE_r600 : CUBE_Common<0x52>;
1441 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
1442 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
1443 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
1444 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
1445 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
1446 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
1447 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
1448 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
1449 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
1450 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
1451 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
1452 def SIN_r600 : SIN_Common<0x6E>;
1453 def COS_r600 : COS_Common<0x6F>;
1454 def ASHR_r600 : ASHR_Common<0x70>;
1455 def LSHR_r600 : LSHR_Common<0x71>;
1456 def LSHL_r600 : LSHL_Common<0x72>;
1457 def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
1458 def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
1459 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
1460 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
1461 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
1463 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
1464 def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL>;
1465 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
1467 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>;
1469 def R600_ExportSwz : ExportSwzInst {
1470 let Word1{20-17} = 0; // BURST_COUNT
1471 let Word1{21} = eop;
1472 let Word1{22} = 1; // VALID_PIXEL_MODE
1473 let Word1{30-23} = inst;
1474 let Word1{31} = 1; // BARRIER
1476 defm : ExportPattern<R600_ExportSwz, 39>;
1478 def R600_ExportBuf : ExportBufInst {
1479 let Word1{20-17} = 0; // BURST_COUNT
1480 let Word1{21} = eop;
1481 let Word1{22} = 1; // VALID_PIXEL_MODE
1482 let Word1{30-23} = inst;
1483 let Word1{31} = 1; // BARRIER
1485 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>;
1487 def CF_TC_R600 : CF_CLAUSE_R600<1, (ins i32imm:$ADDR, i32imm:$COUNT),
1488 "TEX $COUNT @$ADDR"> {
1491 def CF_VC_R600 : CF_CLAUSE_R600<2, (ins i32imm:$ADDR, i32imm:$COUNT),
1492 "VTX $COUNT @$ADDR"> {
1495 def WHILE_LOOP_R600 : CF_CLAUSE_R600<6, (ins i32imm:$ADDR),
1496 "LOOP_START_DX10 @$ADDR"> {
1500 def END_LOOP_R600 : CF_CLAUSE_R600<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1504 def LOOP_BREAK_R600 : CF_CLAUSE_R600<9, (ins i32imm:$ADDR),
1505 "LOOP_BREAK @$ADDR"> {
1509 def CF_CONTINUE_R600 : CF_CLAUSE_R600<8, (ins i32imm:$ADDR),
1510 "CONTINUE @$ADDR"> {
1514 def CF_JUMP_R600 : CF_CLAUSE_R600<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1515 "JUMP @$ADDR POP:$POP_COUNT"> {
1518 def CF_ELSE_R600 : CF_CLAUSE_R600<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1519 "ELSE @$ADDR POP:$POP_COUNT"> {
1522 def CF_CALL_FS_R600 : CF_CLAUSE_R600<19, (ins), "CALL_FS"> {
1527 def POP_R600 : CF_CLAUSE_R600<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1528 "POP @$ADDR POP:$POP_COUNT"> {
1531 def CF_END_R600 : CF_CLAUSE_R600<0, (ins), "CF_END"> {
1535 let END_OF_PROGRAM = 1;
1540 // Helper pattern for normalizing inputs to triginomic instructions for R700+
1542 class COS_PAT <InstR600 trig> : Pat<
1544 (trig (MUL_IEEE (MOV_IMM_I32 CONST.TWO_PI_INV), $src))
1547 class SIN_PAT <InstR600 trig> : Pat<
1549 (trig (MUL_IEEE (MOV_IMM_I32 CONST.TWO_PI_INV), $src))
1552 //===----------------------------------------------------------------------===//
1553 // R700 Only instructions
1554 //===----------------------------------------------------------------------===//
1556 let Predicates = [isR700] in {
1557 def SIN_r700 : SIN_Common<0x6E>;
1558 def COS_r700 : COS_Common<0x6F>;
1560 // R700 normalizes inputs to SIN/COS the same as EG
1561 def : SIN_PAT <SIN_r700>;
1562 def : COS_PAT <COS_r700>;
1565 //===----------------------------------------------------------------------===//
1566 // Evergreen Only instructions
1567 //===----------------------------------------------------------------------===//
1569 let Predicates = [isEG] in {
1571 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
1572 defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
1574 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
1575 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
1576 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
1577 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
1578 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
1579 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
1580 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
1581 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
1582 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
1583 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
1584 def SIN_eg : SIN_Common<0x8D>;
1585 def COS_eg : COS_Common<0x8E>;
1587 def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>;
1588 def : SIN_PAT <SIN_eg>;
1589 def : COS_PAT <COS_eg>;
1590 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>;
1591 } // End Predicates = [isEG]
1593 //===----------------------------------------------------------------------===//
1594 // Evergreen / Cayman Instructions
1595 //===----------------------------------------------------------------------===//
1597 let Predicates = [isEGorCayman] in {
1599 // BFE_UINT - bit_extract, an optimization for mask and shift
1604 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
1609 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0
1610 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
1611 // (16,8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
1612 // (24,8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
1613 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
1614 [(set i32:$dst, (int_AMDIL_bit_extract_u32 i32:$src0, i32:$src1,
1619 def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", [], VecALU>;
1620 defm : BFIPatterns <BFI_INT_eg>;
1622 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT",
1623 [(set i32:$dst, (AMDGPUbitalign i32:$src0, i32:$src1, i32:$src2))],
1627 def MULADD_eg : MULADD_Common<0x14>;
1628 def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>;
1629 def ASHR_eg : ASHR_Common<0x15>;
1630 def LSHR_eg : LSHR_Common<0x16>;
1631 def LSHL_eg : LSHL_Common<0x17>;
1632 def CNDE_eg : CNDE_Common<0x19>;
1633 def CNDGT_eg : CNDGT_Common<0x1A>;
1634 def CNDGE_eg : CNDGE_Common<0x1B>;
1635 def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
1636 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
1637 defm DOT4_eg : DOT4_Common<0xBE>;
1638 defm CUBE_eg : CUBE_Common<0xC0>;
1640 let hasSideEffects = 1 in {
1641 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", []>;
1644 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
1646 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
1650 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
1652 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
1656 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
1658 // TRUNC is used for the FLT_TO_INT instructions to work around a
1659 // perceived problem where the rounding modes are applied differently
1660 // depending on the instruction and the slot they are in.
1662 // https://bugs.freedesktop.org/show_bug.cgi?id=50232
1663 // Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c
1665 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
1666 // which do not need to be truncated since the fp values are 0.0f or 1.0f.
1667 // We should look into handling these cases separately.
1668 def : Pat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>;
1670 def : Pat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>;
1673 def : SHA256MaPattern <BFI_INT_eg, XOR_INT>;
1675 def EG_ExportSwz : ExportSwzInst {
1676 let Word1{19-16} = 0; // BURST_COUNT
1677 let Word1{20} = 1; // VALID_PIXEL_MODE
1678 let Word1{21} = eop;
1679 let Word1{29-22} = inst;
1680 let Word1{30} = 0; // MARK
1681 let Word1{31} = 1; // BARRIER
1683 defm : ExportPattern<EG_ExportSwz, 83>;
1685 def EG_ExportBuf : ExportBufInst {
1686 let Word1{19-16} = 0; // BURST_COUNT
1687 let Word1{20} = 1; // VALID_PIXEL_MODE
1688 let Word1{21} = eop;
1689 let Word1{29-22} = inst;
1690 let Word1{30} = 0; // MARK
1691 let Word1{31} = 1; // BARRIER
1693 defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>;
1695 def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT),
1696 "TEX $COUNT @$ADDR"> {
1699 def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT),
1700 "VTX $COUNT @$ADDR"> {
1703 def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR),
1704 "LOOP_START_DX10 @$ADDR"> {
1708 def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1712 def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR),
1713 "LOOP_BREAK @$ADDR"> {
1717 def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR),
1718 "CONTINUE @$ADDR"> {
1722 def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1723 "JUMP @$ADDR POP:$POP_COUNT"> {
1726 def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1727 "ELSE @$ADDR POP:$POP_COUNT"> {
1730 def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> {
1735 def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1736 "POP @$ADDR POP:$POP_COUNT"> {
1739 def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> {
1743 let END_OF_PROGRAM = 1;
1746 //===----------------------------------------------------------------------===//
1747 // Memory read/write instructions
1748 //===----------------------------------------------------------------------===//
1749 let usesCustomInserter = 1 in {
1751 class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> comp_mask, string name,
1753 : EG_CF_RAT <0x57, 0x2, 0, (outs), ins,
1754 !strconcat(name, " $rw_gpr, $index_gpr, $eop"), pattern> {
1756 // XXX: Have a separate instruction for non-indexed writes.
1762 let COMP_MASK = comp_mask;
1763 let BURST_COUNT = 0;
1769 } // End usesCustomInserter = 1
1772 def RAT_WRITE_CACHELESS_32_eg : RAT_WRITE_CACHELESS_eg <
1773 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1774 0x1, "RAT_WRITE_CACHELESS_32_eg",
1775 [(global_store i32:$rw_gpr, i32:$index_gpr)]
1779 def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg <
1780 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1781 0xf, "RAT_WRITE_CACHELESS_128",
1782 [(global_store v4i32:$rw_gpr, i32:$index_gpr)]
1785 class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
1786 : InstR600ISA <outs, (ins MEMxi:$ptr), name#" $dst, $ptr", pattern>,
1787 VTX_WORD1_GPR, VTX_WORD0 {
1792 let FETCH_WHOLE_QUAD = 0;
1793 let BUFFER_ID = buffer_id;
1795 // XXX: We can infer this field based on the SRC_GPR. This would allow us
1796 // to store vertex addresses in any channel, not just X.
1799 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,
1800 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,
1801 // however, based on my testing if USE_CONST_FIELDS is set, then all
1802 // these fields need to be set to 0.
1803 let USE_CONST_FIELDS = 0;
1804 let NUM_FORMAT_ALL = 1;
1805 let FORMAT_COMP_ALL = 0;
1806 let SRF_MODE_ALL = 0;
1808 let Inst{31-0} = Word0;
1809 let Inst{63-32} = Word1;
1810 // LLVM can only encode 64-bit instructions, so these fields are manually
1811 // encoded in R600CodeEmitter
1814 // bits<2> ENDIAN_SWAP = 0;
1815 // bits<1> CONST_BUF_NO_STRIDE = 0;
1816 // bits<1> MEGA_FETCH = 0;
1817 // bits<1> ALT_CONST = 0;
1818 // bits<2> BUFFER_INDEX_MODE = 0;
1822 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1823 // is done in R600CodeEmitter
1825 // Inst{79-64} = OFFSET;
1826 // Inst{81-80} = ENDIAN_SWAP;
1827 // Inst{82} = CONST_BUF_NO_STRIDE;
1828 // Inst{83} = MEGA_FETCH;
1829 // Inst{84} = ALT_CONST;
1830 // Inst{86-85} = BUFFER_INDEX_MODE;
1831 // Inst{95-86} = 0; Reserved
1833 // VTX_WORD3 (Padding)
1835 // Inst{127-96} = 0;
1840 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
1841 : VTX_READ_eg <"VTX_READ_8", buffer_id, (outs R600_TReg32_X:$dst),
1844 let MEGA_FETCH_COUNT = 1;
1846 let DST_SEL_Y = 7; // Masked
1847 let DST_SEL_Z = 7; // Masked
1848 let DST_SEL_W = 7; // Masked
1849 let DATA_FORMAT = 1; // FMT_8
1852 class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
1853 : VTX_READ_eg <"VTX_READ_16", buffer_id, (outs R600_TReg32_X:$dst),
1855 let MEGA_FETCH_COUNT = 2;
1857 let DST_SEL_Y = 7; // Masked
1858 let DST_SEL_Z = 7; // Masked
1859 let DST_SEL_W = 7; // Masked
1860 let DATA_FORMAT = 5; // FMT_16
1864 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
1865 : VTX_READ_eg <"VTX_READ_32", buffer_id, (outs R600_TReg32_X:$dst),
1868 let MEGA_FETCH_COUNT = 4;
1870 let DST_SEL_Y = 7; // Masked
1871 let DST_SEL_Z = 7; // Masked
1872 let DST_SEL_W = 7; // Masked
1873 let DATA_FORMAT = 0xD; // COLOR_32
1875 // This is not really necessary, but there were some GPU hangs that appeared
1876 // to be caused by ALU instructions in the next instruction group that wrote
1877 // to the $ptr registers of the VTX_READ.
1879 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
1880 // %T2_X<def> = MOV %ZERO
1881 //Adding this constraint prevents this from happening.
1882 let Constraints = "$ptr.ptr = $dst";
1885 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
1886 : VTX_READ_eg <"VTX_READ_128", buffer_id, (outs R600_Reg128:$dst),
1889 let MEGA_FETCH_COUNT = 16;
1894 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
1896 // XXX: Need to force VTX_READ_128 instructions to write to the same register
1897 // that holds its buffer address to avoid potential hangs. We can't use
1898 // the same constraint as VTX_READ_32_eg, because the $ptr.ptr and $dst
1899 // registers are different sizes.
1902 //===----------------------------------------------------------------------===//
1903 // VTX Read from parameter memory space
1904 //===----------------------------------------------------------------------===//
1906 def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <0,
1907 [(set i32:$dst, (load_param_zexti8 ADDRVTX_READ:$ptr))]
1910 def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <0,
1911 [(set i32:$dst, (load_param_zexti16 ADDRVTX_READ:$ptr))]
1914 def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0,
1915 [(set i32:$dst, (load_param ADDRVTX_READ:$ptr))]
1918 def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <0,
1919 [(set v4i32:$dst, (load_param ADDRVTX_READ:$ptr))]
1922 //===----------------------------------------------------------------------===//
1923 // VTX Read from global memory space
1924 //===----------------------------------------------------------------------===//
1927 def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1,
1928 [(set i32:$dst, (zextloadi8_global ADDRVTX_READ:$ptr))]
1932 def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1,
1933 [(set i32:$dst, (global_load ADDRVTX_READ:$ptr))]
1937 def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
1938 [(set v4i32:$dst, (global_load ADDRVTX_READ:$ptr))]
1941 //===----------------------------------------------------------------------===//
1943 // XXX: We are currently storing all constants in the global address space.
1944 //===----------------------------------------------------------------------===//
1946 def CONSTANT_LOAD_eg : VTX_READ_32_eg <1,
1947 [(set i32:$dst, (constant_load ADDRVTX_READ:$ptr))]
1952 //===----------------------------------------------------------------------===//
1953 // Regist loads and stores - for indirect addressing
1954 //===----------------------------------------------------------------------===//
1956 defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>;
1958 let Predicates = [isCayman] in {
1960 let isVector = 1 in {
1962 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
1964 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
1965 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
1966 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
1967 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
1968 def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>;
1969 def EXP_IEEE_cm : EXP_IEEE_Common<0x81>;
1970 def LOG_IEEE_cm : LOG_IEEE_Common<0x83>;
1971 def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>;
1972 def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>;
1973 def SIN_cm : SIN_Common<0x8D>;
1974 def COS_cm : COS_Common<0x8E>;
1975 } // End isVector = 1
1977 def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL>;
1978 def : SIN_PAT <SIN_cm>;
1979 def : COS_PAT <COS_cm>;
1981 defm DIV_cm : DIV_Common<RECIP_IEEE_cm>;
1983 // RECIP_UINT emulation for Cayman
1984 // The multiplication scales from [0,1] to the unsigned integer range
1986 (AMDGPUurecip i32:$src0),
1987 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)),
1988 (MOV_IMM_I32 CONST.FP_UINT_MAX_PLUS_1)))
1991 def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> {
1997 def : Pat<(fsqrt f32:$src), (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm $src))>;
2001 //===----------------------------------------------------------------------===//
2002 // Branch Instructions
2003 //===----------------------------------------------------------------------===//
2006 def IF_PREDICATE_SET : ILFormat<(outs), (ins GPRI32:$src),
2007 "IF_PREDICATE_SET $src", []>;
2009 def PREDICATED_BREAK : ILFormat<(outs), (ins GPRI32:$src),
2010 "PREDICATED_BREAK $src", []>;
2012 //===----------------------------------------------------------------------===//
2013 // Pseudo instructions
2014 //===----------------------------------------------------------------------===//
2016 let isPseudo = 1 in {
2018 def PRED_X : InstR600 <
2019 (outs R600_Predicate_Bit:$dst),
2020 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
2022 let FlagOperandIdx = 3;
2025 let isTerminator = 1, isBranch = 1 in {
2026 def JUMP_COND : InstR600 <
2028 (ins brtarget:$target, R600_Predicate_Bit:$p),
2029 "JUMP $target ($p)",
2033 def JUMP : InstR600 <
2035 (ins brtarget:$target),
2040 let isPredicable = 1;
2044 } // End isTerminator = 1, isBranch = 1
2046 let usesCustomInserter = 1 in {
2048 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
2050 def MASK_WRITE : AMDGPUShaderInst <
2052 (ins R600_Reg32:$src),
2057 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 1
2061 (outs R600_Reg128:$dst),
2062 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
2063 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
2064 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
2065 [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2,
2066 imm:$resourceId, imm:$samplerId, imm:$textureTarget))],
2071 def TXD_SHADOW: InstR600 <
2072 (outs R600_Reg128:$dst),
2073 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
2074 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
2075 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
2076 [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2,
2077 imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))],
2082 } // End isPseudo = 1
2083 } // End usesCustomInserter = 1
2085 def CLAMP_R600 : CLAMP <R600_Reg32>;
2086 def FABS_R600 : FABS<R600_Reg32>;
2087 def FNEG_R600 : FNEG<R600_Reg32>;
2089 //===---------------------------------------------------------------------===//
2090 // Return instruction
2091 //===---------------------------------------------------------------------===//
2092 let isTerminator = 1, isReturn = 1, hasCtrlDep = 1,
2093 usesCustomInserter = 1 in {
2094 def RETURN : ILFormat<(outs), (ins variable_ops),
2095 "RETURN", [(IL_retflag)]>;
2099 //===----------------------------------------------------------------------===//
2100 // Constant Buffer Addressing Support
2101 //===----------------------------------------------------------------------===//
2103 let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
2104 def CONST_COPY : Instruction {
2105 let OutOperandList = (outs R600_Reg32:$dst);
2106 let InOperandList = (ins i32imm:$src);
2108 [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];
2109 let AsmString = "CONST_COPY";
2110 let neverHasSideEffects = 1;
2111 let isAsCheapAsAMove = 1;
2112 let Itinerary = NullALU;
2114 } // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
2116 def TEX_VTX_CONSTBUF :
2117 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "VTX_READ_eg $dst, $ptr",
2118 [(set v4i32:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$BUFFER_ID)))]>,
2119 VTX_WORD1_GPR, VTX_WORD0 {
2123 let FETCH_WHOLE_QUAD = 0;
2127 let USE_CONST_FIELDS = 0;
2128 let NUM_FORMAT_ALL = 2;
2129 let FORMAT_COMP_ALL = 1;
2130 let SRF_MODE_ALL = 1;
2131 let MEGA_FETCH_COUNT = 16;
2136 let DATA_FORMAT = 35;
2138 let Inst{31-0} = Word0;
2139 let Inst{63-32} = Word1;
2141 // LLVM can only encode 64-bit instructions, so these fields are manually
2142 // encoded in R600CodeEmitter
2145 // bits<2> ENDIAN_SWAP = 0;
2146 // bits<1> CONST_BUF_NO_STRIDE = 0;
2147 // bits<1> MEGA_FETCH = 0;
2148 // bits<1> ALT_CONST = 0;
2149 // bits<2> BUFFER_INDEX_MODE = 0;
2153 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
2154 // is done in R600CodeEmitter
2156 // Inst{79-64} = OFFSET;
2157 // Inst{81-80} = ENDIAN_SWAP;
2158 // Inst{82} = CONST_BUF_NO_STRIDE;
2159 // Inst{83} = MEGA_FETCH;
2160 // Inst{84} = ALT_CONST;
2161 // Inst{86-85} = BUFFER_INDEX_MODE;
2162 // Inst{95-86} = 0; Reserved
2164 // VTX_WORD3 (Padding)
2166 // Inst{127-96} = 0;
2171 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr",
2172 [(set v4f32:$dst, (int_R600_load_texbuf ADDRGA_VAR_OFFSET:$ptr, imm:$BUFFER_ID))]>,
2173 VTX_WORD1_GPR, VTX_WORD0 {
2177 let FETCH_WHOLE_QUAD = 0;
2181 let USE_CONST_FIELDS = 1;
2182 let NUM_FORMAT_ALL = 0;
2183 let FORMAT_COMP_ALL = 0;
2184 let SRF_MODE_ALL = 1;
2185 let MEGA_FETCH_COUNT = 16;
2190 let DATA_FORMAT = 0;
2192 let Inst{31-0} = Word0;
2193 let Inst{63-32} = Word1;
2195 // LLVM can only encode 64-bit instructions, so these fields are manually
2196 // encoded in R600CodeEmitter
2199 // bits<2> ENDIAN_SWAP = 0;
2200 // bits<1> CONST_BUF_NO_STRIDE = 0;
2201 // bits<1> MEGA_FETCH = 0;
2202 // bits<1> ALT_CONST = 0;
2203 // bits<2> BUFFER_INDEX_MODE = 0;
2207 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
2208 // is done in R600CodeEmitter
2210 // Inst{79-64} = OFFSET;
2211 // Inst{81-80} = ENDIAN_SWAP;
2212 // Inst{82} = CONST_BUF_NO_STRIDE;
2213 // Inst{83} = MEGA_FETCH;
2214 // Inst{84} = ALT_CONST;
2215 // Inst{86-85} = BUFFER_INDEX_MODE;
2216 // Inst{95-86} = 0; Reserved
2218 // VTX_WORD3 (Padding)
2220 // Inst{127-96} = 0;
2226 //===--------------------------------------------------------------------===//
2227 // Instructions support
2228 //===--------------------------------------------------------------------===//
2229 //===---------------------------------------------------------------------===//
2230 // Custom Inserter for Branches and returns, this eventually will be a
2232 //===---------------------------------------------------------------------===//
2233 let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in {
2234 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
2235 "; Pseudo unconditional branch instruction",
2237 defm BRANCH_COND : BranchConditional<IL_brcond>;
2240 //===---------------------------------------------------------------------===//
2241 // Flow and Program control Instructions
2242 //===---------------------------------------------------------------------===//
2243 let isTerminator=1 in {
2244 def SWITCH : ILFormat< (outs), (ins GPRI32:$src),
2245 !strconcat("SWITCH", " $src"), []>;
2246 def CASE : ILFormat< (outs), (ins GPRI32:$src),
2247 !strconcat("CASE", " $src"), []>;
2248 def BREAK : ILFormat< (outs), (ins),
2250 def CONTINUE : ILFormat< (outs), (ins),
2252 def DEFAULT : ILFormat< (outs), (ins),
2254 def ELSE : ILFormat< (outs), (ins),
2256 def ENDSWITCH : ILFormat< (outs), (ins),
2258 def ENDMAIN : ILFormat< (outs), (ins),
2260 def END : ILFormat< (outs), (ins),
2262 def ENDFUNC : ILFormat< (outs), (ins),
2264 def ENDIF : ILFormat< (outs), (ins),
2266 def WHILELOOP : ILFormat< (outs), (ins),
2268 def ENDLOOP : ILFormat< (outs), (ins),
2270 def FUNC : ILFormat< (outs), (ins),
2272 def RETDYN : ILFormat< (outs), (ins),
2274 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2275 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">;
2276 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2277 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">;
2278 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2279 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">;
2280 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2281 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">;
2282 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2283 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">;
2284 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2285 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">;
2286 defm IFC : BranchInstr2<"IFC">;
2287 defm BREAKC : BranchInstr2<"BREAKC">;
2288 defm CONTINUEC : BranchInstr2<"CONTINUEC">;
2291 //===----------------------------------------------------------------------===//
2293 //===----------------------------------------------------------------------===//
2295 // CND*_INT Pattterns for f32 True / False values
2297 class CND_INT_f32 <InstR600 cnd, CondCode cc> : Pat <
2298 (selectcc i32:$src0, 0, f32:$src1, f32:$src2, cc),
2299 (cnd $src0, $src1, $src2)
2302 def : CND_INT_f32 <CNDE_INT, SETEQ>;
2303 def : CND_INT_f32 <CNDGT_INT, SETGT>;
2304 def : CND_INT_f32 <CNDGE_INT, SETGE>;
2306 //CNDGE_INT extra pattern
2308 (selectcc i32:$src0, -1, i32:$src1, i32:$src2, COND_GT),
2309 (CNDGE_INT $src0, $src1, $src2)
2315 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
2319 (int_AMDGPU_kill f32:$src0),
2320 (MASK_WRITE (KILLGT (f32 ZERO), $src0))
2325 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_LT),
2331 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_LE),
2335 // SETGT_DX10 reverse args
2337 (selectcc f32:$src0, f32:$src1, -1, 0, COND_LT),
2338 (SETGT_DX10 $src1, $src0)
2341 // SETGE_DX10 reverse args
2343 (selectcc f32:$src0, f32:$src1, -1, 0, COND_LE),
2344 (SETGE_DX10 $src1, $src0)
2347 // SETGT_INT reverse args
2349 (selectcc i32:$src0, i32:$src1, -1, 0, SETLT),
2350 (SETGT_INT $src1, $src0)
2353 // SETGE_INT reverse args
2355 (selectcc i32:$src0, i32:$src1, -1, 0, SETLE),
2356 (SETGE_INT $src1, $src0)
2359 // SETGT_UINT reverse args
2361 (selectcc i32:$src0, i32:$src1, -1, 0, SETULT),
2362 (SETGT_UINT $src1, $src0)
2365 // SETGE_UINT reverse args
2367 (selectcc i32:$src0, i32:$src1, -1, 0, SETULE),
2368 (SETGE_UINT $src1, $src0)
2371 // The next two patterns are special cases for handling 'true if ordered' and
2372 // 'true if unordered' conditionals. The assumption here is that the behavior of
2373 // SETE and SNE conforms to the Direct3D 10 rules for floating point values
2375 // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit
2376 // We assume that SETE returns false when one of the operands is NAN and
2377 // SNE returns true when on of the operands is NAN
2379 //SETE - 'true if ordered'
2381 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, SETO),
2385 //SETE_DX10 - 'true if ordered'
2387 (selectcc f32:$src0, f32:$src1, -1, 0, SETO),
2388 (SETE_DX10 $src0, $src1)
2391 //SNE - 'true if unordered'
2393 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, SETUO),
2397 //SETNE_DX10 - 'true if ordered'
2399 (selectcc f32:$src0, f32:$src1, -1, 0, SETUO),
2400 (SETNE_DX10 $src0, $src1)
2403 def : Extract_Element <f32, v4f32, 0, sub0>;
2404 def : Extract_Element <f32, v4f32, 1, sub1>;
2405 def : Extract_Element <f32, v4f32, 2, sub2>;
2406 def : Extract_Element <f32, v4f32, 3, sub3>;
2408 def : Insert_Element <f32, v4f32, 0, sub0>;
2409 def : Insert_Element <f32, v4f32, 1, sub1>;
2410 def : Insert_Element <f32, v4f32, 2, sub2>;
2411 def : Insert_Element <f32, v4f32, 3, sub3>;
2413 def : Extract_Element <i32, v4i32, 0, sub0>;
2414 def : Extract_Element <i32, v4i32, 1, sub1>;
2415 def : Extract_Element <i32, v4i32, 2, sub2>;
2416 def : Extract_Element <i32, v4i32, 3, sub3>;
2418 def : Insert_Element <i32, v4i32, 0, sub0>;
2419 def : Insert_Element <i32, v4i32, 1, sub1>;
2420 def : Insert_Element <i32, v4i32, 2, sub2>;
2421 def : Insert_Element <i32, v4i32, 3, sub3>;
2423 def : Vector4_Build <v4f32, f32>;
2424 def : Vector4_Build <v4i32, i32>;
2426 // bitconvert patterns
2428 def : BitConvert <i32, f32, R600_Reg32>;
2429 def : BitConvert <f32, i32, R600_Reg32>;
2430 def : BitConvert <v4f32, v4i32, R600_Reg128>;
2431 def : BitConvert <v4i32, v4f32, R600_Reg128>;
2433 // DWORDADDR pattern
2434 def : DwordAddrPat <i32, R600_Reg32>;
2436 } // End isR600toCayman Predicate