1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // TableGen definitions for instructions which are available on R600 family
13 //===----------------------------------------------------------------------===//
15 include "R600Intrinsics.td"
16 include "R600InstrFormats.td"
18 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
19 InstR600 <outs, ins, asm, pattern, NullALU> {
21 let Namespace = "AMDGPU";
24 def MEMxi : Operand<iPTR> {
25 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
26 let PrintMethod = "printMemOperand";
29 def MEMrr : Operand<iPTR> {
30 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
33 // Operands for non-registers
35 class InstFlag<string PM = "printOperand", int Default = 0>
36 : OperandWithDefaultOps <i32, (ops (i32 Default))> {
40 // src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers
41 def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> {
42 let PrintMethod = "printSel";
44 def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> {
45 let PrintMethod = "printBankSwizzle";
48 def LITERAL : InstFlag<"printLiteral">;
50 def WRITE : InstFlag <"printWrite", 1>;
51 def OMOD : InstFlag <"printOMOD">;
52 def REL : InstFlag <"printRel">;
53 def CLAMP : InstFlag <"printClamp">;
54 def NEG : InstFlag <"printNeg">;
55 def ABS : InstFlag <"printAbs">;
56 def UEM : InstFlag <"printUpdateExecMask">;
57 def UP : InstFlag <"printUpdatePred">;
59 // XXX: The r600g finalizer in Mesa expects last to be one in most cases.
60 // Once we start using the packetizer in this backend we should have this
62 def LAST : InstFlag<"printLast", 1>;
63 def RSel : Operand<i32> {
64 let PrintMethod = "printRSel";
66 def CT: Operand<i32> {
67 let PrintMethod = "printCT";
70 def FRAMEri : Operand<iPTR> {
71 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index);
74 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
75 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
76 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
77 def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>;
78 def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>;
81 def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
85 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
87 // Class for instructions with only one source register.
88 // If you add new ins to this instruction, make sure they are listed before
89 // $literal, because the backend currently assumes that the last operand is
90 // a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in
91 // R600Defines.h, R600InstrInfo::buildDefaultInstruction(),
92 // and R600InstrInfo::getOperandIdx().
93 class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
94 InstrItinClass itin = AnyALU> :
95 InstR600 <(outs R600_Reg32:$dst),
96 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
97 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
98 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
99 BANK_SWIZZLE:$bank_swizzle),
100 !strconcat(" ", opName,
101 "$clamp $last $dst$write$dst_rel$omod, "
102 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
103 "$pred_sel $bank_swizzle"),
107 R600ALU_Word1_OP2 <inst> {
113 let update_exec_mask = 0;
115 let HasNativeOperands = 1;
118 let DisableEncoding = "$literal";
119 let UseNamedOperandTable = 1;
121 let Inst{31-0} = Word0;
122 let Inst{63-32} = Word1;
125 class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
126 InstrItinClass itin = AnyALU> :
127 R600_1OP <inst, opName,
128 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))], itin
131 // If you add or change the operands for R600_2OP instructions, you must
132 // also update the R600Op2OperandIndex::ROI enum in R600Defines.h,
133 // R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx().
134 class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
135 InstrItinClass itin = AnyALU> :
136 InstR600 <(outs R600_Reg32:$dst),
137 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
138 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
139 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
140 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
141 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
142 BANK_SWIZZLE:$bank_swizzle),
143 !strconcat(" ", opName,
144 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
145 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
146 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
147 "$pred_sel $bank_swizzle"),
151 R600ALU_Word1_OP2 <inst> {
153 let HasNativeOperands = 1;
156 let DisableEncoding = "$literal";
157 let UseNamedOperandTable = 1;
159 let Inst{31-0} = Word0;
160 let Inst{63-32} = Word1;
163 class R600_2OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
164 InstrItinClass itin = AnyALU> :
165 R600_2OP <inst, opName,
166 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
167 R600_Reg32:$src1))], itin
170 // If you add our change the operands for R600_3OP instructions, you must
171 // also update the R600Op3OperandIndex::ROI enum in R600Defines.h,
172 // R600InstrInfo::buildDefaultInstruction(), and
173 // R600InstrInfo::getOperandIdx().
174 class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
175 InstrItinClass itin = AnyALU> :
176 InstR600 <(outs R600_Reg32:$dst),
177 (ins REL:$dst_rel, CLAMP:$clamp,
178 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
179 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
180 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,
181 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
182 BANK_SWIZZLE:$bank_swizzle),
183 !strconcat(" ", opName, "$clamp $last $dst$dst_rel, "
184 "$src0_neg$src0$src0_rel, "
185 "$src1_neg$src1$src1_rel, "
186 "$src2_neg$src2$src2_rel, "
192 R600ALU_Word1_OP3<inst>{
194 let HasNativeOperands = 1;
195 let DisableEncoding = "$literal";
197 let UseNamedOperandTable = 1;
200 let Inst{31-0} = Word0;
201 let Inst{63-32} = Word1;
204 class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern,
205 InstrItinClass itin = VecALU> :
206 InstR600 <(outs R600_Reg32:$dst),
214 } // End mayLoad = 1, mayStore = 0, hasSideEffects = 0
216 def TEX_SHADOW : PatLeaf<
218 [{uint32_t TType = (uint32_t)N->getZExtValue();
219 return (TType >= 6 && TType <= 8) || TType == 13;
223 def TEX_RECT : PatLeaf<
225 [{uint32_t TType = (uint32_t)N->getZExtValue();
230 def TEX_ARRAY : PatLeaf<
232 [{uint32_t TType = (uint32_t)N->getZExtValue();
233 return TType == 9 || TType == 10 || TType == 16;
237 def TEX_SHADOW_ARRAY : PatLeaf<
239 [{uint32_t TType = (uint32_t)N->getZExtValue();
240 return TType == 11 || TType == 12 || TType == 17;
244 def TEX_MSAA : PatLeaf<
246 [{uint32_t TType = (uint32_t)N->getZExtValue();
251 def TEX_ARRAY_MSAA : PatLeaf<
253 [{uint32_t TType = (uint32_t)N->getZExtValue();
258 class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> ratid, bits<4> mask,
259 dag outs, dag ins, string asm, list<dag> pattern> :
260 InstR600ISA <outs, ins, asm, pattern>,
261 CF_ALLOC_EXPORT_WORD0_RAT, CF_ALLOC_EXPORT_WORD1_BUF {
264 let rat_inst = ratinst;
266 // XXX: Have a separate instruction for non-indexed writes.
272 let comp_mask = mask;
275 let cf_inst = cfinst;
279 let Inst{31-0} = Word0;
280 let Inst{63-32} = Word1;
285 class VTX_READ <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
286 : InstR600ISA <outs, (ins MEMxi:$src_gpr), name, pattern>,
291 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,
292 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,
293 // however, based on my testing if USE_CONST_FIELDS is set, then all
294 // these fields need to be set to 0.
295 let USE_CONST_FIELDS = 0;
296 let NUM_FORMAT_ALL = 1;
297 let FORMAT_COMP_ALL = 0;
298 let SRF_MODE_ALL = 0;
300 let Inst{63-32} = Word1;
301 // LLVM can only encode 64-bit instructions, so these fields are manually
302 // encoded in R600CodeEmitter
305 // bits<2> ENDIAN_SWAP = 0;
306 // bits<1> CONST_BUF_NO_STRIDE = 0;
307 // bits<1> MEGA_FETCH = 0;
308 // bits<1> ALT_CONST = 0;
309 // bits<2> BUFFER_INDEX_MODE = 0;
311 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
312 // is done in R600CodeEmitter
314 // Inst{79-64} = OFFSET;
315 // Inst{81-80} = ENDIAN_SWAP;
316 // Inst{82} = CONST_BUF_NO_STRIDE;
317 // Inst{83} = MEGA_FETCH;
318 // Inst{84} = ALT_CONST;
319 // Inst{86-85} = BUFFER_INDEX_MODE;
320 // Inst{95-86} = 0; Reserved
322 // VTX_WORD3 (Padding)
329 class LoadParamFrag <PatFrag load_type> : PatFrag <
330 (ops node:$ptr), (load_type node:$ptr),
331 [{ return isConstantLoad(dyn_cast<LoadSDNode>(N), 0); }]
334 def load_param : LoadParamFrag<load>;
335 def load_param_exti8 : LoadParamFrag<az_extloadi8>;
336 def load_param_exti16 : LoadParamFrag<az_extloadi16>;
338 def isR600 : Predicate<"Subtarget->getGeneration() <= AMDGPUSubtarget::R700">;
342 "Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS">;
344 //===----------------------------------------------------------------------===//
346 //===----------------------------------------------------------------------===//
348 def INTERP_PAIR_XY : AMDGPUShaderInst <
349 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1),
350 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
351 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
354 def INTERP_PAIR_ZW : AMDGPUShaderInst <
355 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1),
356 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
357 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",
360 def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS",
361 SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>,
365 def DOT4 : SDNode<"AMDGPUISD::DOT4",
366 SDTypeProfile<1, 8, [SDTCisFP<0>, SDTCisVT<1, f32>, SDTCisVT<2, f32>,
367 SDTCisVT<3, f32>, SDTCisVT<4, f32>, SDTCisVT<5, f32>,
368 SDTCisVT<6, f32>, SDTCisVT<7, f32>, SDTCisVT<8, f32>]>,
372 def COS_HW : SDNode<"AMDGPUISD::COS_HW",
373 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>
376 def SIN_HW : SDNode<"AMDGPUISD::SIN_HW",
377 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>
380 def TEXTURE_FETCH_Type : SDTypeProfile<1, 19, [SDTCisFP<0>]>;
382 def TEXTURE_FETCH: SDNode<"AMDGPUISD::TEXTURE_FETCH", TEXTURE_FETCH_Type, []>;
384 multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> {
385 def : Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR,
386 (i32 imm:$srcx), (i32 imm:$srcy), (i32 imm:$srcz), (i32 imm:$srcw),
387 (i32 imm:$offsetx), (i32 imm:$offsety), (i32 imm:$offsetz),
388 (i32 imm:$DST_SEL_X), (i32 imm:$DST_SEL_Y), (i32 imm:$DST_SEL_Z),
389 (i32 imm:$DST_SEL_W),
390 (i32 imm:$RESOURCE_ID), (i32 imm:$SAMPLER_ID),
391 (i32 imm:$COORD_TYPE_X), (i32 imm:$COORD_TYPE_Y), (i32 imm:$COORD_TYPE_Z),
392 (i32 imm:$COORD_TYPE_W)),
393 (inst R600_Reg128:$SRC_GPR,
394 imm:$srcx, imm:$srcy, imm:$srcz, imm:$srcw,
395 imm:$offsetx, imm:$offsety, imm:$offsetz,
396 imm:$DST_SEL_X, imm:$DST_SEL_Y, imm:$DST_SEL_Z,
398 imm:$RESOURCE_ID, imm:$SAMPLER_ID,
399 imm:$COORD_TYPE_X, imm:$COORD_TYPE_Y, imm:$COORD_TYPE_Z,
403 //===----------------------------------------------------------------------===//
404 // Interpolation Instructions
405 //===----------------------------------------------------------------------===//
407 def INTERP_VEC_LOAD : AMDGPUShaderInst <
408 (outs R600_Reg128:$dst),
410 "INTERP_LOAD $src0 : $dst",
411 [(set R600_Reg128:$dst, (int_R600_interp_const imm:$src0))]>;
413 def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> {
414 let bank_swizzle = 5;
417 def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> {
418 let bank_swizzle = 5;
421 def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>;
423 //===----------------------------------------------------------------------===//
424 // Export Instructions
425 //===----------------------------------------------------------------------===//
427 def ExportType : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
429 def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType,
430 [SDNPHasChain, SDNPSideEffect]>;
433 field bits<32> Word0;
440 let Word0{12-0} = arraybase;
441 let Word0{14-13} = type;
442 let Word0{21-15} = gpr;
443 let Word0{22} = 0; // RW_REL
444 let Word0{29-23} = 0; // INDEX_GPR
445 let Word0{31-30} = elem_size;
448 class ExportSwzWord1 {
449 field bits<32> Word1;
458 let Word1{2-0} = sw_x;
459 let Word1{5-3} = sw_y;
460 let Word1{8-6} = sw_z;
461 let Word1{11-9} = sw_w;
464 class ExportBufWord1 {
465 field bits<32> Word1;
472 let Word1{11-0} = arraySize;
473 let Word1{15-12} = compMask;
476 multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
477 def : Pat<(int_R600_store_pixel_depth R600_Reg32:$reg),
479 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), $reg, sub0),
480 0, 61, 0, 7, 7, 7, cf_inst, 0)
483 def : Pat<(int_R600_store_pixel_stencil R600_Reg32:$reg),
485 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), $reg, sub0),
486 0, 61, 7, 0, 7, 7, cf_inst, 0)
489 def : Pat<(int_R600_store_dummy (i32 imm:$type)),
491 (v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0)
494 def : Pat<(int_R600_store_dummy 1),
496 (v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0)
499 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
500 (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)),
501 (ExportInst R600_Reg128:$src, imm:$type, imm:$base,
502 imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0)
507 multiclass SteamOutputExportPattern<Instruction ExportInst,
508 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> {
510 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
511 (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)),
512 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
513 4095, imm:$mask, buf0inst, 0)>;
515 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
516 (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)),
517 (ExportInst $src, 0, imm:$arraybase,
518 4095, imm:$mask, buf1inst, 0)>;
520 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
521 (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)),
522 (ExportInst $src, 0, imm:$arraybase,
523 4095, imm:$mask, buf2inst, 0)>;
525 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
526 (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)),
527 (ExportInst $src, 0, imm:$arraybase,
528 4095, imm:$mask, buf3inst, 0)>;
531 // Export Instructions should not be duplicated by TailDuplication pass
532 // (which assumes that duplicable instruction are affected by exec mask)
533 let usesCustomInserter = 1, isNotDuplicable = 1 in {
535 class ExportSwzInst : InstR600ISA<(
537 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
538 RSel:$sw_x, RSel:$sw_y, RSel:$sw_z, RSel:$sw_w, i32imm:$inst,
540 !strconcat("EXPORT", " $gpr.$sw_x$sw_y$sw_z$sw_w"),
541 []>, ExportWord0, ExportSwzWord1 {
543 let Inst{31-0} = Word0;
544 let Inst{63-32} = Word1;
548 } // End usesCustomInserter = 1
550 class ExportBufInst : InstR600ISA<(
552 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
553 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop),
554 !strconcat("EXPORT", " $gpr"),
555 []>, ExportWord0, ExportBufWord1 {
557 let Inst{31-0} = Word0;
558 let Inst{63-32} = Word1;
562 //===----------------------------------------------------------------------===//
563 // Control Flow Instructions
564 //===----------------------------------------------------------------------===//
567 def KCACHE : InstFlag<"printKCache">;
569 class ALU_CLAUSE<bits<4> inst, string OpName> : AMDGPUInst <(outs),
570 (ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1,
571 KCACHE:$KCACHE_MODE0, KCACHE:$KCACHE_MODE1,
572 i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1,
573 i32imm:$COUNT, i32imm:$Enabled),
574 !strconcat(OpName, " $COUNT, @$ADDR, "
575 "KC0[$KCACHE_MODE0], KC1[$KCACHE_MODE1]"),
576 [] >, CF_ALU_WORD0, CF_ALU_WORD1 {
581 let WHOLE_QUAD_MODE = 0;
583 let UseNamedOperandTable = 1;
585 let Inst{31-0} = Word0;
586 let Inst{63-32} = Word1;
589 class CF_WORD0_R600 {
590 field bits<32> Word0;
597 class CF_CLAUSE_R600 <bits<7> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
598 ins, AsmPrint, [] >, CF_WORD0_R600, CF_WORD1_R600 {
605 let VALID_PIXEL_MODE = 0;
607 let COUNT = CNT{2-0};
609 let COUNT_3 = CNT{3};
610 let END_OF_PROGRAM = 0;
611 let WHOLE_QUAD_MODE = 0;
613 let Inst{31-0} = Word0;
614 let Inst{63-32} = Word1;
617 class CF_CLAUSE_EG <bits<8> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
618 ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG {
623 let JUMPTABLE_SEL = 0;
625 let VALID_PIXEL_MODE = 0;
627 let END_OF_PROGRAM = 0;
629 let Inst{31-0} = Word0;
630 let Inst{63-32} = Word1;
633 def CF_ALU : ALU_CLAUSE<8, "ALU">;
634 def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">;
635 def CF_ALU_POP_AFTER : ALU_CLAUSE<10, "ALU_POP_AFTER">;
636 def CF_ALU_CONTINUE : ALU_CLAUSE<13, "ALU_CONTINUE">;
637 def CF_ALU_BREAK : ALU_CLAUSE<14, "ALU_BREAK">;
638 def CF_ALU_ELSE_AFTER : ALU_CLAUSE<15, "ALU_ELSE_AFTER">;
640 def FETCH_CLAUSE : AMDGPUInst <(outs),
641 (ins i32imm:$addr), "Fetch clause starting at $addr:", [] > {
647 def ALU_CLAUSE : AMDGPUInst <(outs),
648 (ins i32imm:$addr), "ALU clause starting at $addr:", [] > {
654 def LITERALS : AMDGPUInst <(outs),
655 (ins LITERAL:$literal1, LITERAL:$literal2), "$literal1, $literal2", [] > {
660 let Inst{31-0} = literal1;
661 let Inst{63-32} = literal2;
664 def PAD : AMDGPUInst <(outs), (ins), "PAD", [] > {
668 let Predicates = [isR600toCayman] in {
670 //===----------------------------------------------------------------------===//
671 // Common Instructions R600, R700, Evergreen, Cayman
672 //===----------------------------------------------------------------------===//
674 def ADD : R600_2OP_Helper <0x0, "ADD", fadd>;
675 // Non-IEEE MUL: 0 * anything = 0
676 def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE", int_AMDGPU_mul>;
677 def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>;
678 // TODO: Do these actually match the regular fmin/fmax behavior?
679 def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax_legacy>;
680 def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin_legacy>;
682 // For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
683 // so some of the instruction names don't match the asm string.
684 // XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
685 def SETE : R600_2OP <
687 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OEQ))]
692 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGT))]
697 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGE))]
702 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_UNE_NE))]
705 def SETE_DX10 : R600_2OP <
707 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OEQ))]
710 def SETGT_DX10 : R600_2OP <
712 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGT))]
715 def SETGE_DX10 : R600_2OP <
717 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGE))]
720 // FIXME: This should probably be COND_ONE
721 def SETNE_DX10 : R600_2OP <
723 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_UNE_NE))]
726 def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>;
727 def TRUNC : R600_1OP_Helper <0x11, "TRUNC", ftrunc>;
728 def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;
729 def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>;
730 def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>;
732 def MOV : R600_1OP <0x19, "MOV", []>;
734 let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in {
736 class MOV_IMM <ValueType vt, Operand immType> : AMDGPUInst <
737 (outs R600_Reg32:$dst),
743 } // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1
745 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
748 (MOV_IMM_I32 imm:$val)
751 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
754 (MOV_IMM_F32 fpimm:$val)
757 def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>;
758 def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>;
759 def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>;
760 def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>;
762 let hasSideEffects = 1 in {
764 def KILLGT : R600_2OP <0x2D, "KILLGT", []>;
766 } // end hasSideEffects
768 def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>;
769 def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>;
770 def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>;
771 def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>;
772 def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>;
773 def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>;
774 def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", AMDGPUsmax>;
775 def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", AMDGPUsmin>;
776 def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", AMDGPUumax>;
777 def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", AMDGPUumin>;
779 def SETE_INT : R600_2OP <
781 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETEQ))]
784 def SETGT_INT : R600_2OP <
786 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGT))]
789 def SETGE_INT : R600_2OP <
791 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))]
794 def SETNE_INT : R600_2OP <
796 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETNE))]
799 def SETGT_UINT : R600_2OP <
801 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGT))]
804 def SETGE_UINT : R600_2OP <
806 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGE))]
809 def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>;
810 def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>;
811 def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>;
812 def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>;
814 def CNDE_INT : R600_3OP <
816 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_EQ))]
819 def CNDGE_INT : R600_3OP <
821 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGE))]
824 def CNDGT_INT : R600_3OP <
826 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGT))]
829 //===----------------------------------------------------------------------===//
830 // Texture instructions
831 //===----------------------------------------------------------------------===//
833 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
835 class R600_TEX <bits<11> inst, string opName> :
836 InstR600 <(outs R600_Reg128:$DST_GPR),
837 (ins R600_Reg128:$SRC_GPR,
838 RSel:$srcx, RSel:$srcy, RSel:$srcz, RSel:$srcw,
839 i32imm:$offsetx, i32imm:$offsety, i32imm:$offsetz,
840 RSel:$DST_SEL_X, RSel:$DST_SEL_Y, RSel:$DST_SEL_Z, RSel:$DST_SEL_W,
841 i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID,
842 CT:$COORD_TYPE_X, CT:$COORD_TYPE_Y, CT:$COORD_TYPE_Z,
845 " $DST_GPR.$DST_SEL_X$DST_SEL_Y$DST_SEL_Z$DST_SEL_W, "
846 "$SRC_GPR.$srcx$srcy$srcz$srcw "
847 "RID:$RESOURCE_ID SID:$SAMPLER_ID "
848 "CT:$COORD_TYPE_X$COORD_TYPE_Y$COORD_TYPE_Z$COORD_TYPE_W"),
850 NullALU>, TEX_WORD0, TEX_WORD1, TEX_WORD2 {
851 let Inst{31-0} = Word0;
852 let Inst{63-32} = Word1;
854 let TEX_INST = inst{4-0};
860 let FETCH_WHOLE_QUAD = 0;
862 let SAMPLER_INDEX_MODE = 0;
863 let RESOURCE_INDEX_MODE = 0;
868 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
872 def TEX_SAMPLE : R600_TEX <0x10, "TEX_SAMPLE">;
873 def TEX_SAMPLE_C : R600_TEX <0x18, "TEX_SAMPLE_C">;
874 def TEX_SAMPLE_L : R600_TEX <0x11, "TEX_SAMPLE_L">;
875 def TEX_SAMPLE_C_L : R600_TEX <0x19, "TEX_SAMPLE_C_L">;
876 def TEX_SAMPLE_LB : R600_TEX <0x12, "TEX_SAMPLE_LB">;
877 def TEX_SAMPLE_C_LB : R600_TEX <0x1A, "TEX_SAMPLE_C_LB">;
878 def TEX_LD : R600_TEX <0x03, "TEX_LD">;
879 def TEX_LDPTR : R600_TEX <0x03, "TEX_LDPTR"> {
882 def TEX_GET_TEXTURE_RESINFO : R600_TEX <0x04, "TEX_GET_TEXTURE_RESINFO">;
883 def TEX_GET_GRADIENTS_H : R600_TEX <0x07, "TEX_GET_GRADIENTS_H">;
884 def TEX_GET_GRADIENTS_V : R600_TEX <0x08, "TEX_GET_GRADIENTS_V">;
885 def TEX_SET_GRADIENTS_H : R600_TEX <0x0B, "TEX_SET_GRADIENTS_H">;
886 def TEX_SET_GRADIENTS_V : R600_TEX <0x0C, "TEX_SET_GRADIENTS_V">;
887 def TEX_SAMPLE_G : R600_TEX <0x14, "TEX_SAMPLE_G">;
888 def TEX_SAMPLE_C_G : R600_TEX <0x1C, "TEX_SAMPLE_C_G">;
890 defm : TexPattern<0, TEX_SAMPLE>;
891 defm : TexPattern<1, TEX_SAMPLE_C>;
892 defm : TexPattern<2, TEX_SAMPLE_L>;
893 defm : TexPattern<3, TEX_SAMPLE_C_L>;
894 defm : TexPattern<4, TEX_SAMPLE_LB>;
895 defm : TexPattern<5, TEX_SAMPLE_C_LB>;
896 defm : TexPattern<6, TEX_LD, v4i32>;
897 defm : TexPattern<7, TEX_GET_TEXTURE_RESINFO, v4i32>;
898 defm : TexPattern<8, TEX_GET_GRADIENTS_H>;
899 defm : TexPattern<9, TEX_GET_GRADIENTS_V>;
900 defm : TexPattern<10, TEX_LDPTR, v4i32>;
902 //===----------------------------------------------------------------------===//
903 // Helper classes for common instructions
904 //===----------------------------------------------------------------------===//
906 class MUL_LIT_Common <bits<5> inst> : R600_3OP <
911 class MULADD_Common <bits<5> inst> : R600_3OP <
916 class MULADD_IEEE_Common <bits<5> inst> : R600_3OP <
918 [(set f32:$dst, (fadd (fmul f32:$src0, f32:$src1), f32:$src2))]
921 class FMA_Common <bits<5> inst> : R600_3OP <
923 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))], VecALU
926 class CNDE_Common <bits<5> inst> : R600_3OP <
928 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OEQ))]
931 class CNDGT_Common <bits<5> inst> : R600_3OP <
933 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGT))]
935 let Itinerary = VecALU;
938 class CNDGE_Common <bits<5> inst> : R600_3OP <
940 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGE))]
942 let Itinerary = VecALU;
946 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
947 class R600_VEC2OP<list<dag> pattern> : InstR600 <(outs R600_Reg32:$dst), (ins
949 UEM:$update_exec_mask_X, UP:$update_pred_X, WRITE:$write_X,
950 OMOD:$omod_X, REL:$dst_rel_X, CLAMP:$clamp_X,
951 R600_TReg32_X:$src0_X, NEG:$src0_neg_X, REL:$src0_rel_X, ABS:$src0_abs_X, SEL:$src0_sel_X,
952 R600_TReg32_X:$src1_X, NEG:$src1_neg_X, REL:$src1_rel_X, ABS:$src1_abs_X, SEL:$src1_sel_X,
953 R600_Pred:$pred_sel_X,
955 UEM:$update_exec_mask_Y, UP:$update_pred_Y, WRITE:$write_Y,
956 OMOD:$omod_Y, REL:$dst_rel_Y, CLAMP:$clamp_Y,
957 R600_TReg32_Y:$src0_Y, NEG:$src0_neg_Y, REL:$src0_rel_Y, ABS:$src0_abs_Y, SEL:$src0_sel_Y,
958 R600_TReg32_Y:$src1_Y, NEG:$src1_neg_Y, REL:$src1_rel_Y, ABS:$src1_abs_Y, SEL:$src1_sel_Y,
959 R600_Pred:$pred_sel_Y,
961 UEM:$update_exec_mask_Z, UP:$update_pred_Z, WRITE:$write_Z,
962 OMOD:$omod_Z, REL:$dst_rel_Z, CLAMP:$clamp_Z,
963 R600_TReg32_Z:$src0_Z, NEG:$src0_neg_Z, REL:$src0_rel_Z, ABS:$src0_abs_Z, SEL:$src0_sel_Z,
964 R600_TReg32_Z:$src1_Z, NEG:$src1_neg_Z, REL:$src1_rel_Z, ABS:$src1_abs_Z, SEL:$src1_sel_Z,
965 R600_Pred:$pred_sel_Z,
967 UEM:$update_exec_mask_W, UP:$update_pred_W, WRITE:$write_W,
968 OMOD:$omod_W, REL:$dst_rel_W, CLAMP:$clamp_W,
969 R600_TReg32_W:$src0_W, NEG:$src0_neg_W, REL:$src0_rel_W, ABS:$src0_abs_W, SEL:$src0_sel_W,
970 R600_TReg32_W:$src1_W, NEG:$src1_neg_W, REL:$src1_rel_W, ABS:$src1_abs_W, SEL:$src1_sel_W,
971 R600_Pred:$pred_sel_W,
972 LITERAL:$literal0, LITERAL:$literal1),
977 let UseNamedOperandTable = 1;
982 def DOT_4 : R600_VEC2OP<[(set R600_Reg32:$dst, (DOT4
983 R600_TReg32_X:$src0_X, R600_TReg32_X:$src1_X,
984 R600_TReg32_Y:$src0_Y, R600_TReg32_Y:$src1_Y,
985 R600_TReg32_Z:$src0_Z, R600_TReg32_Z:$src1_Z,
986 R600_TReg32_W:$src0_W, R600_TReg32_W:$src1_W))]>;
989 class DOT4_Common <bits<11> inst> : R600_2OP <inst, "DOT4", []>;
992 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
993 multiclass CUBE_Common <bits<11> inst> {
995 def _pseudo : InstR600 <
996 (outs R600_Reg128:$dst),
997 (ins R600_Reg128:$src0),
999 [(set v4f32:$dst, (int_AMDGPU_cube v4f32:$src0))],
1003 let UseNamedOperandTable = 1;
1006 def _real : R600_2OP <inst, "CUBE", []>;
1008 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
1010 class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1011 inst, "EXP_IEEE", fexp2
1013 let Itinerary = TransALU;
1016 class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper <
1017 inst, "FLT_TO_INT", fp_to_sint
1019 let Itinerary = TransALU;
1022 class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1023 inst, "INT_TO_FLT", sint_to_fp
1025 let Itinerary = TransALU;
1028 class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1029 inst, "FLT_TO_UINT", fp_to_uint
1031 let Itinerary = TransALU;
1034 class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1035 inst, "UINT_TO_FLT", uint_to_fp
1037 let Itinerary = TransALU;
1040 class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <
1041 inst, "LOG_CLAMPED", []
1044 class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1045 inst, "LOG_IEEE", flog2
1047 let Itinerary = TransALU;
1050 class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>;
1051 class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>;
1052 class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>;
1053 class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper <
1054 inst, "MULHI_INT", mulhs
1056 let Itinerary = TransALU;
1058 class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper <
1059 inst, "MULHI", mulhu
1061 let Itinerary = TransALU;
1063 class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper <
1064 inst, "MULLO_INT", mul
1066 let Itinerary = TransALU;
1068 class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []> {
1069 let Itinerary = TransALU;
1072 class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <
1073 inst, "RECIP_CLAMPED", []
1075 let Itinerary = TransALU;
1078 class RECIP_IEEE_Common <bits<11> inst> : R600_1OP <
1079 inst, "RECIP_IEEE", [(set f32:$dst, (AMDGPUrcp f32:$src0))]
1081 let Itinerary = TransALU;
1084 class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1085 inst, "RECIP_UINT", AMDGPUurecip
1087 let Itinerary = TransALU;
1090 // Clamped to maximum.
1091 class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper <
1092 inst, "RECIPSQRT_CLAMPED", AMDGPUrsq_clamped
1094 let Itinerary = TransALU;
1097 class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1098 inst, "RECIPSQRT_IEEE", AMDGPUrsq_legacy
1100 let Itinerary = TransALU;
1103 // TODO: There is also RECIPSQRT_FF which clamps to zero.
1105 class SIN_Common <bits<11> inst> : R600_1OP <
1106 inst, "SIN", [(set f32:$dst, (SIN_HW f32:$src0))]>{
1108 let Itinerary = TransALU;
1111 class COS_Common <bits<11> inst> : R600_1OP <
1112 inst, "COS", [(set f32:$dst, (COS_HW f32:$src0))]> {
1114 let Itinerary = TransALU;
1117 def CLAMP_R600 : CLAMP <R600_Reg32>;
1118 def FABS_R600 : FABS<R600_Reg32>;
1119 def FNEG_R600 : FNEG<R600_Reg32>;
1121 //===----------------------------------------------------------------------===//
1122 // Helper patterns for complex intrinsics
1123 //===----------------------------------------------------------------------===//
1125 // FIXME: Should be predicated on unsafe fp math.
1126 multiclass DIV_Common <InstR600 recip_ieee> {
1128 (int_AMDGPU_div f32:$src0, f32:$src1),
1129 (MUL_IEEE $src0, (recip_ieee $src1))
1133 (fdiv f32:$src0, f32:$src1),
1134 (MUL_IEEE $src0, (recip_ieee $src1))
1137 def : RcpPat<recip_ieee, f32>;
1140 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee>
1142 (int_TGSI_lit_z f32:$src_x, f32:$src_y, f32:$src_w),
1143 (exp_ieee (mul_lit (log_clamped (MAX $src_y, (f32 ZERO))), $src_w, $src_x))
1146 //===----------------------------------------------------------------------===//
1147 // R600 / R700 Instructions
1148 //===----------------------------------------------------------------------===//
1150 let Predicates = [isR600] in {
1152 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
1153 def MULADD_r600 : MULADD_Common<0x10>;
1154 def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>;
1155 def CNDE_r600 : CNDE_Common<0x18>;
1156 def CNDGT_r600 : CNDGT_Common<0x19>;
1157 def CNDGE_r600 : CNDGE_Common<0x1A>;
1158 def DOT4_r600 : DOT4_Common<0x50>;
1159 defm CUBE_r600 : CUBE_Common<0x52>;
1160 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
1161 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
1162 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
1163 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
1164 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
1165 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
1166 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
1167 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
1168 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
1169 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
1170 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
1171 def SIN_r600 : SIN_Common<0x6E>;
1172 def COS_r600 : COS_Common<0x6F>;
1173 def ASHR_r600 : ASHR_Common<0x70>;
1174 def LSHR_r600 : LSHR_Common<0x71>;
1175 def LSHL_r600 : LSHL_Common<0x72>;
1176 def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
1177 def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
1178 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
1179 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
1180 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
1182 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
1183 def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL>;
1184 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
1186 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>;
1187 defm : RsqPat<RECIPSQRT_IEEE_r600, f32>;
1189 def R600_ExportSwz : ExportSwzInst {
1190 let Word1{20-17} = 0; // BURST_COUNT
1191 let Word1{21} = eop;
1192 let Word1{22} = 0; // VALID_PIXEL_MODE
1193 let Word1{30-23} = inst;
1194 let Word1{31} = 1; // BARRIER
1196 defm : ExportPattern<R600_ExportSwz, 39>;
1198 def R600_ExportBuf : ExportBufInst {
1199 let Word1{20-17} = 0; // BURST_COUNT
1200 let Word1{21} = eop;
1201 let Word1{22} = 0; // VALID_PIXEL_MODE
1202 let Word1{30-23} = inst;
1203 let Word1{31} = 1; // BARRIER
1205 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>;
1207 def CF_TC_R600 : CF_CLAUSE_R600<1, (ins i32imm:$ADDR, i32imm:$CNT),
1208 "TEX $CNT @$ADDR"> {
1211 def CF_VC_R600 : CF_CLAUSE_R600<2, (ins i32imm:$ADDR, i32imm:$CNT),
1212 "VTX $CNT @$ADDR"> {
1215 def WHILE_LOOP_R600 : CF_CLAUSE_R600<6, (ins i32imm:$ADDR),
1216 "LOOP_START_DX10 @$ADDR"> {
1220 def END_LOOP_R600 : CF_CLAUSE_R600<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1224 def LOOP_BREAK_R600 : CF_CLAUSE_R600<9, (ins i32imm:$ADDR),
1225 "LOOP_BREAK @$ADDR"> {
1229 def CF_CONTINUE_R600 : CF_CLAUSE_R600<8, (ins i32imm:$ADDR),
1230 "CONTINUE @$ADDR"> {
1234 def CF_JUMP_R600 : CF_CLAUSE_R600<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1235 "JUMP @$ADDR POP:$POP_COUNT"> {
1238 def CF_PUSH_ELSE_R600 : CF_CLAUSE_R600<12, (ins i32imm:$ADDR),
1239 "PUSH_ELSE @$ADDR"> {
1242 def CF_ELSE_R600 : CF_CLAUSE_R600<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1243 "ELSE @$ADDR POP:$POP_COUNT"> {
1246 def CF_CALL_FS_R600 : CF_CLAUSE_R600<19, (ins), "CALL_FS"> {
1251 def POP_R600 : CF_CLAUSE_R600<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1252 "POP @$ADDR POP:$POP_COUNT"> {
1255 def CF_END_R600 : CF_CLAUSE_R600<0, (ins), "CF_END"> {
1259 let END_OF_PROGRAM = 1;
1265 //===----------------------------------------------------------------------===//
1266 // Regist loads and stores - for indirect addressing
1267 //===----------------------------------------------------------------------===//
1269 defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>;
1272 //===----------------------------------------------------------------------===//
1273 // Pseudo instructions
1274 //===----------------------------------------------------------------------===//
1276 let isPseudo = 1 in {
1278 def PRED_X : InstR600 <
1279 (outs R600_Predicate_Bit:$dst),
1280 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
1282 let FlagOperandIdx = 3;
1285 let isTerminator = 1, isBranch = 1 in {
1286 def JUMP_COND : InstR600 <
1288 (ins brtarget:$target, R600_Predicate_Bit:$p),
1289 "JUMP $target ($p)",
1293 def JUMP : InstR600 <
1295 (ins brtarget:$target),
1300 let isPredicable = 1;
1304 } // End isTerminator = 1, isBranch = 1
1306 let usesCustomInserter = 1 in {
1308 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
1310 def MASK_WRITE : AMDGPUShaderInst <
1312 (ins R600_Reg32:$src),
1317 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 1
1321 (outs R600_Reg128:$dst),
1322 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
1323 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
1324 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
1325 [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2,
1326 imm:$resourceId, imm:$samplerId, imm:$textureTarget))],
1331 def TXD_SHADOW: InstR600 <
1332 (outs R600_Reg128:$dst),
1333 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
1334 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
1335 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
1336 [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2,
1337 imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))],
1342 } // End isPseudo = 1
1343 } // End usesCustomInserter = 1
1346 //===----------------------------------------------------------------------===//
1347 // Constant Buffer Addressing Support
1348 //===----------------------------------------------------------------------===//
1350 let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
1351 def CONST_COPY : Instruction {
1352 let OutOperandList = (outs R600_Reg32:$dst);
1353 let InOperandList = (ins i32imm:$src);
1355 [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];
1356 let AsmString = "CONST_COPY";
1357 let hasSideEffects = 0;
1358 let isAsCheapAsAMove = 1;
1359 let Itinerary = NullALU;
1361 } // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
1363 def TEX_VTX_CONSTBUF :
1364 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "VTX_READ_eg $dst, $ptr",
1365 [(set v4i32:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$BUFFER_ID)))]>,
1366 VTX_WORD1_GPR, VTX_WORD0_eg {
1370 let FETCH_WHOLE_QUAD = 0;
1374 let USE_CONST_FIELDS = 0;
1375 let NUM_FORMAT_ALL = 2;
1376 let FORMAT_COMP_ALL = 1;
1377 let SRF_MODE_ALL = 1;
1378 let MEGA_FETCH_COUNT = 16;
1383 let DATA_FORMAT = 35;
1385 let Inst{31-0} = Word0;
1386 let Inst{63-32} = Word1;
1388 // LLVM can only encode 64-bit instructions, so these fields are manually
1389 // encoded in R600CodeEmitter
1392 // bits<2> ENDIAN_SWAP = 0;
1393 // bits<1> CONST_BUF_NO_STRIDE = 0;
1394 // bits<1> MEGA_FETCH = 0;
1395 // bits<1> ALT_CONST = 0;
1396 // bits<2> BUFFER_INDEX_MODE = 0;
1400 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1401 // is done in R600CodeEmitter
1403 // Inst{79-64} = OFFSET;
1404 // Inst{81-80} = ENDIAN_SWAP;
1405 // Inst{82} = CONST_BUF_NO_STRIDE;
1406 // Inst{83} = MEGA_FETCH;
1407 // Inst{84} = ALT_CONST;
1408 // Inst{86-85} = BUFFER_INDEX_MODE;
1409 // Inst{95-86} = 0; Reserved
1411 // VTX_WORD3 (Padding)
1413 // Inst{127-96} = 0;
1418 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr",
1419 [(set v4f32:$dst, (int_R600_load_texbuf ADDRGA_VAR_OFFSET:$ptr, imm:$BUFFER_ID))]>,
1420 VTX_WORD1_GPR, VTX_WORD0_eg {
1424 let FETCH_WHOLE_QUAD = 0;
1428 let USE_CONST_FIELDS = 1;
1429 let NUM_FORMAT_ALL = 0;
1430 let FORMAT_COMP_ALL = 0;
1431 let SRF_MODE_ALL = 1;
1432 let MEGA_FETCH_COUNT = 16;
1437 let DATA_FORMAT = 0;
1439 let Inst{31-0} = Word0;
1440 let Inst{63-32} = Word1;
1442 // LLVM can only encode 64-bit instructions, so these fields are manually
1443 // encoded in R600CodeEmitter
1446 // bits<2> ENDIAN_SWAP = 0;
1447 // bits<1> CONST_BUF_NO_STRIDE = 0;
1448 // bits<1> MEGA_FETCH = 0;
1449 // bits<1> ALT_CONST = 0;
1450 // bits<2> BUFFER_INDEX_MODE = 0;
1454 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1455 // is done in R600CodeEmitter
1457 // Inst{79-64} = OFFSET;
1458 // Inst{81-80} = ENDIAN_SWAP;
1459 // Inst{82} = CONST_BUF_NO_STRIDE;
1460 // Inst{83} = MEGA_FETCH;
1461 // Inst{84} = ALT_CONST;
1462 // Inst{86-85} = BUFFER_INDEX_MODE;
1463 // Inst{95-86} = 0; Reserved
1465 // VTX_WORD3 (Padding)
1467 // Inst{127-96} = 0;
1471 //===---------------------------------------------------------------------===//
1472 // Flow and Program control Instructions
1473 //===---------------------------------------------------------------------===//
1474 class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern>
1477 let Namespace = "AMDGPU";
1478 dag OutOperandList = outs;
1479 dag InOperandList = ins;
1480 let Pattern = pattern;
1481 let AsmString = !strconcat(asmstr, "\n");
1483 let Itinerary = NullALU;
1484 bit hasIEEEFlag = 0;
1485 bit hasZeroOpFlag = 0;
1488 let hasSideEffects = 0;
1489 let isCodeGenOnly = 1;
1492 multiclass BranchConditional<SDNode Op, RegisterClass rci, RegisterClass rcf> {
1493 def _i32 : ILFormat<(outs),
1494 (ins brtarget:$target, rci:$src0),
1495 "; i32 Pseudo branch instruction",
1496 [(Op bb:$target, (i32 rci:$src0))]>;
1497 def _f32 : ILFormat<(outs),
1498 (ins brtarget:$target, rcf:$src0),
1499 "; f32 Pseudo branch instruction",
1500 [(Op bb:$target, (f32 rcf:$src0))]>;
1503 // Only scalar types should generate flow control
1504 multiclass BranchInstr<string name> {
1505 def _i32 : ILFormat<(outs), (ins R600_Reg32:$src),
1506 !strconcat(name, " $src"), []>;
1507 def _f32 : ILFormat<(outs), (ins R600_Reg32:$src),
1508 !strconcat(name, " $src"), []>;
1510 // Only scalar types should generate flow control
1511 multiclass BranchInstr2<string name> {
1512 def _i32 : ILFormat<(outs), (ins R600_Reg32:$src0, R600_Reg32:$src1),
1513 !strconcat(name, " $src0, $src1"), []>;
1514 def _f32 : ILFormat<(outs), (ins R600_Reg32:$src0, R600_Reg32:$src1),
1515 !strconcat(name, " $src0, $src1"), []>;
1518 //===---------------------------------------------------------------------===//
1519 // Custom Inserter for Branches and returns, this eventually will be a
1521 //===---------------------------------------------------------------------===//
1522 let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in {
1523 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
1524 "; Pseudo unconditional branch instruction",
1526 defm BRANCH_COND : BranchConditional<IL_brcond, R600_Reg32, R600_Reg32>;
1529 //===---------------------------------------------------------------------===//
1530 // Return instruction
1531 //===---------------------------------------------------------------------===//
1532 let isTerminator = 1, isReturn = 1, hasCtrlDep = 1,
1533 usesCustomInserter = 1 in {
1534 def RETURN : ILFormat<(outs), (ins variable_ops),
1535 "RETURN", [(IL_retflag)]>;
1538 //===----------------------------------------------------------------------===//
1539 // Branch Instructions
1540 //===----------------------------------------------------------------------===//
1542 def IF_PREDICATE_SET : ILFormat<(outs), (ins R600_Reg32:$src),
1543 "IF_PREDICATE_SET $src", []>;
1545 let isTerminator=1 in {
1546 def BREAK : ILFormat< (outs), (ins),
1548 def CONTINUE : ILFormat< (outs), (ins),
1550 def DEFAULT : ILFormat< (outs), (ins),
1552 def ELSE : ILFormat< (outs), (ins),
1554 def ENDSWITCH : ILFormat< (outs), (ins),
1556 def ENDMAIN : ILFormat< (outs), (ins),
1558 def END : ILFormat< (outs), (ins),
1560 def ENDFUNC : ILFormat< (outs), (ins),
1562 def ENDIF : ILFormat< (outs), (ins),
1564 def WHILELOOP : ILFormat< (outs), (ins),
1566 def ENDLOOP : ILFormat< (outs), (ins),
1568 def FUNC : ILFormat< (outs), (ins),
1570 def RETDYN : ILFormat< (outs), (ins),
1572 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1573 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">;
1574 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1575 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">;
1576 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1577 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">;
1578 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1579 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">;
1580 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1581 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">;
1582 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1583 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">;
1584 defm IFC : BranchInstr2<"IFC">;
1585 defm BREAKC : BranchInstr2<"BREAKC">;
1586 defm CONTINUEC : BranchInstr2<"CONTINUEC">;
1589 //===----------------------------------------------------------------------===//
1590 // Indirect addressing pseudo instructions
1591 //===----------------------------------------------------------------------===//
1593 let isPseudo = 1 in {
1595 class ExtractVertical <RegisterClass vec_rc> : InstR600 <
1596 (outs R600_Reg32:$dst),
1597 (ins vec_rc:$vec, R600_Reg32:$index), "",
1602 let Constraints = "$dst = $vec" in {
1604 class InsertVertical <RegisterClass vec_rc> : InstR600 <
1606 (ins vec_rc:$vec, R600_Reg32:$value, R600_Reg32:$index), "",
1611 } // End Constraints = "$dst = $vec"
1613 } // End isPseudo = 1
1615 def R600_EXTRACT_ELT_V2 : ExtractVertical <R600_Reg64Vertical>;
1616 def R600_EXTRACT_ELT_V4 : ExtractVertical <R600_Reg128Vertical>;
1618 def R600_INSERT_ELT_V2 : InsertVertical <R600_Reg64Vertical>;
1619 def R600_INSERT_ELT_V4 : InsertVertical <R600_Reg128Vertical>;
1621 class ExtractVerticalPat <Instruction inst, ValueType vec_ty,
1622 ValueType scalar_ty> : Pat <
1623 (scalar_ty (extractelt vec_ty:$vec, i32:$index)),
1627 def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2i32, i32>;
1628 def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2f32, f32>;
1629 def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4i32, i32>;
1630 def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4f32, f32>;
1632 class InsertVerticalPat <Instruction inst, ValueType vec_ty,
1633 ValueType scalar_ty> : Pat <
1634 (vec_ty (insertelt vec_ty:$vec, scalar_ty:$value, i32:$index)),
1635 (inst $vec, $value, $index)
1638 def : InsertVerticalPat <R600_INSERT_ELT_V2, v2i32, i32>;
1639 def : InsertVerticalPat <R600_INSERT_ELT_V2, v2f32, f32>;
1640 def : InsertVerticalPat <R600_INSERT_ELT_V4, v4i32, i32>;
1641 def : InsertVerticalPat <R600_INSERT_ELT_V4, v4f32, f32>;
1643 //===----------------------------------------------------------------------===//
1645 //===----------------------------------------------------------------------===//
1647 // CND*_INT Pattterns for f32 True / False values
1649 class CND_INT_f32 <InstR600 cnd, CondCode cc> : Pat <
1650 (selectcc i32:$src0, 0, f32:$src1, f32:$src2, cc),
1651 (cnd $src0, $src1, $src2)
1654 def : CND_INT_f32 <CNDE_INT, SETEQ>;
1655 def : CND_INT_f32 <CNDGT_INT, SETGT>;
1656 def : CND_INT_f32 <CNDGE_INT, SETGE>;
1658 //CNDGE_INT extra pattern
1660 (selectcc i32:$src0, -1, i32:$src1, i32:$src2, COND_SGT),
1661 (CNDGE_INT $src0, $src1, $src2)
1667 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
1671 (int_AMDGPU_kill f32:$src0),
1672 (MASK_WRITE (KILLGT (f32 ZERO), $src0))
1675 def : Extract_Element <f32, v4f32, 0, sub0>;
1676 def : Extract_Element <f32, v4f32, 1, sub1>;
1677 def : Extract_Element <f32, v4f32, 2, sub2>;
1678 def : Extract_Element <f32, v4f32, 3, sub3>;
1680 def : Insert_Element <f32, v4f32, 0, sub0>;
1681 def : Insert_Element <f32, v4f32, 1, sub1>;
1682 def : Insert_Element <f32, v4f32, 2, sub2>;
1683 def : Insert_Element <f32, v4f32, 3, sub3>;
1685 def : Extract_Element <i32, v4i32, 0, sub0>;
1686 def : Extract_Element <i32, v4i32, 1, sub1>;
1687 def : Extract_Element <i32, v4i32, 2, sub2>;
1688 def : Extract_Element <i32, v4i32, 3, sub3>;
1690 def : Insert_Element <i32, v4i32, 0, sub0>;
1691 def : Insert_Element <i32, v4i32, 1, sub1>;
1692 def : Insert_Element <i32, v4i32, 2, sub2>;
1693 def : Insert_Element <i32, v4i32, 3, sub3>;
1695 def : Extract_Element <f32, v2f32, 0, sub0>;
1696 def : Extract_Element <f32, v2f32, 1, sub1>;
1698 def : Insert_Element <f32, v2f32, 0, sub0>;
1699 def : Insert_Element <f32, v2f32, 1, sub1>;
1701 def : Extract_Element <i32, v2i32, 0, sub0>;
1702 def : Extract_Element <i32, v2i32, 1, sub1>;
1704 def : Insert_Element <i32, v2i32, 0, sub0>;
1705 def : Insert_Element <i32, v2i32, 1, sub1>;
1707 // bitconvert patterns
1709 def : BitConvert <i32, f32, R600_Reg32>;
1710 def : BitConvert <f32, i32, R600_Reg32>;
1711 def : BitConvert <v2f32, v2i32, R600_Reg64>;
1712 def : BitConvert <v2i32, v2f32, R600_Reg64>;
1713 def : BitConvert <v4f32, v4i32, R600_Reg128>;
1714 def : BitConvert <v4i32, v4f32, R600_Reg128>;
1716 // DWORDADDR pattern
1717 def : DwordAddrPat <i32, R600_Reg32>;
1719 } // End isR600toCayman Predicate
1721 let Predicates = [isR600] in {
1722 // Intrinsic patterns
1723 defm : Expand24IBitOps<MULLO_INT_r600, ADD_INT>;
1724 defm : Expand24UBitOps<MULLO_UINT_r600, ADD_INT>;
1727 def getLDSNoRetOp : InstrMapping {
1728 let FilterClass = "R600_LDS_1A1D";
1729 let RowFields = ["BaseOp"];
1730 let ColFields = ["DisableEncoding"];
1731 let KeyCol = ["$dst"];
1732 let ValueCols = [[""""]];