1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // R600 Tablegen instruction definitions
12 //===----------------------------------------------------------------------===//
14 include "R600Intrinsics.td"
16 class InstR600 <bits<11> inst, dag outs, dag ins, string asm, list<dag> pattern,
18 : AMDGPUInst <outs, ins, asm, pattern> {
24 bits<2> FlagOperandIdx = 0;
27 bit HasNativeOperands = 0;
29 bits<11> op_code = inst;
31 let Namespace = "AMDGPU";
32 let OutOperandList = outs;
33 let InOperandList = ins;
35 let Pattern = pattern;
38 let TSFlags{4} = Trig;
41 // Vector instructions are instructions that must fill all slots in an
43 let TSFlags{6} = isVector;
44 let TSFlags{8-7} = FlagOperandIdx;
45 let TSFlags{9} = HasNativeOperands;
46 let TSFlags{10} = Op1;
47 let TSFlags{11} = Op2;
50 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
51 AMDGPUInst <outs, ins, asm, pattern> {
54 let Namespace = "AMDGPU";
57 def MEMxi : Operand<iPTR> {
58 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
59 let PrintMethod = "printMemOperand";
62 def MEMrr : Operand<iPTR> {
63 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
66 // Operands for non-registers
68 class InstFlag<string PM = "printOperand", int Default = 0>
69 : OperandWithDefaultOps <i32, (ops (i32 Default))> {
73 // src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers
74 def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> {
75 let PrintMethod = "printSel";
78 def LITERAL : InstFlag<"printLiteral">;
80 def WRITE : InstFlag <"printWrite", 1>;
81 def OMOD : InstFlag <"printOMOD">;
82 def REL : InstFlag <"printRel">;
83 def CLAMP : InstFlag <"printClamp">;
84 def NEG : InstFlag <"printNeg">;
85 def ABS : InstFlag <"printAbs">;
86 def UEM : InstFlag <"printUpdateExecMask">;
87 def UP : InstFlag <"printUpdatePred">;
89 // XXX: The r600g finalizer in Mesa expects last to be one in most cases.
90 // Once we start using the packetizer in this backend we should have this
92 def LAST : InstFlag<"printLast", 1>;
94 def FRAMEri : Operand<iPTR> {
95 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index);
98 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
99 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
100 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
101 def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>;
102 def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>;
103 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
105 class R600ALU_Word0 {
106 field bits<32> Word0;
114 bits<3> index_mode = 0;
118 bits<9> src0_sel = src0{8-0};
119 bits<2> src0_chan = src0{10-9};
120 bits<9> src1_sel = src1{8-0};
121 bits<2> src1_chan = src1{10-9};
123 let Word0{8-0} = src0_sel;
124 let Word0{9} = src0_rel;
125 let Word0{11-10} = src0_chan;
126 let Word0{12} = src0_neg;
127 let Word0{21-13} = src1_sel;
128 let Word0{22} = src1_rel;
129 let Word0{24-23} = src1_chan;
130 let Word0{25} = src1_neg;
131 let Word0{28-26} = index_mode;
132 let Word0{30-29} = pred_sel;
133 let Word0{31} = last;
136 class R600ALU_Word1 {
137 field bits<32> Word1;
140 bits<3> bank_swizzle = 0;
144 bits<7> dst_sel = dst{6-0};
145 bits<2> dst_chan = dst{10-9};
147 let Word1{20-18} = bank_swizzle;
148 let Word1{27-21} = dst_sel;
149 let Word1{28} = dst_rel;
150 let Word1{30-29} = dst_chan;
151 let Word1{31} = clamp;
154 class R600ALU_Word1_OP2 <bits<11> alu_inst> : R600ALU_Word1{
158 bits<1> update_exec_mask;
163 let Word1{0} = src0_abs;
164 let Word1{1} = src1_abs;
165 let Word1{2} = update_exec_mask;
166 let Word1{3} = update_pred;
167 let Word1{4} = write;
168 let Word1{6-5} = omod;
169 let Word1{17-7} = alu_inst;
172 class R600ALU_Word1_OP3 <bits<5> alu_inst> : R600ALU_Word1{
178 bits<9> src2_sel = src2{8-0};
179 bits<2> src2_chan = src2{10-9};
181 let Word1{8-0} = src2_sel;
182 let Word1{9} = src2_rel;
183 let Word1{11-10} = src2_chan;
184 let Word1{12} = src2_neg;
185 let Word1{17-13} = alu_inst;
189 field bits<32> Word0;
193 bits<1> FETCH_WHOLE_QUAD;
197 bits<6> MEGA_FETCH_COUNT;
199 let Word0{4-0} = VC_INST;
200 let Word0{6-5} = FETCH_TYPE;
201 let Word0{7} = FETCH_WHOLE_QUAD;
202 let Word0{15-8} = BUFFER_ID;
203 let Word0{22-16} = SRC_GPR;
204 let Word0{23} = SRC_REL;
205 let Word0{25-24} = SRC_SEL_X;
206 let Word0{31-26} = MEGA_FETCH_COUNT;
209 class VTX_WORD1_GPR {
210 field bits<32> Word1;
217 bits<1> USE_CONST_FIELDS;
219 bits<2> NUM_FORMAT_ALL;
220 bits<1> FORMAT_COMP_ALL;
221 bits<1> SRF_MODE_ALL;
223 let Word1{6-0} = DST_GPR;
224 let Word1{7} = DST_REL;
225 let Word1{8} = 0; // Reserved
226 let Word1{11-9} = DST_SEL_X;
227 let Word1{14-12} = DST_SEL_Y;
228 let Word1{17-15} = DST_SEL_Z;
229 let Word1{20-18} = DST_SEL_W;
230 let Word1{21} = USE_CONST_FIELDS;
231 let Word1{27-22} = DATA_FORMAT;
232 let Word1{29-28} = NUM_FORMAT_ALL;
233 let Word1{30} = FORMAT_COMP_ALL;
234 let Word1{31} = SRF_MODE_ALL;
238 XXX: R600 subtarget uses a slightly different encoding than the other
239 subtargets. We currently handle this in R600MCCodeEmitter, but we may
240 want to use these instruction classes in the future.
242 class R600ALU_Word1_OP2_r600 : R600ALU_Word1_OP2 {
247 let Inst{37} = fog_merge;
248 let Inst{39-38} = omod;
249 let Inst{49-40} = alu_inst;
252 class R600ALU_Word1_OP2_r700 : R600ALU_Word1_OP2 {
256 let Inst{38-37} = omod;
257 let Inst{49-39} = alu_inst;
261 def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
265 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
267 // Class for instructions with only one source register.
268 // If you add new ins to this instruction, make sure they are listed before
269 // $literal, because the backend currently assumes that the last operand is
270 // a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in
271 // R600Defines.h, R600InstrInfo::buildDefaultInstruction(),
272 // and R600InstrInfo::getOperandIdx().
273 class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
274 InstrItinClass itin = AnyALU> :
276 (outs R600_Reg32:$dst),
277 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
278 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
279 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
281 "$clamp $dst$write$dst_rel$omod, "
282 "$src0_neg$src0_abs$src0$src0_sel$src0_abs$src0_rel, "
283 "$literal $pred_sel$last"),
287 R600ALU_Word1_OP2 <inst> {
293 let update_exec_mask = 0;
295 let HasNativeOperands = 1;
297 let DisableEncoding = "$literal";
299 let Inst{31-0} = Word0;
300 let Inst{63-32} = Word1;
303 class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
304 InstrItinClass itin = AnyALU> :
305 R600_1OP <inst, opName,
306 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))]
309 // If you add our change the operands for R600_2OP instructions, you must
310 // also update the R600Op2OperandIndex::ROI enum in R600Defines.h,
311 // R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx().
312 class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
313 InstrItinClass itin = AnyALU> :
315 (outs R600_Reg32:$dst),
316 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
317 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
318 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
319 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
320 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
322 "$clamp $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
323 "$src0_neg$src0_abs$src0$src0_sel$src0_abs$src0_rel, "
324 "$src1_neg$src1_abs$src1$src1_sel$src1_abs$src1_rel, "
325 "$literal $pred_sel$last"),
329 R600ALU_Word1_OP2 <inst> {
331 let HasNativeOperands = 1;
333 let DisableEncoding = "$literal";
335 let Inst{31-0} = Word0;
336 let Inst{63-32} = Word1;
339 class R600_2OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
340 InstrItinClass itim = AnyALU> :
341 R600_2OP <inst, opName,
342 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
346 // If you add our change the operands for R600_3OP instructions, you must
347 // also update the R600Op3OperandIndex::ROI enum in R600Defines.h,
348 // R600InstrInfo::buildDefaultInstruction(), and
349 // R600InstrInfo::getOperandIdx().
350 class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
351 InstrItinClass itin = AnyALU> :
353 (outs R600_Reg32:$dst),
354 (ins REL:$dst_rel, CLAMP:$clamp,
355 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
356 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
357 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,
358 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
359 !strconcat(opName, "$clamp $dst$dst_rel, "
360 "$src0_neg$src0$src0_sel$src0_rel, "
361 "$src1_neg$src1$src1_sel$src1_rel, "
362 "$src2_neg$src2$src2_sel$src2_rel, "
363 "$literal $pred_sel$last"),
367 R600ALU_Word1_OP3<inst>{
369 let HasNativeOperands = 1;
370 let DisableEncoding = "$literal";
373 let Inst{31-0} = Word0;
374 let Inst{63-32} = Word1;
377 class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern,
378 InstrItinClass itin = VecALU> :
380 (outs R600_Reg32:$dst),
386 class R600_TEX <bits<11> inst, string opName, list<dag> pattern,
387 InstrItinClass itin = AnyALU> :
389 (outs R600_Reg128:$dst),
390 (ins R600_Reg128:$src0, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
391 !strconcat(opName, "$dst, $src0, $resourceId, $samplerId, $textureTarget"),
394 let Inst {10-0} = inst;
397 } // End mayLoad = 1, mayStore = 0, hasSideEffects = 0
399 def TEX_SHADOW : PatLeaf<
401 [{uint32_t TType = (uint32_t)N->getZExtValue();
402 return (TType >= 6 && TType <= 8) || (TType >= 11 && TType <= 13);
406 def TEX_RECT : PatLeaf<
408 [{uint32_t TType = (uint32_t)N->getZExtValue();
413 def TEX_ARRAY : PatLeaf<
415 [{uint32_t TType = (uint32_t)N->getZExtValue();
416 return TType == 9 || TType == 10 || TType == 15 || TType == 16;
420 def TEX_SHADOW_ARRAY : PatLeaf<
422 [{uint32_t TType = (uint32_t)N->getZExtValue();
423 return TType == 11 || TType == 12 || TType == 17;
427 class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
428 dag ins, string asm, list<dag> pattern> :
429 InstR600ISA <outs, ins, asm, pattern> {
446 // CF_ALLOC_EXPORT_WORD0_RAT
447 let Inst{3-0} = rat_id;
448 let Inst{9-4} = rat_inst;
449 let Inst{10} = 0; // Reserved
450 let Inst{12-11} = RIM;
451 let Inst{14-13} = TYPE;
452 let Inst{21-15} = RW_GPR;
453 let Inst{22} = RW_REL;
454 let Inst{29-23} = INDEX_GPR;
455 let Inst{31-30} = ELEM_SIZE;
457 // CF_ALLOC_EXPORT_WORD1_BUF
458 let Inst{43-32} = ARRAY_SIZE;
459 let Inst{47-44} = COMP_MASK;
460 let Inst{51-48} = BURST_COUNT;
463 let Inst{61-54} = cf_inst;
465 let Inst{63} = BARRIER;
468 class LoadParamFrag <PatFrag load_type> : PatFrag <
469 (ops node:$ptr), (load_type node:$ptr),
470 [{ return isParamLoad(dyn_cast<LoadSDNode>(N)); }]
473 def load_param : LoadParamFrag<load>;
474 def load_param_zexti8 : LoadParamFrag<zextloadi8>;
475 def load_param_zexti16 : LoadParamFrag<zextloadi16>;
477 def isR600 : Predicate<"Subtarget.device()"
478 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX">;
479 def isR700 : Predicate<"Subtarget.device()"
480 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX &&"
481 "Subtarget.device()->getDeviceFlag()"
482 ">= OCL_DEVICE_RV710">;
483 def isEG : Predicate<
484 "Subtarget.device()->getGeneration() >= AMDGPUDeviceInfo::HD5XXX && "
485 "Subtarget.device()->getGeneration() < AMDGPUDeviceInfo::HD7XXX && "
486 "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">;
488 def isCayman : Predicate<"Subtarget.device()"
489 "->getDeviceFlag() == OCL_DEVICE_CAYMAN">;
490 def isEGorCayman : Predicate<"Subtarget.device()"
491 "->getGeneration() == AMDGPUDeviceInfo::HD5XXX"
492 "|| Subtarget.device()->getGeneration() =="
493 "AMDGPUDeviceInfo::HD6XXX">;
495 def isR600toCayman : Predicate<
496 "Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX">;
498 //===----------------------------------------------------------------------===//
500 //===----------------------------------------------------------------------===//
502 def INTERP_PAIR_XY : AMDGPUShaderInst <
503 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1),
504 (ins i32imm:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
505 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
508 def INTERP_PAIR_ZW : AMDGPUShaderInst <
509 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1),
510 (ins i32imm:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
511 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",
514 def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS",
515 SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>,
519 //===----------------------------------------------------------------------===//
520 // Interpolation Instructions
521 //===----------------------------------------------------------------------===//
523 def INTERP_VEC_LOAD : AMDGPUShaderInst <
524 (outs R600_Reg128:$dst),
526 "INTERP_LOAD $src0 : $dst",
529 def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> {
530 let bank_swizzle = 5;
533 def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> {
534 let bank_swizzle = 5;
537 def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>;
539 //===----------------------------------------------------------------------===//
540 // Export Instructions
541 //===----------------------------------------------------------------------===//
543 def ExportType : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
545 def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType,
546 [SDNPHasChain, SDNPSideEffect]>;
549 field bits<32> Word0;
556 let Word0{12-0} = arraybase;
557 let Word0{14-13} = type;
558 let Word0{21-15} = gpr;
559 let Word0{22} = 0; // RW_REL
560 let Word0{29-23} = 0; // INDEX_GPR
561 let Word0{31-30} = elem_size;
564 class ExportSwzWord1 {
565 field bits<32> Word1;
574 let Word1{2-0} = sw_x;
575 let Word1{5-3} = sw_y;
576 let Word1{8-6} = sw_z;
577 let Word1{11-9} = sw_w;
580 class ExportBufWord1 {
581 field bits<32> Word1;
588 let Word1{11-0} = arraySize;
589 let Word1{15-12} = compMask;
592 multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
593 def : Pat<(int_R600_store_pixel_depth R600_Reg32:$reg),
595 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
596 0, 61, 0, 7, 7, 7, cf_inst, 0)
599 def : Pat<(int_R600_store_pixel_stencil R600_Reg32:$reg),
601 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
602 0, 61, 7, 0, 7, 7, cf_inst, 0)
605 def : Pat<(int_R600_store_dummy (i32 imm:$type)),
607 (v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0)
610 def : Pat<(int_R600_store_dummy 1),
612 (v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0)
615 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
616 (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)),
617 (ExportInst R600_Reg128:$src, imm:$type, imm:$base,
618 imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0)
623 multiclass SteamOutputExportPattern<Instruction ExportInst,
624 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> {
626 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
627 (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)),
628 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
629 4095, imm:$mask, buf0inst, 0)>;
631 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
632 (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)),
633 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
634 4095, imm:$mask, buf1inst, 0)>;
636 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
637 (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)),
638 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
639 4095, imm:$mask, buf2inst, 0)>;
641 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
642 (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)),
643 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
644 4095, imm:$mask, buf3inst, 0)>;
647 let usesCustomInserter = 1 in {
649 class ExportSwzInst : InstR600ISA<(
651 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
652 i32imm:$sw_x, i32imm:$sw_y, i32imm:$sw_z, i32imm:$sw_w, i32imm:$inst,
654 !strconcat("EXPORT", " $gpr"),
655 []>, ExportWord0, ExportSwzWord1 {
657 let Inst{31-0} = Word0;
658 let Inst{63-32} = Word1;
661 } // End usesCustomInserter = 1
663 class ExportBufInst : InstR600ISA<(
665 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
666 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop),
667 !strconcat("EXPORT", " $gpr"),
668 []>, ExportWord0, ExportBufWord1 {
670 let Inst{31-0} = Word0;
671 let Inst{63-32} = Word1;
674 let Predicates = [isR600toCayman] in {
676 //===----------------------------------------------------------------------===//
677 // Common Instructions R600, R700, Evergreen, Cayman
678 //===----------------------------------------------------------------------===//
680 def ADD : R600_2OP_Helper <0x0, "ADD", fadd>;
681 // Non-IEEE MUL: 0 * anything = 0
682 def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE", int_AMDGPU_mul>;
683 def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>;
684 def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax>;
685 def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin>;
687 // For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
688 // so some of the instruction names don't match the asm string.
689 // XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
690 def SETE : R600_2OP <
692 [(set R600_Reg32:$dst,
693 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
699 [(set R600_Reg32:$dst,
700 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
706 [(set R600_Reg32:$dst,
707 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
713 [(set R600_Reg32:$dst,
714 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
718 def SETE_DX10 : R600_2OP <
720 [(set R600_Reg32:$dst,
721 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
725 def SETGT_DX10 : R600_2OP <
727 [(set R600_Reg32:$dst,
728 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
732 def SETGE_DX10 : R600_2OP <
734 [(set R600_Reg32:$dst,
735 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
739 def SETNE_DX10 : R600_2OP <
741 [(set R600_Reg32:$dst,
742 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
746 def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>;
747 def TRUNC : R600_1OP_Helper <0x11, "TRUNC", int_AMDGPU_trunc>;
748 def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;
749 def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>;
750 def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>;
752 def MOV : R600_1OP <0x19, "MOV", []>;
754 let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in {
756 class MOV_IMM <ValueType vt, Operand immType> : AMDGPUInst <
757 (outs R600_Reg32:$dst),
763 } // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1
765 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
768 (MOV_IMM_I32 imm:$val)
771 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
774 (MOV_IMM_F32 fpimm:$val)
777 def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>;
778 def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>;
779 def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>;
780 def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>;
782 let hasSideEffects = 1 in {
784 def KILLGT : R600_2OP <0x2D, "KILLGT", []>;
786 } // end hasSideEffects
788 def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>;
789 def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>;
790 def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>;
791 def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>;
792 def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>;
793 def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>;
794 def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", AMDGPUsmax>;
795 def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", AMDGPUsmin>;
796 def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", AMDGPUumax>;
797 def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", AMDGPUumin>;
799 def SETE_INT : R600_2OP <
801 [(set (i32 R600_Reg32:$dst),
802 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))]
805 def SETGT_INT : R600_2OP <
807 [(set (i32 R600_Reg32:$dst),
808 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))]
811 def SETGE_INT : R600_2OP <
813 [(set (i32 R600_Reg32:$dst),
814 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
817 def SETNE_INT : R600_2OP <
819 [(set (i32 R600_Reg32:$dst),
820 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
823 def SETGT_UINT : R600_2OP <
825 [(set (i32 R600_Reg32:$dst),
826 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))]
829 def SETGE_UINT : R600_2OP <
831 [(set (i32 R600_Reg32:$dst),
832 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
835 def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>;
836 def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>;
837 def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>;
838 def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>;
840 def CNDE_INT : R600_3OP <
842 [(set (i32 R600_Reg32:$dst),
843 (selectcc (i32 R600_Reg32:$src0), 0,
844 (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
848 def CNDGE_INT : R600_3OP <
850 [(set (i32 R600_Reg32:$dst),
851 (selectcc (i32 R600_Reg32:$src0), 0,
852 (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
856 def CNDGT_INT : R600_3OP <
858 [(set (i32 R600_Reg32:$dst),
859 (selectcc (i32 R600_Reg32:$src0), 0,
860 (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
864 //===----------------------------------------------------------------------===//
865 // Texture instructions
866 //===----------------------------------------------------------------------===//
868 def TEX_LD : R600_TEX <
870 [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
872 let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $resourceId, $samplerId, $textureTarget";
873 let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget);
876 def TEX_GET_TEXTURE_RESINFO : R600_TEX <
877 0x04, "TEX_GET_TEXTURE_RESINFO",
878 [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
881 def TEX_GET_GRADIENTS_H : R600_TEX <
882 0x07, "TEX_GET_GRADIENTS_H",
883 [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
886 def TEX_GET_GRADIENTS_V : R600_TEX <
887 0x08, "TEX_GET_GRADIENTS_V",
888 [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
891 def TEX_SET_GRADIENTS_H : R600_TEX <
892 0x0B, "TEX_SET_GRADIENTS_H",
896 def TEX_SET_GRADIENTS_V : R600_TEX <
897 0x0C, "TEX_SET_GRADIENTS_V",
901 def TEX_SAMPLE : R600_TEX <
903 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
906 def TEX_SAMPLE_C : R600_TEX <
907 0x18, "TEX_SAMPLE_C",
908 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))]
911 def TEX_SAMPLE_L : R600_TEX <
912 0x11, "TEX_SAMPLE_L",
913 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
916 def TEX_SAMPLE_C_L : R600_TEX <
917 0x19, "TEX_SAMPLE_C_L",
918 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))]
921 def TEX_SAMPLE_LB : R600_TEX <
922 0x12, "TEX_SAMPLE_LB",
923 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0,imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
926 def TEX_SAMPLE_C_LB : R600_TEX <
927 0x1A, "TEX_SAMPLE_C_LB",
928 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))]
931 def TEX_SAMPLE_G : R600_TEX <
932 0x14, "TEX_SAMPLE_G",
936 def TEX_SAMPLE_C_G : R600_TEX <
937 0x1C, "TEX_SAMPLE_C_G",
941 //===----------------------------------------------------------------------===//
942 // Helper classes for common instructions
943 //===----------------------------------------------------------------------===//
945 class MUL_LIT_Common <bits<5> inst> : R600_3OP <
950 class MULADD_Common <bits<5> inst> : R600_3OP <
955 class MULADD_IEEE_Common <bits<5> inst> : R600_3OP <
957 [(set (f32 R600_Reg32:$dst),
958 (fadd (fmul R600_Reg32:$src0, R600_Reg32:$src1), R600_Reg32:$src2))]
961 class CNDE_Common <bits<5> inst> : R600_3OP <
963 [(set R600_Reg32:$dst,
964 (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
965 (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
969 class CNDGT_Common <bits<5> inst> : R600_3OP <
971 [(set R600_Reg32:$dst,
972 (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
973 (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
977 class CNDGE_Common <bits<5> inst> : R600_3OP <
979 [(set R600_Reg32:$dst,
980 (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
981 (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
985 multiclass DOT4_Common <bits<11> inst> {
987 def _pseudo : R600_REDUCTION <inst,
988 (ins R600_Reg128:$src0, R600_Reg128:$src1),
989 "DOT4 $dst $src0, $src1",
990 [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))]
993 def _real : R600_2OP <inst, "DOT4", []>;
996 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
997 multiclass CUBE_Common <bits<11> inst> {
999 def _pseudo : InstR600 <
1001 (outs R600_Reg128:$dst),
1002 (ins R600_Reg128:$src),
1004 [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))],
1010 def _real : R600_2OP <inst, "CUBE", []>;
1012 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
1014 class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1015 inst, "EXP_IEEE", fexp2
1018 class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper <
1019 inst, "FLT_TO_INT", fp_to_sint
1022 class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1023 inst, "INT_TO_FLT", sint_to_fp
1026 class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1027 inst, "FLT_TO_UINT", fp_to_uint
1030 class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1031 inst, "UINT_TO_FLT", uint_to_fp
1034 class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <
1035 inst, "LOG_CLAMPED", []
1038 class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1039 inst, "LOG_IEEE", flog2
1042 class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>;
1043 class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>;
1044 class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>;
1045 class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper <
1046 inst, "MULHI_INT", mulhs
1048 class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper <
1049 inst, "MULHI", mulhu
1051 class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper <
1052 inst, "MULLO_INT", mul
1054 class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []>;
1056 class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <
1057 inst, "RECIP_CLAMPED", []
1060 class RECIP_IEEE_Common <bits<11> inst> : R600_1OP <
1061 inst, "RECIP_IEEE", [(set R600_Reg32:$dst, (fdiv FP_ONE, R600_Reg32:$src0))]
1064 class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1065 inst, "RECIP_UINT", AMDGPUurecip
1068 class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper <
1069 inst, "RECIPSQRT_CLAMPED", int_AMDGPU_rsq
1072 class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP <
1073 inst, "RECIPSQRT_IEEE", []
1076 class SIN_Common <bits<11> inst> : R600_1OP <
1081 class COS_Common <bits<11> inst> : R600_1OP <
1086 //===----------------------------------------------------------------------===//
1087 // Helper patterns for complex intrinsics
1088 //===----------------------------------------------------------------------===//
1090 multiclass DIV_Common <InstR600 recip_ieee> {
1092 (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
1093 (MUL_IEEE R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
1097 (fdiv R600_Reg32:$src0, R600_Reg32:$src1),
1098 (MUL_IEEE R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
1102 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat <
1103 (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w),
1104 (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x))
1107 //===----------------------------------------------------------------------===//
1108 // R600 / R700 Instructions
1109 //===----------------------------------------------------------------------===//
1111 let Predicates = [isR600] in {
1113 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
1114 def MULADD_r600 : MULADD_Common<0x10>;
1115 def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>;
1116 def CNDE_r600 : CNDE_Common<0x18>;
1117 def CNDGT_r600 : CNDGT_Common<0x19>;
1118 def CNDGE_r600 : CNDGE_Common<0x1A>;
1119 defm DOT4_r600 : DOT4_Common<0x50>;
1120 defm CUBE_r600 : CUBE_Common<0x52>;
1121 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
1122 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
1123 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
1124 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
1125 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
1126 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
1127 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
1128 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
1129 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
1130 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
1131 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
1132 def SIN_r600 : SIN_Common<0x6E>;
1133 def COS_r600 : COS_Common<0x6F>;
1134 def ASHR_r600 : ASHR_Common<0x70>;
1135 def LSHR_r600 : LSHR_Common<0x71>;
1136 def LSHL_r600 : LSHL_Common<0x72>;
1137 def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
1138 def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
1139 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
1140 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
1141 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
1143 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
1144 def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL, R600_Reg32>;
1145 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
1147 def : Pat<(fsqrt R600_Reg32:$src),
1148 (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_r600 R600_Reg32:$src))>;
1150 def R600_ExportSwz : ExportSwzInst {
1151 let Word1{20-17} = 1; // BURST_COUNT
1152 let Word1{21} = eop;
1153 let Word1{22} = 1; // VALID_PIXEL_MODE
1154 let Word1{30-23} = inst;
1155 let Word1{31} = 1; // BARRIER
1157 defm : ExportPattern<R600_ExportSwz, 39>;
1159 def R600_ExportBuf : ExportBufInst {
1160 let Word1{20-17} = 1; // BURST_COUNT
1161 let Word1{21} = eop;
1162 let Word1{22} = 1; // VALID_PIXEL_MODE
1163 let Word1{30-23} = inst;
1164 let Word1{31} = 1; // BARRIER
1166 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>;
1169 // Helper pattern for normalizing inputs to triginomic instructions for R700+
1171 class COS_PAT <InstR600 trig> : Pat<
1172 (fcos R600_Reg32:$src),
1173 (trig (MUL_IEEE (MOV_IMM_I32 CONST.TWO_PI_INV), R600_Reg32:$src))
1176 class SIN_PAT <InstR600 trig> : Pat<
1177 (fsin R600_Reg32:$src),
1178 (trig (MUL_IEEE (MOV_IMM_I32 CONST.TWO_PI_INV), R600_Reg32:$src))
1181 //===----------------------------------------------------------------------===//
1182 // R700 Only instructions
1183 //===----------------------------------------------------------------------===//
1185 let Predicates = [isR700] in {
1186 def SIN_r700 : SIN_Common<0x6E>;
1187 def COS_r700 : COS_Common<0x6F>;
1189 // R700 normalizes inputs to SIN/COS the same as EG
1190 def : SIN_PAT <SIN_r700>;
1191 def : COS_PAT <COS_r700>;
1194 //===----------------------------------------------------------------------===//
1195 // Evergreen Only instructions
1196 //===----------------------------------------------------------------------===//
1198 let Predicates = [isEG] in {
1200 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
1201 defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
1203 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
1204 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
1205 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
1206 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
1207 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
1208 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
1209 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
1210 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
1211 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
1212 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
1213 def SIN_eg : SIN_Common<0x8D>;
1214 def COS_eg : COS_Common<0x8E>;
1216 def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL, R600_Reg32>;
1217 def : SIN_PAT <SIN_eg>;
1218 def : COS_PAT <COS_eg>;
1219 def : Pat<(fsqrt R600_Reg32:$src),
1220 (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_eg R600_Reg32:$src))>;
1221 } // End Predicates = [isEG]
1223 //===----------------------------------------------------------------------===//
1224 // Evergreen / Cayman Instructions
1225 //===----------------------------------------------------------------------===//
1227 let Predicates = [isEGorCayman] in {
1229 // BFE_UINT - bit_extract, an optimization for mask and shift
1234 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
1239 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0
1240 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
1241 // (16,8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
1242 // (24,8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
1243 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
1244 [(set R600_Reg32:$dst, (int_AMDIL_bit_extract_u32 R600_Reg32:$src0,
1246 R600_Reg32:$src2))],
1250 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT",
1251 [(set R600_Reg32:$dst, (AMDGPUbitalign R600_Reg32:$src0, R600_Reg32:$src1,
1252 R600_Reg32:$src2))],
1256 def MULADD_eg : MULADD_Common<0x14>;
1257 def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>;
1258 def ASHR_eg : ASHR_Common<0x15>;
1259 def LSHR_eg : LSHR_Common<0x16>;
1260 def LSHL_eg : LSHL_Common<0x17>;
1261 def CNDE_eg : CNDE_Common<0x19>;
1262 def CNDGT_eg : CNDGT_Common<0x1A>;
1263 def CNDGE_eg : CNDGE_Common<0x1B>;
1264 def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
1265 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
1266 defm DOT4_eg : DOT4_Common<0xBE>;
1267 defm CUBE_eg : CUBE_Common<0xC0>;
1269 let hasSideEffects = 1 in {
1270 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", []>;
1273 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
1275 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
1279 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
1281 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
1285 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
1287 // TRUNC is used for the FLT_TO_INT instructions to work around a
1288 // perceived problem where the rounding modes are applied differently
1289 // depending on the instruction and the slot they are in.
1291 // https://bugs.freedesktop.org/show_bug.cgi?id=50232
1292 // Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c
1294 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
1295 // which do not need to be truncated since the fp values are 0.0f or 1.0f.
1296 // We should look into handling these cases separately.
1297 def : Pat<(fp_to_sint R600_Reg32:$src0),
1298 (FLT_TO_INT_eg (TRUNC R600_Reg32:$src0))>;
1300 def : Pat<(fp_to_uint R600_Reg32:$src0),
1301 (FLT_TO_UINT_eg (TRUNC R600_Reg32:$src0))>;
1303 def EG_ExportSwz : ExportSwzInst {
1304 let Word1{19-16} = 1; // BURST_COUNT
1305 let Word1{20} = 1; // VALID_PIXEL_MODE
1306 let Word1{21} = eop;
1307 let Word1{29-22} = inst;
1308 let Word1{30} = 0; // MARK
1309 let Word1{31} = 1; // BARRIER
1311 defm : ExportPattern<EG_ExportSwz, 83>;
1313 def EG_ExportBuf : ExportBufInst {
1314 let Word1{19-16} = 1; // BURST_COUNT
1315 let Word1{20} = 1; // VALID_PIXEL_MODE
1316 let Word1{21} = eop;
1317 let Word1{29-22} = inst;
1318 let Word1{30} = 0; // MARK
1319 let Word1{31} = 1; // BARRIER
1321 defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>;
1323 //===----------------------------------------------------------------------===//
1324 // Memory read/write instructions
1325 //===----------------------------------------------------------------------===//
1326 let usesCustomInserter = 1 in {
1328 class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> comp_mask, string name,
1330 : EG_CF_RAT <0x57, 0x2, 0, (outs), ins,
1331 !strconcat(name, " $rw_gpr, $index_gpr, $eop"), pattern> {
1333 // XXX: Have a separate instruction for non-indexed writes.
1339 let COMP_MASK = comp_mask;
1340 let BURST_COUNT = 0;
1346 } // End usesCustomInserter = 1
1349 def RAT_WRITE_CACHELESS_32_eg : RAT_WRITE_CACHELESS_eg <
1350 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1351 0x1, "RAT_WRITE_CACHELESS_32_eg",
1352 [(global_store (i32 R600_TReg32_X:$rw_gpr), R600_TReg32_X:$index_gpr)]
1356 def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg <
1357 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1358 0xf, "RAT_WRITE_CACHELESS_128",
1359 [(global_store (v4i32 R600_Reg128:$rw_gpr), R600_TReg32_X:$index_gpr)]
1362 class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
1363 : InstR600ISA <outs, (ins MEMxi:$ptr), name#" $dst, $ptr", pattern>,
1364 VTX_WORD1_GPR, VTX_WORD0 {
1369 let FETCH_WHOLE_QUAD = 0;
1370 let BUFFER_ID = buffer_id;
1372 // XXX: We can infer this field based on the SRC_GPR. This would allow us
1373 // to store vertex addresses in any channel, not just X.
1376 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,
1377 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,
1378 // however, based on my testing if USE_CONST_FIELDS is set, then all
1379 // these fields need to be set to 0.
1380 let USE_CONST_FIELDS = 0;
1381 let NUM_FORMAT_ALL = 1;
1382 let FORMAT_COMP_ALL = 0;
1383 let SRF_MODE_ALL = 0;
1385 let Inst{31-0} = Word0;
1386 let Inst{63-32} = Word1;
1387 // LLVM can only encode 64-bit instructions, so these fields are manually
1388 // encoded in R600CodeEmitter
1391 // bits<2> ENDIAN_SWAP = 0;
1392 // bits<1> CONST_BUF_NO_STRIDE = 0;
1393 // bits<1> MEGA_FETCH = 0;
1394 // bits<1> ALT_CONST = 0;
1395 // bits<2> BUFFER_INDEX_MODE = 0;
1399 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1400 // is done in R600CodeEmitter
1402 // Inst{79-64} = OFFSET;
1403 // Inst{81-80} = ENDIAN_SWAP;
1404 // Inst{82} = CONST_BUF_NO_STRIDE;
1405 // Inst{83} = MEGA_FETCH;
1406 // Inst{84} = ALT_CONST;
1407 // Inst{86-85} = BUFFER_INDEX_MODE;
1408 // Inst{95-86} = 0; Reserved
1410 // VTX_WORD3 (Padding)
1412 // Inst{127-96} = 0;
1415 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
1416 : VTX_READ_eg <"VTX_READ_8", buffer_id, (outs R600_TReg32_X:$dst),
1419 let MEGA_FETCH_COUNT = 1;
1421 let DST_SEL_Y = 7; // Masked
1422 let DST_SEL_Z = 7; // Masked
1423 let DST_SEL_W = 7; // Masked
1424 let DATA_FORMAT = 1; // FMT_8
1427 class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
1428 : VTX_READ_eg <"VTX_READ_16", buffer_id, (outs R600_TReg32_X:$dst),
1430 let MEGA_FETCH_COUNT = 2;
1432 let DST_SEL_Y = 7; // Masked
1433 let DST_SEL_Z = 7; // Masked
1434 let DST_SEL_W = 7; // Masked
1435 let DATA_FORMAT = 5; // FMT_16
1439 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
1440 : VTX_READ_eg <"VTX_READ_32", buffer_id, (outs R600_TReg32_X:$dst),
1443 let MEGA_FETCH_COUNT = 4;
1445 let DST_SEL_Y = 7; // Masked
1446 let DST_SEL_Z = 7; // Masked
1447 let DST_SEL_W = 7; // Masked
1448 let DATA_FORMAT = 0xD; // COLOR_32
1450 // This is not really necessary, but there were some GPU hangs that appeared
1451 // to be caused by ALU instructions in the next instruction group that wrote
1452 // to the $ptr registers of the VTX_READ.
1454 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
1455 // %T2_X<def> = MOV %ZERO
1456 //Adding this constraint prevents this from happening.
1457 let Constraints = "$ptr.ptr = $dst";
1460 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
1461 : VTX_READ_eg <"VTX_READ_128", buffer_id, (outs R600_Reg128:$dst),
1464 let MEGA_FETCH_COUNT = 16;
1469 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
1471 // XXX: Need to force VTX_READ_128 instructions to write to the same register
1472 // that holds its buffer address to avoid potential hangs. We can't use
1473 // the same constraint as VTX_READ_32_eg, because the $ptr.ptr and $dst
1474 // registers are different sizes.
1477 //===----------------------------------------------------------------------===//
1478 // VTX Read from parameter memory space
1479 //===----------------------------------------------------------------------===//
1481 def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <0,
1482 [(set (i32 R600_TReg32_X:$dst), (load_param_zexti8 ADDRVTX_READ:$ptr))]
1485 def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <0,
1486 [(set (i32 R600_TReg32_X:$dst), (load_param_zexti16 ADDRVTX_READ:$ptr))]
1489 def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0,
1490 [(set (i32 R600_TReg32_X:$dst), (load_param ADDRVTX_READ:$ptr))]
1493 def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <0,
1494 [(set (v4i32 R600_Reg128:$dst), (load_param ADDRVTX_READ:$ptr))]
1497 //===----------------------------------------------------------------------===//
1498 // VTX Read from global memory space
1499 //===----------------------------------------------------------------------===//
1502 def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1,
1503 [(set (i32 R600_TReg32_X:$dst), (zextloadi8_global ADDRVTX_READ:$ptr))]
1507 def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1,
1508 [(set (i32 R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))]
1512 def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
1513 [(set (v4i32 R600_Reg128:$dst), (global_load ADDRVTX_READ:$ptr))]
1516 //===----------------------------------------------------------------------===//
1518 // XXX: We are currently storing all constants in the global address space.
1519 //===----------------------------------------------------------------------===//
1521 def CONSTANT_LOAD_eg : VTX_READ_32_eg <1,
1522 [(set (i32 R600_TReg32_X:$dst), (constant_load ADDRVTX_READ:$ptr))]
1527 //===----------------------------------------------------------------------===//
1528 // Regist loads and stores - for indirect addressing
1529 //===----------------------------------------------------------------------===//
1531 defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>;
1533 let Predicates = [isCayman] in {
1535 let isVector = 1 in {
1537 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
1539 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
1540 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
1541 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
1542 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
1543 def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>;
1544 def EXP_IEEE_cm : EXP_IEEE_Common<0x81>;
1545 def LOG_IEEE_cm : LOG_IEEE_Common<0x83>;
1546 def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>;
1547 def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>;
1548 def SIN_cm : SIN_Common<0x8D>;
1549 def COS_cm : COS_Common<0x8E>;
1550 } // End isVector = 1
1552 def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL, R600_Reg32>;
1553 def : SIN_PAT <SIN_cm>;
1554 def : COS_PAT <COS_cm>;
1556 defm DIV_cm : DIV_Common<RECIP_IEEE_cm>;
1558 // RECIP_UINT emulation for Cayman
1560 (AMDGPUurecip R600_Reg32:$src0),
1561 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg R600_Reg32:$src0)),
1562 (MOV_IMM_I32 0x4f800000)))
1566 def : Pat<(fsqrt R600_Reg32:$src),
1567 (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm R600_Reg32:$src))>;
1571 //===----------------------------------------------------------------------===//
1572 // Branch Instructions
1573 //===----------------------------------------------------------------------===//
1576 def IF_PREDICATE_SET : ILFormat<(outs), (ins GPRI32:$src),
1577 "IF_PREDICATE_SET $src", []>;
1579 def PREDICATED_BREAK : ILFormat<(outs), (ins GPRI32:$src),
1580 "PREDICATED_BREAK $src", []>;
1582 //===----------------------------------------------------------------------===//
1583 // Pseudo instructions
1584 //===----------------------------------------------------------------------===//
1586 let isPseudo = 1 in {
1588 def PRED_X : InstR600 <
1589 0, (outs R600_Predicate_Bit:$dst),
1590 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
1592 let FlagOperandIdx = 3;
1595 let isTerminator = 1, isBranch = 1 in {
1596 def JUMP_COND : InstR600 <0x10,
1598 (ins brtarget:$target, R600_Predicate_Bit:$p),
1599 "JUMP $target ($p)",
1603 def JUMP : InstR600 <0x10,
1605 (ins brtarget:$target),
1610 let isPredicable = 1;
1614 } // End isTerminator = 1, isBranch = 1
1616 let usesCustomInserter = 1 in {
1618 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
1620 def MASK_WRITE : AMDGPUShaderInst <
1622 (ins R600_Reg32:$src),
1627 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 1
1630 def TXD: AMDGPUShaderInst <
1631 (outs R600_Reg128:$dst),
1632 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
1633 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
1634 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
1637 def TXD_SHADOW: AMDGPUShaderInst <
1638 (outs R600_Reg128:$dst),
1639 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
1640 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
1641 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))]
1644 } // End isPseudo = 1
1645 } // End usesCustomInserter = 1
1647 def CLAMP_R600 : CLAMP <R600_Reg32>;
1648 def FABS_R600 : FABS<R600_Reg32>;
1649 def FNEG_R600 : FNEG<R600_Reg32>;
1651 //===---------------------------------------------------------------------===//
1652 // Return instruction
1653 //===---------------------------------------------------------------------===//
1654 let isTerminator = 1, isReturn = 1, hasCtrlDep = 1,
1655 usesCustomInserter = 1 in {
1656 def RETURN : ILFormat<(outs), (ins variable_ops),
1657 "RETURN", [(IL_retflag)]>;
1661 //===----------------------------------------------------------------------===//
1662 // Constant Buffer Addressing Support
1663 //===----------------------------------------------------------------------===//
1665 let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
1666 def CONST_COPY : Instruction {
1667 let OutOperandList = (outs R600_Reg32:$dst);
1668 let InOperandList = (ins i32imm:$src);
1670 [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];
1671 let AsmString = "CONST_COPY";
1672 let neverHasSideEffects = 1;
1673 let isAsCheapAsAMove = 1;
1674 let Itinerary = NullALU;
1676 } // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
1678 def TEX_VTX_CONSTBUF :
1679 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "VTX_READ_eg $dst, $ptr",
1680 [(set R600_Reg128:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$BUFFER_ID)))]>,
1681 VTX_WORD1_GPR, VTX_WORD0 {
1685 let FETCH_WHOLE_QUAD = 0;
1689 let USE_CONST_FIELDS = 0;
1690 let NUM_FORMAT_ALL = 2;
1691 let FORMAT_COMP_ALL = 1;
1692 let SRF_MODE_ALL = 1;
1693 let MEGA_FETCH_COUNT = 16;
1698 let DATA_FORMAT = 35;
1700 let Inst{31-0} = Word0;
1701 let Inst{63-32} = Word1;
1703 // LLVM can only encode 64-bit instructions, so these fields are manually
1704 // encoded in R600CodeEmitter
1707 // bits<2> ENDIAN_SWAP = 0;
1708 // bits<1> CONST_BUF_NO_STRIDE = 0;
1709 // bits<1> MEGA_FETCH = 0;
1710 // bits<1> ALT_CONST = 0;
1711 // bits<2> BUFFER_INDEX_MODE = 0;
1715 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1716 // is done in R600CodeEmitter
1718 // Inst{79-64} = OFFSET;
1719 // Inst{81-80} = ENDIAN_SWAP;
1720 // Inst{82} = CONST_BUF_NO_STRIDE;
1721 // Inst{83} = MEGA_FETCH;
1722 // Inst{84} = ALT_CONST;
1723 // Inst{86-85} = BUFFER_INDEX_MODE;
1724 // Inst{95-86} = 0; Reserved
1726 // VTX_WORD3 (Padding)
1728 // Inst{127-96} = 0;
1732 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr",
1733 [(set R600_Reg128:$dst, (int_R600_load_texbuf ADDRGA_VAR_OFFSET:$ptr, imm:$BUFFER_ID))]>,
1734 VTX_WORD1_GPR, VTX_WORD0 {
1738 let FETCH_WHOLE_QUAD = 0;
1742 let USE_CONST_FIELDS = 1;
1743 let NUM_FORMAT_ALL = 0;
1744 let FORMAT_COMP_ALL = 0;
1745 let SRF_MODE_ALL = 1;
1746 let MEGA_FETCH_COUNT = 16;
1751 let DATA_FORMAT = 0;
1753 let Inst{31-0} = Word0;
1754 let Inst{63-32} = Word1;
1756 // LLVM can only encode 64-bit instructions, so these fields are manually
1757 // encoded in R600CodeEmitter
1760 // bits<2> ENDIAN_SWAP = 0;
1761 // bits<1> CONST_BUF_NO_STRIDE = 0;
1762 // bits<1> MEGA_FETCH = 0;
1763 // bits<1> ALT_CONST = 0;
1764 // bits<2> BUFFER_INDEX_MODE = 0;
1768 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1769 // is done in R600CodeEmitter
1771 // Inst{79-64} = OFFSET;
1772 // Inst{81-80} = ENDIAN_SWAP;
1773 // Inst{82} = CONST_BUF_NO_STRIDE;
1774 // Inst{83} = MEGA_FETCH;
1775 // Inst{84} = ALT_CONST;
1776 // Inst{86-85} = BUFFER_INDEX_MODE;
1777 // Inst{95-86} = 0; Reserved
1779 // VTX_WORD3 (Padding)
1781 // Inst{127-96} = 0;
1786 //===--------------------------------------------------------------------===//
1787 // Instructions support
1788 //===--------------------------------------------------------------------===//
1789 //===---------------------------------------------------------------------===//
1790 // Custom Inserter for Branches and returns, this eventually will be a
1792 //===---------------------------------------------------------------------===//
1793 let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in {
1794 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
1795 "; Pseudo unconditional branch instruction",
1797 defm BRANCH_COND : BranchConditional<IL_brcond>;
1800 //===---------------------------------------------------------------------===//
1801 // Flow and Program control Instructions
1802 //===---------------------------------------------------------------------===//
1803 let isTerminator=1 in {
1804 def SWITCH : ILFormat< (outs), (ins GPRI32:$src),
1805 !strconcat("SWITCH", " $src"), []>;
1806 def CASE : ILFormat< (outs), (ins GPRI32:$src),
1807 !strconcat("CASE", " $src"), []>;
1808 def BREAK : ILFormat< (outs), (ins),
1810 def CONTINUE : ILFormat< (outs), (ins),
1812 def DEFAULT : ILFormat< (outs), (ins),
1814 def ELSE : ILFormat< (outs), (ins),
1816 def ENDSWITCH : ILFormat< (outs), (ins),
1818 def ENDMAIN : ILFormat< (outs), (ins),
1820 def END : ILFormat< (outs), (ins),
1822 def ENDFUNC : ILFormat< (outs), (ins),
1824 def ENDIF : ILFormat< (outs), (ins),
1826 def WHILELOOP : ILFormat< (outs), (ins),
1828 def ENDLOOP : ILFormat< (outs), (ins),
1830 def FUNC : ILFormat< (outs), (ins),
1832 def RETDYN : ILFormat< (outs), (ins),
1834 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1835 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">;
1836 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1837 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">;
1838 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1839 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">;
1840 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1841 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">;
1842 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1843 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">;
1844 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1845 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">;
1846 defm IFC : BranchInstr2<"IFC">;
1847 defm BREAKC : BranchInstr2<"BREAKC">;
1848 defm CONTINUEC : BranchInstr2<"CONTINUEC">;
1851 //===----------------------------------------------------------------------===//
1853 //===----------------------------------------------------------------------===//
1855 // CND*_INT Pattterns for f32 True / False values
1857 class CND_INT_f32 <InstR600 cnd, CondCode cc> : Pat <
1858 (selectcc (i32 R600_Reg32:$src0), 0, (f32 R600_Reg32:$src1),
1859 R600_Reg32:$src2, cc),
1860 (cnd R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2)
1863 def : CND_INT_f32 <CNDE_INT, SETEQ>;
1864 def : CND_INT_f32 <CNDGT_INT, SETGT>;
1865 def : CND_INT_f32 <CNDGE_INT, SETGE>;
1867 //CNDGE_INT extra pattern
1869 (selectcc (i32 R600_Reg32:$src0), -1, (i32 R600_Reg32:$src1),
1870 (i32 R600_Reg32:$src2), COND_GT),
1871 (CNDGE_INT R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2)
1877 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
1881 (int_AMDGPU_kill R600_Reg32:$src0),
1882 (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
1887 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT),
1888 (SGT R600_Reg32:$src1, R600_Reg32:$src0)
1893 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LE),
1894 (SGE R600_Reg32:$src1, R600_Reg32:$src0)
1897 // SETGT_DX10 reverse args
1899 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, COND_LT),
1900 (SETGT_DX10 R600_Reg32:$src1, R600_Reg32:$src0)
1903 // SETGE_DX10 reverse args
1905 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, COND_LE),
1906 (SETGE_DX10 R600_Reg32:$src1, R600_Reg32:$src0)
1909 // SETGT_INT reverse args
1911 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT),
1912 (SETGT_INT R600_Reg32:$src1, R600_Reg32:$src0)
1915 // SETGE_INT reverse args
1917 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLE),
1918 (SETGE_INT R600_Reg32:$src1, R600_Reg32:$src0)
1921 // SETGT_UINT reverse args
1923 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT),
1924 (SETGT_UINT R600_Reg32:$src1, R600_Reg32:$src0)
1927 // SETGE_UINT reverse args
1929 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULE),
1930 (SETGE_UINT R600_Reg32:$src1, R600_Reg32:$src0)
1933 // The next two patterns are special cases for handling 'true if ordered' and
1934 // 'true if unordered' conditionals. The assumption here is that the behavior of
1935 // SETE and SNE conforms to the Direct3D 10 rules for floating point values
1937 // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit
1938 // We assume that SETE returns false when one of the operands is NAN and
1939 // SNE returns true when on of the operands is NAN
1941 //SETE - 'true if ordered'
1943 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO),
1944 (SETE R600_Reg32:$src0, R600_Reg32:$src1)
1947 //SETE_DX10 - 'true if ordered'
1949 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETO),
1950 (SETE_DX10 R600_Reg32:$src0, R600_Reg32:$src1)
1953 //SNE - 'true if unordered'
1955 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETUO),
1956 (SNE R600_Reg32:$src0, R600_Reg32:$src1)
1959 //SETNE_DX10 - 'true if ordered'
1961 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUO),
1962 (SETNE_DX10 R600_Reg32:$src0, R600_Reg32:$src1)
1965 def : Extract_Element <f32, v4f32, R600_Reg128, 0, sub0>;
1966 def : Extract_Element <f32, v4f32, R600_Reg128, 1, sub1>;
1967 def : Extract_Element <f32, v4f32, R600_Reg128, 2, sub2>;
1968 def : Extract_Element <f32, v4f32, R600_Reg128, 3, sub3>;
1970 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 0, sub0>;
1971 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 1, sub1>;
1972 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 2, sub2>;
1973 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 3, sub3>;
1975 def : Extract_Element <i32, v4i32, R600_Reg128, 0, sub0>;
1976 def : Extract_Element <i32, v4i32, R600_Reg128, 1, sub1>;
1977 def : Extract_Element <i32, v4i32, R600_Reg128, 2, sub2>;
1978 def : Extract_Element <i32, v4i32, R600_Reg128, 3, sub3>;
1980 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 0, sub0>;
1981 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 1, sub1>;
1982 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 2, sub2>;
1983 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 3, sub3>;
1985 def : Vector4_Build <v4f32, R600_Reg128, f32, R600_Reg32>;
1986 def : Vector4_Build <v4i32, R600_Reg128, i32, R600_Reg32>;
1988 // bitconvert patterns
1990 def : BitConvert <i32, f32, R600_Reg32>;
1991 def : BitConvert <f32, i32, R600_Reg32>;
1992 def : BitConvert <v4f32, v4i32, R600_Reg128>;
1993 def : BitConvert <v4i32, v4f32, R600_Reg128>;
1995 // DWORDADDR pattern
1996 def : DwordAddrPat <i32, R600_Reg32>;
1998 } // End isR600toCayman Predicate