1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // R600 Tablegen instruction definitions
12 //===----------------------------------------------------------------------===//
14 include "R600Intrinsics.td"
15 include "R600InstrFormats.td"
17 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
18 InstR600 <outs, ins, asm, pattern, NullALU> {
20 let Namespace = "AMDGPU";
23 def MEMxi : Operand<iPTR> {
24 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
25 let PrintMethod = "printMemOperand";
28 def MEMrr : Operand<iPTR> {
29 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
32 // Operands for non-registers
34 class InstFlag<string PM = "printOperand", int Default = 0>
35 : OperandWithDefaultOps <i32, (ops (i32 Default))> {
39 // src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers
40 def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> {
41 let PrintMethod = "printSel";
43 def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> {
44 let PrintMethod = "printBankSwizzle";
47 def LITERAL : InstFlag<"printLiteral">;
49 def WRITE : InstFlag <"printWrite", 1>;
50 def OMOD : InstFlag <"printOMOD">;
51 def REL : InstFlag <"printRel">;
52 def CLAMP : InstFlag <"printClamp">;
53 def NEG : InstFlag <"printNeg">;
54 def ABS : InstFlag <"printAbs">;
55 def UEM : InstFlag <"printUpdateExecMask">;
56 def UP : InstFlag <"printUpdatePred">;
58 // XXX: The r600g finalizer in Mesa expects last to be one in most cases.
59 // Once we start using the packetizer in this backend we should have this
61 def LAST : InstFlag<"printLast", 1>;
62 def RSel : Operand<i32> {
63 let PrintMethod = "printRSel";
65 def CT: Operand<i32> {
66 let PrintMethod = "printCT";
69 def FRAMEri : Operand<iPTR> {
70 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index);
73 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
74 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
75 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
76 def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>;
77 def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>;
78 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
81 def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
85 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
87 // Class for instructions with only one source register.
88 // If you add new ins to this instruction, make sure they are listed before
89 // $literal, because the backend currently assumes that the last operand is
90 // a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in
91 // R600Defines.h, R600InstrInfo::buildDefaultInstruction(),
92 // and R600InstrInfo::getOperandIdx().
93 class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
94 InstrItinClass itin = AnyALU> :
95 InstR600 <(outs R600_Reg32:$dst),
96 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
97 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
98 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
99 BANK_SWIZZLE:$bank_swizzle),
100 !strconcat(" ", opName,
101 "$clamp $last $dst$write$dst_rel$omod, "
102 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
103 "$pred_sel $bank_swizzle"),
107 R600ALU_Word1_OP2 <inst> {
113 let update_exec_mask = 0;
115 let HasNativeOperands = 1;
118 let DisableEncoding = "$literal";
119 let UseNamedOperandTable = 1;
121 let Inst{31-0} = Word0;
122 let Inst{63-32} = Word1;
125 class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
126 InstrItinClass itin = AnyALU> :
127 R600_1OP <inst, opName,
128 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))]
131 // If you add or change the operands for R600_2OP instructions, you must
132 // also update the R600Op2OperandIndex::ROI enum in R600Defines.h,
133 // R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx().
134 class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
135 InstrItinClass itin = AnyALU> :
136 InstR600 <(outs R600_Reg32:$dst),
137 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
138 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
139 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
140 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
141 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
142 BANK_SWIZZLE:$bank_swizzle),
143 !strconcat(" ", opName,
144 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
145 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
146 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
147 "$pred_sel $bank_swizzle"),
151 R600ALU_Word1_OP2 <inst> {
153 let HasNativeOperands = 1;
156 let DisableEncoding = "$literal";
157 let UseNamedOperandTable = 1;
159 let Inst{31-0} = Word0;
160 let Inst{63-32} = Word1;
163 class R600_2OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
164 InstrItinClass itim = AnyALU> :
165 R600_2OP <inst, opName,
166 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
170 // If you add our change the operands for R600_3OP instructions, you must
171 // also update the R600Op3OperandIndex::ROI enum in R600Defines.h,
172 // R600InstrInfo::buildDefaultInstruction(), and
173 // R600InstrInfo::getOperandIdx().
174 class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
175 InstrItinClass itin = AnyALU> :
176 InstR600 <(outs R600_Reg32:$dst),
177 (ins REL:$dst_rel, CLAMP:$clamp,
178 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
179 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
180 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,
181 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
182 BANK_SWIZZLE:$bank_swizzle),
183 !strconcat(" ", opName, "$clamp $last $dst$dst_rel, "
184 "$src0_neg$src0$src0_rel, "
185 "$src1_neg$src1$src1_rel, "
186 "$src2_neg$src2$src2_rel, "
192 R600ALU_Word1_OP3<inst>{
194 let HasNativeOperands = 1;
195 let DisableEncoding = "$literal";
197 let UseNamedOperandTable = 1;
200 let Inst{31-0} = Word0;
201 let Inst{63-32} = Word1;
204 class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern,
205 InstrItinClass itin = VecALU> :
206 InstR600 <(outs R600_Reg32:$dst),
214 } // End mayLoad = 1, mayStore = 0, hasSideEffects = 0
216 def TEX_SHADOW : PatLeaf<
218 [{uint32_t TType = (uint32_t)N->getZExtValue();
219 return (TType >= 6 && TType <= 8) || (TType >= 11 && TType <= 13);
223 def TEX_RECT : PatLeaf<
225 [{uint32_t TType = (uint32_t)N->getZExtValue();
230 def TEX_ARRAY : PatLeaf<
232 [{uint32_t TType = (uint32_t)N->getZExtValue();
233 return TType == 9 || TType == 10 || TType == 15 || TType == 16;
237 def TEX_SHADOW_ARRAY : PatLeaf<
239 [{uint32_t TType = (uint32_t)N->getZExtValue();
240 return TType == 11 || TType == 12 || TType == 17;
244 class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> mask, dag outs,
245 dag ins, string asm, list<dag> pattern> :
246 InstR600ISA <outs, ins, asm, pattern>,
247 CF_ALLOC_EXPORT_WORD0_RAT, CF_ALLOC_EXPORT_WORD1_BUF {
250 let rat_inst = ratinst;
252 // XXX: Have a separate instruction for non-indexed writes.
258 let comp_mask = mask;
261 let cf_inst = cfinst;
265 let Inst{31-0} = Word0;
266 let Inst{63-32} = Word1;
270 class VTX_READ <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
271 : InstR600ISA <outs, (ins MEMxi:$src_gpr), name, pattern>,
276 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,
277 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,
278 // however, based on my testing if USE_CONST_FIELDS is set, then all
279 // these fields need to be set to 0.
280 let USE_CONST_FIELDS = 0;
281 let NUM_FORMAT_ALL = 1;
282 let FORMAT_COMP_ALL = 0;
283 let SRF_MODE_ALL = 0;
285 let Inst{63-32} = Word1;
286 // LLVM can only encode 64-bit instructions, so these fields are manually
287 // encoded in R600CodeEmitter
290 // bits<2> ENDIAN_SWAP = 0;
291 // bits<1> CONST_BUF_NO_STRIDE = 0;
292 // bits<1> MEGA_FETCH = 0;
293 // bits<1> ALT_CONST = 0;
294 // bits<2> BUFFER_INDEX_MODE = 0;
296 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
297 // is done in R600CodeEmitter
299 // Inst{79-64} = OFFSET;
300 // Inst{81-80} = ENDIAN_SWAP;
301 // Inst{82} = CONST_BUF_NO_STRIDE;
302 // Inst{83} = MEGA_FETCH;
303 // Inst{84} = ALT_CONST;
304 // Inst{86-85} = BUFFER_INDEX_MODE;
305 // Inst{95-86} = 0; Reserved
307 // VTX_WORD3 (Padding)
314 class LoadParamFrag <PatFrag load_type> : PatFrag <
315 (ops node:$ptr), (load_type node:$ptr),
316 [{ return isParamLoad(dyn_cast<LoadSDNode>(N)); }]
319 def load_param : LoadParamFrag<load>;
320 def load_param_zexti8 : LoadParamFrag<zextloadi8>;
321 def load_param_zexti16 : LoadParamFrag<zextloadi16>;
323 def isR600 : Predicate<"Subtarget.getGeneration() <= AMDGPUSubtarget::R700">;
324 def isR700 : Predicate<"Subtarget.getGeneration() == AMDGPUSubtarget::R700">;
325 def isEG : Predicate<
326 "Subtarget.getGeneration() >= AMDGPUSubtarget::EVERGREEN && "
327 "Subtarget.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && "
328 "!Subtarget.hasCaymanISA()">;
330 def isCayman : Predicate<"Subtarget.hasCaymanISA()">;
331 def isEGorCayman : Predicate<"Subtarget.getGeneration() == "
332 "AMDGPUSubtarget::EVERGREEN"
333 "|| Subtarget.getGeneration() =="
334 "AMDGPUSubtarget::NORTHERN_ISLANDS">;
336 def isR600toCayman : Predicate<
337 "Subtarget.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS">;
339 //===----------------------------------------------------------------------===//
341 //===----------------------------------------------------------------------===//
343 def INTERP_PAIR_XY : AMDGPUShaderInst <
344 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1),
345 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
346 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
349 def INTERP_PAIR_ZW : AMDGPUShaderInst <
350 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1),
351 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
352 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",
355 def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS",
356 SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>,
360 def DOT4 : SDNode<"AMDGPUISD::DOT4",
361 SDTypeProfile<1, 8, [SDTCisFP<0>, SDTCisVT<1, f32>, SDTCisVT<2, f32>,
362 SDTCisVT<3, f32>, SDTCisVT<4, f32>, SDTCisVT<5, f32>,
363 SDTCisVT<6, f32>, SDTCisVT<7, f32>, SDTCisVT<8, f32>]>,
367 def TEXTURE_FETCH_Type : SDTypeProfile<1, 19, [SDTCisFP<0>]>;
369 def TEXTURE_FETCH: SDNode<"AMDGPUISD::TEXTURE_FETCH", TEXTURE_FETCH_Type, []>;
371 multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> {
372 def : Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR,
373 (i32 imm:$srcx), (i32 imm:$srcy), (i32 imm:$srcz), (i32 imm:$srcw),
374 (i32 imm:$offsetx), (i32 imm:$offsety), (i32 imm:$offsetz),
375 (i32 imm:$DST_SEL_X), (i32 imm:$DST_SEL_Y), (i32 imm:$DST_SEL_Z),
376 (i32 imm:$DST_SEL_W),
377 (i32 imm:$RESOURCE_ID), (i32 imm:$SAMPLER_ID),
378 (i32 imm:$COORD_TYPE_X), (i32 imm:$COORD_TYPE_Y), (i32 imm:$COORD_TYPE_Z),
379 (i32 imm:$COORD_TYPE_W)),
380 (inst R600_Reg128:$SRC_GPR,
381 imm:$srcx, imm:$srcy, imm:$srcz, imm:$srcw,
382 imm:$offsetx, imm:$offsety, imm:$offsetz,
383 imm:$DST_SEL_X, imm:$DST_SEL_Y, imm:$DST_SEL_Z,
385 imm:$RESOURCE_ID, imm:$SAMPLER_ID,
386 imm:$COORD_TYPE_X, imm:$COORD_TYPE_Y, imm:$COORD_TYPE_Z,
390 //===----------------------------------------------------------------------===//
391 // Interpolation Instructions
392 //===----------------------------------------------------------------------===//
394 def INTERP_VEC_LOAD : AMDGPUShaderInst <
395 (outs R600_Reg128:$dst),
397 "INTERP_LOAD $src0 : $dst",
400 def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> {
401 let bank_swizzle = 5;
404 def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> {
405 let bank_swizzle = 5;
408 def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>;
410 //===----------------------------------------------------------------------===//
411 // Export Instructions
412 //===----------------------------------------------------------------------===//
414 def ExportType : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
416 def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType,
417 [SDNPHasChain, SDNPSideEffect]>;
420 field bits<32> Word0;
427 let Word0{12-0} = arraybase;
428 let Word0{14-13} = type;
429 let Word0{21-15} = gpr;
430 let Word0{22} = 0; // RW_REL
431 let Word0{29-23} = 0; // INDEX_GPR
432 let Word0{31-30} = elem_size;
435 class ExportSwzWord1 {
436 field bits<32> Word1;
445 let Word1{2-0} = sw_x;
446 let Word1{5-3} = sw_y;
447 let Word1{8-6} = sw_z;
448 let Word1{11-9} = sw_w;
451 class ExportBufWord1 {
452 field bits<32> Word1;
459 let Word1{11-0} = arraySize;
460 let Word1{15-12} = compMask;
463 multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
464 def : Pat<(int_R600_store_pixel_depth R600_Reg32:$reg),
466 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
467 0, 61, 0, 7, 7, 7, cf_inst, 0)
470 def : Pat<(int_R600_store_pixel_stencil R600_Reg32:$reg),
472 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
473 0, 61, 7, 0, 7, 7, cf_inst, 0)
476 def : Pat<(int_R600_store_dummy (i32 imm:$type)),
478 (v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0)
481 def : Pat<(int_R600_store_dummy 1),
483 (v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0)
486 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
487 (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)),
488 (ExportInst R600_Reg128:$src, imm:$type, imm:$base,
489 imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0)
494 multiclass SteamOutputExportPattern<Instruction ExportInst,
495 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> {
497 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
498 (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)),
499 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
500 4095, imm:$mask, buf0inst, 0)>;
502 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
503 (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)),
504 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
505 4095, imm:$mask, buf1inst, 0)>;
507 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
508 (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)),
509 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
510 4095, imm:$mask, buf2inst, 0)>;
512 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
513 (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)),
514 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
515 4095, imm:$mask, buf3inst, 0)>;
518 // Export Instructions should not be duplicated by TailDuplication pass
519 // (which assumes that duplicable instruction are affected by exec mask)
520 let usesCustomInserter = 1, isNotDuplicable = 1 in {
522 class ExportSwzInst : InstR600ISA<(
524 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
525 i32imm:$sw_x, i32imm:$sw_y, i32imm:$sw_z, i32imm:$sw_w, i32imm:$inst,
527 !strconcat("EXPORT", " $gpr"),
528 []>, ExportWord0, ExportSwzWord1 {
530 let Inst{31-0} = Word0;
531 let Inst{63-32} = Word1;
534 } // End usesCustomInserter = 1
536 class ExportBufInst : InstR600ISA<(
538 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
539 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop),
540 !strconcat("EXPORT", " $gpr"),
541 []>, ExportWord0, ExportBufWord1 {
543 let Inst{31-0} = Word0;
544 let Inst{63-32} = Word1;
547 //===----------------------------------------------------------------------===//
548 // Control Flow Instructions
549 //===----------------------------------------------------------------------===//
552 def KCACHE : InstFlag<"printKCache">;
554 class ALU_CLAUSE<bits<4> inst, string OpName> : AMDGPUInst <(outs),
555 (ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1,
556 KCACHE:$KCACHE_MODE0, KCACHE:$KCACHE_MODE1,
557 i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1,
559 !strconcat(OpName, " $COUNT, @$ADDR, "
560 "KC0[$KCACHE_MODE0], KC1[$KCACHE_MODE1]"),
561 [] >, CF_ALU_WORD0, CF_ALU_WORD1 {
566 let WHOLE_QUAD_MODE = 0;
569 let Inst{31-0} = Word0;
570 let Inst{63-32} = Word1;
573 class CF_WORD0_R600 {
574 field bits<32> Word0;
581 class CF_CLAUSE_R600 <bits<7> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
582 ins, AsmPrint, [] >, CF_WORD0_R600, CF_WORD1_R600 {
589 let VALID_PIXEL_MODE = 0;
591 let COUNT = CNT{2-0};
593 let COUNT_3 = CNT{3};
594 let END_OF_PROGRAM = 0;
595 let WHOLE_QUAD_MODE = 0;
597 let Inst{31-0} = Word0;
598 let Inst{63-32} = Word1;
601 class CF_CLAUSE_EG <bits<8> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
602 ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG {
607 let JUMPTABLE_SEL = 0;
609 let VALID_PIXEL_MODE = 0;
611 let END_OF_PROGRAM = 0;
613 let Inst{31-0} = Word0;
614 let Inst{63-32} = Word1;
617 def CF_ALU : ALU_CLAUSE<8, "ALU">;
618 def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">;
620 def FETCH_CLAUSE : AMDGPUInst <(outs),
621 (ins i32imm:$addr), "Fetch clause starting at $addr:", [] > {
627 def ALU_CLAUSE : AMDGPUInst <(outs),
628 (ins i32imm:$addr), "ALU clause starting at $addr:", [] > {
634 def LITERALS : AMDGPUInst <(outs),
635 (ins LITERAL:$literal1, LITERAL:$literal2), "$literal1, $literal2", [] > {
640 let Inst{31-0} = literal1;
641 let Inst{63-32} = literal2;
644 def PAD : AMDGPUInst <(outs), (ins), "PAD", [] > {
648 let Predicates = [isR600toCayman] in {
650 //===----------------------------------------------------------------------===//
651 // Common Instructions R600, R700, Evergreen, Cayman
652 //===----------------------------------------------------------------------===//
654 def ADD : R600_2OP_Helper <0x0, "ADD", fadd>;
655 // Non-IEEE MUL: 0 * anything = 0
656 def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE", int_AMDGPU_mul>;
657 def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>;
658 def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax>;
659 def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin>;
661 // For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
662 // so some of the instruction names don't match the asm string.
663 // XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
664 def SETE : R600_2OP <
666 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_EQ))]
671 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_GT))]
676 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_GE))]
681 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_NE))]
684 def SETE_DX10 : R600_2OP <
686 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_EQ))]
689 def SETGT_DX10 : R600_2OP <
691 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_GT))]
694 def SETGE_DX10 : R600_2OP <
696 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_GE))]
699 def SETNE_DX10 : R600_2OP <
701 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_NE))]
704 def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>;
705 def TRUNC : R600_1OP_Helper <0x11, "TRUNC", int_AMDGPU_trunc>;
706 def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;
707 def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>;
708 def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>;
710 def MOV : R600_1OP <0x19, "MOV", []>;
712 let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in {
714 class MOV_IMM <ValueType vt, Operand immType> : AMDGPUInst <
715 (outs R600_Reg32:$dst),
721 } // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1
723 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
726 (MOV_IMM_I32 imm:$val)
729 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
732 (MOV_IMM_F32 fpimm:$val)
735 def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>;
736 def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>;
737 def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>;
738 def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>;
740 let hasSideEffects = 1 in {
742 def KILLGT : R600_2OP <0x2D, "KILLGT", []>;
744 } // end hasSideEffects
746 def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>;
747 def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>;
748 def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>;
749 def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>;
750 def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>;
751 def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>;
752 def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", AMDGPUsmax>;
753 def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", AMDGPUsmin>;
754 def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", AMDGPUumax>;
755 def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", AMDGPUumin>;
757 def SETE_INT : R600_2OP <
759 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETEQ))]
762 def SETGT_INT : R600_2OP <
764 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGT))]
767 def SETGE_INT : R600_2OP <
769 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))]
772 def SETNE_INT : R600_2OP <
774 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETNE))]
777 def SETGT_UINT : R600_2OP <
779 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGT))]
782 def SETGE_UINT : R600_2OP <
784 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGE))]
787 def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>;
788 def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>;
789 def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>;
790 def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>;
792 def CNDE_INT : R600_3OP <
794 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_EQ))]
797 def CNDGE_INT : R600_3OP <
799 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_GE))]
802 def CNDGT_INT : R600_3OP <
804 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_GT))]
807 //===----------------------------------------------------------------------===//
808 // Texture instructions
809 //===----------------------------------------------------------------------===//
811 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
813 class R600_TEX <bits<11> inst, string opName> :
814 InstR600 <(outs R600_Reg128:$DST_GPR),
815 (ins R600_Reg128:$SRC_GPR,
816 RSel:$srcx, RSel:$srcy, RSel:$srcz, RSel:$srcw,
817 i32imm:$offsetx, i32imm:$offsety, i32imm:$offsetz,
818 RSel:$DST_SEL_X, RSel:$DST_SEL_Y, RSel:$DST_SEL_Z, RSel:$DST_SEL_W,
819 i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID,
820 CT:$COORD_TYPE_X, CT:$COORD_TYPE_Y, CT:$COORD_TYPE_Z,
823 " $DST_GPR.$DST_SEL_X$DST_SEL_Y$DST_SEL_Z$DST_SEL_W, "
824 "$SRC_GPR.$srcx$srcy$srcz$srcw "
825 "RID:$RESOURCE_ID SID:$SAMPLER_ID "
826 "CT:$COORD_TYPE_X$COORD_TYPE_Y$COORD_TYPE_Z$COORD_TYPE_W"),
828 NullALU>, TEX_WORD0, TEX_WORD1, TEX_WORD2 {
829 let Inst{31-0} = Word0;
830 let Inst{63-32} = Word1;
832 let TEX_INST = inst{4-0};
838 let FETCH_WHOLE_QUAD = 0;
840 let SAMPLER_INDEX_MODE = 0;
841 let RESOURCE_INDEX_MODE = 0;
846 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
850 def TEX_SAMPLE : R600_TEX <0x10, "TEX_SAMPLE">;
851 def TEX_SAMPLE_C : R600_TEX <0x18, "TEX_SAMPLE_C">;
852 def TEX_SAMPLE_L : R600_TEX <0x11, "TEX_SAMPLE_L">;
853 def TEX_SAMPLE_C_L : R600_TEX <0x19, "TEX_SAMPLE_C_L">;
854 def TEX_SAMPLE_LB : R600_TEX <0x12, "TEX_SAMPLE_LB">;
855 def TEX_SAMPLE_C_LB : R600_TEX <0x1A, "TEX_SAMPLE_C_LB">;
856 def TEX_LD : R600_TEX <0x03, "TEX_LD">;
857 def TEX_GET_TEXTURE_RESINFO : R600_TEX <0x04, "TEX_GET_TEXTURE_RESINFO">;
858 def TEX_GET_GRADIENTS_H : R600_TEX <0x07, "TEX_GET_GRADIENTS_H">;
859 def TEX_GET_GRADIENTS_V : R600_TEX <0x08, "TEX_GET_GRADIENTS_V">;
860 def TEX_SET_GRADIENTS_H : R600_TEX <0x0B, "TEX_SET_GRADIENTS_H">;
861 def TEX_SET_GRADIENTS_V : R600_TEX <0x0C, "TEX_SET_GRADIENTS_V">;
862 def TEX_SAMPLE_G : R600_TEX <0x14, "TEX_SAMPLE_G">;
863 def TEX_SAMPLE_C_G : R600_TEX <0x1C, "TEX_SAMPLE_C_G">;
865 defm : TexPattern<0, TEX_SAMPLE>;
866 defm : TexPattern<1, TEX_SAMPLE_C>;
867 defm : TexPattern<2, TEX_SAMPLE_L>;
868 defm : TexPattern<3, TEX_SAMPLE_C_L>;
869 defm : TexPattern<4, TEX_SAMPLE_LB>;
870 defm : TexPattern<5, TEX_SAMPLE_C_LB>;
871 defm : TexPattern<6, TEX_LD, v4i32>;
872 defm : TexPattern<7, TEX_GET_TEXTURE_RESINFO, v4i32>;
873 defm : TexPattern<8, TEX_GET_GRADIENTS_H>;
874 defm : TexPattern<9, TEX_GET_GRADIENTS_V>;
876 //===----------------------------------------------------------------------===//
877 // Helper classes for common instructions
878 //===----------------------------------------------------------------------===//
880 class MUL_LIT_Common <bits<5> inst> : R600_3OP <
885 class MULADD_Common <bits<5> inst> : R600_3OP <
890 class MULADD_IEEE_Common <bits<5> inst> : R600_3OP <
892 [(set f32:$dst, (fadd (fmul f32:$src0, f32:$src1), f32:$src2))]
895 class CNDE_Common <bits<5> inst> : R600_3OP <
897 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_EQ))]
900 class CNDGT_Common <bits<5> inst> : R600_3OP <
902 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_GT))]
905 class CNDGE_Common <bits<5> inst> : R600_3OP <
907 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_GE))]
911 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
912 class R600_VEC2OP<list<dag> pattern> : InstR600 <(outs R600_Reg32:$dst), (ins
914 UEM:$update_exec_mask_X, UP:$update_pred_X, WRITE:$write_X,
915 OMOD:$omod_X, REL:$dst_rel_X, CLAMP:$clamp_X,
916 R600_TReg32_X:$src0_X, NEG:$src0_neg_X, REL:$src0_rel_X, ABS:$src0_abs_X, SEL:$src0_sel_X,
917 R600_TReg32_X:$src1_X, NEG:$src1_neg_X, REL:$src1_rel_X, ABS:$src1_abs_X, SEL:$src1_sel_X,
918 R600_Pred:$pred_sel_X,
920 UEM:$update_exec_mask_Y, UP:$update_pred_Y, WRITE:$write_Y,
921 OMOD:$omod_Y, REL:$dst_rel_Y, CLAMP:$clamp_Y,
922 R600_TReg32_Y:$src0_Y, NEG:$src0_neg_Y, REL:$src0_rel_Y, ABS:$src0_abs_Y, SEL:$src0_sel_Y,
923 R600_TReg32_Y:$src1_Y, NEG:$src1_neg_Y, REL:$src1_rel_Y, ABS:$src1_abs_Y, SEL:$src1_sel_Y,
924 R600_Pred:$pred_sel_Y,
926 UEM:$update_exec_mask_Z, UP:$update_pred_Z, WRITE:$write_Z,
927 OMOD:$omod_Z, REL:$dst_rel_Z, CLAMP:$clamp_Z,
928 R600_TReg32_Z:$src0_Z, NEG:$src0_neg_Z, REL:$src0_rel_Z, ABS:$src0_abs_Z, SEL:$src0_sel_Z,
929 R600_TReg32_Z:$src1_Z, NEG:$src1_neg_Z, REL:$src1_rel_Z, ABS:$src1_abs_Z, SEL:$src1_sel_Z,
930 R600_Pred:$pred_sel_Z,
932 UEM:$update_exec_mask_W, UP:$update_pred_W, WRITE:$write_W,
933 OMOD:$omod_W, REL:$dst_rel_W, CLAMP:$clamp_W,
934 R600_TReg32_W:$src0_W, NEG:$src0_neg_W, REL:$src0_rel_W, ABS:$src0_abs_W, SEL:$src0_sel_W,
935 R600_TReg32_W:$src1_W, NEG:$src1_neg_W, REL:$src1_rel_W, ABS:$src1_abs_W, SEL:$src1_sel_W,
936 R600_Pred:$pred_sel_W,
937 LITERAL:$literal0, LITERAL:$literal1),
942 let UseNamedOperandTable = 1;
947 def DOT_4 : R600_VEC2OP<[(set R600_Reg32:$dst, (DOT4
948 R600_TReg32_X:$src0_X, R600_TReg32_X:$src1_X,
949 R600_TReg32_Y:$src0_Y, R600_TReg32_Y:$src1_Y,
950 R600_TReg32_Z:$src0_Z, R600_TReg32_Z:$src1_Z,
951 R600_TReg32_W:$src0_W, R600_TReg32_W:$src1_W))]>;
954 class DOT4_Common <bits<11> inst> : R600_2OP <inst, "DOT4", []>;
957 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
958 multiclass CUBE_Common <bits<11> inst> {
960 def _pseudo : InstR600 <
961 (outs R600_Reg128:$dst),
962 (ins R600_Reg128:$src0),
964 [(set v4f32:$dst, (int_AMDGPU_cube v4f32:$src0))],
968 let UseNamedOperandTable = 1;
971 def _real : R600_2OP <inst, "CUBE", []>;
973 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
975 class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
976 inst, "EXP_IEEE", fexp2
979 let Itinerary = TransALU;
982 class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper <
983 inst, "FLT_TO_INT", fp_to_sint
986 let Itinerary = TransALU;
989 class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
990 inst, "INT_TO_FLT", sint_to_fp
993 let Itinerary = TransALU;
996 class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper <
997 inst, "FLT_TO_UINT", fp_to_uint
1000 let Itinerary = TransALU;
1003 class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1004 inst, "UINT_TO_FLT", uint_to_fp
1007 let Itinerary = TransALU;
1010 class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <
1011 inst, "LOG_CLAMPED", []
1014 class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1015 inst, "LOG_IEEE", flog2
1018 let Itinerary = TransALU;
1021 class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>;
1022 class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>;
1023 class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>;
1024 class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper <
1025 inst, "MULHI_INT", mulhs
1028 let Itinerary = TransALU;
1030 class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper <
1031 inst, "MULHI", mulhu
1034 let Itinerary = TransALU;
1036 class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper <
1037 inst, "MULLO_INT", mul
1040 let Itinerary = TransALU;
1042 class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []> {
1044 let Itinerary = TransALU;
1047 class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <
1048 inst, "RECIP_CLAMPED", []
1051 let Itinerary = TransALU;
1054 class RECIP_IEEE_Common <bits<11> inst> : R600_1OP <
1055 inst, "RECIP_IEEE", [(set f32:$dst, (fdiv FP_ONE, f32:$src0))]
1058 let Itinerary = TransALU;
1061 class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1062 inst, "RECIP_UINT", AMDGPUurecip
1065 let Itinerary = TransALU;
1068 class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper <
1069 inst, "RECIPSQRT_CLAMPED", int_AMDGPU_rsq
1072 let Itinerary = TransALU;
1075 class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP <
1076 inst, "RECIPSQRT_IEEE", []
1079 let Itinerary = TransALU;
1082 class SIN_Common <bits<11> inst> : R600_1OP <
1086 let Itinerary = TransALU;
1089 class COS_Common <bits<11> inst> : R600_1OP <
1093 let Itinerary = TransALU;
1096 //===----------------------------------------------------------------------===//
1097 // Helper patterns for complex intrinsics
1098 //===----------------------------------------------------------------------===//
1100 multiclass DIV_Common <InstR600 recip_ieee> {
1102 (int_AMDGPU_div f32:$src0, f32:$src1),
1103 (MUL_IEEE $src0, (recip_ieee $src1))
1107 (fdiv f32:$src0, f32:$src1),
1108 (MUL_IEEE $src0, (recip_ieee $src1))
1112 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee>
1114 (int_TGSI_lit_z f32:$src_x, f32:$src_y, f32:$src_w),
1115 (exp_ieee (mul_lit (log_clamped (MAX $src_y, (f32 ZERO))), $src_w, $src_x))
1118 //===----------------------------------------------------------------------===//
1119 // R600 / R700 Instructions
1120 //===----------------------------------------------------------------------===//
1122 let Predicates = [isR600] in {
1124 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
1125 def MULADD_r600 : MULADD_Common<0x10>;
1126 def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>;
1127 def CNDE_r600 : CNDE_Common<0x18>;
1128 def CNDGT_r600 : CNDGT_Common<0x19>;
1129 def CNDGE_r600 : CNDGE_Common<0x1A>;
1130 def DOT4_r600 : DOT4_Common<0x50>;
1131 defm CUBE_r600 : CUBE_Common<0x52>;
1132 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
1133 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
1134 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
1135 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
1136 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
1137 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
1138 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
1139 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
1140 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
1141 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
1142 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
1143 def SIN_r600 : SIN_Common<0x6E>;
1144 def COS_r600 : COS_Common<0x6F>;
1145 def ASHR_r600 : ASHR_Common<0x70>;
1146 def LSHR_r600 : LSHR_Common<0x71>;
1147 def LSHL_r600 : LSHL_Common<0x72>;
1148 def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
1149 def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
1150 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
1151 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
1152 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
1154 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
1155 def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL>;
1156 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
1158 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>;
1160 def R600_ExportSwz : ExportSwzInst {
1161 let Word1{20-17} = 0; // BURST_COUNT
1162 let Word1{21} = eop;
1163 let Word1{22} = 1; // VALID_PIXEL_MODE
1164 let Word1{30-23} = inst;
1165 let Word1{31} = 1; // BARRIER
1167 defm : ExportPattern<R600_ExportSwz, 39>;
1169 def R600_ExportBuf : ExportBufInst {
1170 let Word1{20-17} = 0; // BURST_COUNT
1171 let Word1{21} = eop;
1172 let Word1{22} = 1; // VALID_PIXEL_MODE
1173 let Word1{30-23} = inst;
1174 let Word1{31} = 1; // BARRIER
1176 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>;
1178 def CF_TC_R600 : CF_CLAUSE_R600<1, (ins i32imm:$ADDR, i32imm:$CNT),
1179 "TEX $CNT @$ADDR"> {
1182 def CF_VC_R600 : CF_CLAUSE_R600<2, (ins i32imm:$ADDR, i32imm:$CNT),
1183 "VTX $CNT @$ADDR"> {
1186 def WHILE_LOOP_R600 : CF_CLAUSE_R600<6, (ins i32imm:$ADDR),
1187 "LOOP_START_DX10 @$ADDR"> {
1191 def END_LOOP_R600 : CF_CLAUSE_R600<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1195 def LOOP_BREAK_R600 : CF_CLAUSE_R600<9, (ins i32imm:$ADDR),
1196 "LOOP_BREAK @$ADDR"> {
1200 def CF_CONTINUE_R600 : CF_CLAUSE_R600<8, (ins i32imm:$ADDR),
1201 "CONTINUE @$ADDR"> {
1205 def CF_JUMP_R600 : CF_CLAUSE_R600<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1206 "JUMP @$ADDR POP:$POP_COUNT"> {
1209 def CF_ELSE_R600 : CF_CLAUSE_R600<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1210 "ELSE @$ADDR POP:$POP_COUNT"> {
1213 def CF_CALL_FS_R600 : CF_CLAUSE_R600<19, (ins), "CALL_FS"> {
1218 def POP_R600 : CF_CLAUSE_R600<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1219 "POP @$ADDR POP:$POP_COUNT"> {
1222 def CF_END_R600 : CF_CLAUSE_R600<0, (ins), "CF_END"> {
1226 let END_OF_PROGRAM = 1;
1231 // Helper pattern for normalizing inputs to triginomic instructions for R700+
1233 class COS_PAT <InstR600 trig> : Pat<
1235 (trig (MUL_IEEE (MOV_IMM_I32 CONST.TWO_PI_INV), $src))
1238 class SIN_PAT <InstR600 trig> : Pat<
1240 (trig (MUL_IEEE (MOV_IMM_I32 CONST.TWO_PI_INV), $src))
1243 //===----------------------------------------------------------------------===//
1244 // R700 Only instructions
1245 //===----------------------------------------------------------------------===//
1247 let Predicates = [isR700] in {
1248 def SIN_r700 : SIN_Common<0x6E>;
1249 def COS_r700 : COS_Common<0x6F>;
1251 // R700 normalizes inputs to SIN/COS the same as EG
1252 def : SIN_PAT <SIN_r700>;
1253 def : COS_PAT <COS_r700>;
1256 //===----------------------------------------------------------------------===//
1257 // Evergreen Only instructions
1258 //===----------------------------------------------------------------------===//
1260 let Predicates = [isEG] in {
1262 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
1263 defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
1265 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
1266 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
1267 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
1268 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
1269 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
1270 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
1271 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
1272 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
1273 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
1274 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
1275 def SIN_eg : SIN_Common<0x8D>;
1276 def COS_eg : COS_Common<0x8E>;
1278 def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>;
1279 def : SIN_PAT <SIN_eg>;
1280 def : COS_PAT <COS_eg>;
1281 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>;
1283 //===----------------------------------------------------------------------===//
1284 // Memory read/write instructions
1285 //===----------------------------------------------------------------------===//
1286 let usesCustomInserter = 1 in {
1288 class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> mask, string name,
1290 : EG_CF_RAT <0x57, 0x2, mask, (outs), ins, name, pattern> {
1293 } // End usesCustomInserter = 1
1296 def RAT_WRITE_CACHELESS_32_eg : RAT_WRITE_CACHELESS_eg <
1297 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1298 0x1, "RAT_WRITE_CACHELESS_32_eg $rw_gpr, $index_gpr, $eop",
1299 [(global_store i32:$rw_gpr, i32:$index_gpr)]
1303 def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg <
1304 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1305 0xf, "RAT_WRITE_CACHELESS_128 $rw_gpr.XYZW, $index_gpr, $eop",
1306 [(global_store v4i32:$rw_gpr, i32:$index_gpr)]
1309 class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
1310 : VTX_WORD0_eg, VTX_READ<name, buffer_id, outs, pattern> {
1315 let FETCH_WHOLE_QUAD = 0;
1316 let BUFFER_ID = buffer_id;
1318 // XXX: We can infer this field based on the SRC_GPR. This would allow us
1319 // to store vertex addresses in any channel, not just X.
1322 let Inst{31-0} = Word0;
1325 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
1326 : VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id,
1327 (outs R600_TReg32_X:$dst_gpr), pattern> {
1329 let MEGA_FETCH_COUNT = 1;
1331 let DST_SEL_Y = 7; // Masked
1332 let DST_SEL_Z = 7; // Masked
1333 let DST_SEL_W = 7; // Masked
1334 let DATA_FORMAT = 1; // FMT_8
1337 class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
1338 : VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id,
1339 (outs R600_TReg32_X:$dst_gpr), pattern> {
1340 let MEGA_FETCH_COUNT = 2;
1342 let DST_SEL_Y = 7; // Masked
1343 let DST_SEL_Z = 7; // Masked
1344 let DST_SEL_W = 7; // Masked
1345 let DATA_FORMAT = 5; // FMT_16
1349 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
1350 : VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id,
1351 (outs R600_TReg32_X:$dst_gpr), pattern> {
1353 let MEGA_FETCH_COUNT = 4;
1355 let DST_SEL_Y = 7; // Masked
1356 let DST_SEL_Z = 7; // Masked
1357 let DST_SEL_W = 7; // Masked
1358 let DATA_FORMAT = 0xD; // COLOR_32
1360 // This is not really necessary, but there were some GPU hangs that appeared
1361 // to be caused by ALU instructions in the next instruction group that wrote
1362 // to the $src_gpr registers of the VTX_READ.
1364 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
1365 // %T2_X<def> = MOV %ZERO
1366 //Adding this constraint prevents this from happening.
1367 let Constraints = "$src_gpr.ptr = $dst_gpr";
1370 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
1371 : VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id,
1372 (outs R600_Reg128:$dst_gpr), pattern> {
1374 let MEGA_FETCH_COUNT = 16;
1379 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
1381 // XXX: Need to force VTX_READ_128 instructions to write to the same register
1382 // that holds its buffer address to avoid potential hangs. We can't use
1383 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst
1384 // registers are different sizes.
1387 //===----------------------------------------------------------------------===//
1388 // VTX Read from parameter memory space
1389 //===----------------------------------------------------------------------===//
1391 def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <0,
1392 [(set i32:$dst_gpr, (load_param_zexti8 ADDRVTX_READ:$src_gpr))]
1395 def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <0,
1396 [(set i32:$dst_gpr, (load_param_zexti16 ADDRVTX_READ:$src_gpr))]
1399 def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0,
1400 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1403 def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <0,
1404 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1407 //===----------------------------------------------------------------------===//
1408 // VTX Read from global memory space
1409 //===----------------------------------------------------------------------===//
1412 def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1,
1413 [(set i32:$dst_gpr, (zextloadi8_global ADDRVTX_READ:$src_gpr))]
1417 def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1,
1418 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
1422 def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
1423 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
1426 //===----------------------------------------------------------------------===//
1428 // XXX: We are currently storing all constants in the global address space.
1429 //===----------------------------------------------------------------------===//
1431 def CONSTANT_LOAD_eg : VTX_READ_32_eg <1,
1432 [(set i32:$dst_gpr, (constant_load ADDRVTX_READ:$src_gpr))]
1436 } // End Predicates = [isEG]
1438 //===----------------------------------------------------------------------===//
1439 // Evergreen / Cayman Instructions
1440 //===----------------------------------------------------------------------===//
1442 let Predicates = [isEGorCayman] in {
1444 // BFE_UINT - bit_extract, an optimization for mask and shift
1449 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
1454 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0
1455 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
1456 // (16,8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
1457 // (24,8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
1458 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
1459 [(set i32:$dst, (int_AMDIL_bit_extract_u32 i32:$src0, i32:$src1,
1463 def : BFEPattern <BFE_UINT_eg>;
1465 def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", [], VecALU>;
1466 defm : BFIPatterns <BFI_INT_eg>;
1468 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>;
1469 def : ROTRPattern <BIT_ALIGN_INT_eg>;
1471 def MULADD_eg : MULADD_Common<0x14>;
1472 def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>;
1473 def ASHR_eg : ASHR_Common<0x15>;
1474 def LSHR_eg : LSHR_Common<0x16>;
1475 def LSHL_eg : LSHL_Common<0x17>;
1476 def CNDE_eg : CNDE_Common<0x19>;
1477 def CNDGT_eg : CNDGT_Common<0x1A>;
1478 def CNDGE_eg : CNDGE_Common<0x1B>;
1479 def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
1480 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
1481 def DOT4_eg : DOT4_Common<0xBE>;
1482 defm CUBE_eg : CUBE_Common<0xC0>;
1484 let hasSideEffects = 1 in {
1485 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", []>;
1488 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
1490 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
1494 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
1496 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
1500 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
1502 // TRUNC is used for the FLT_TO_INT instructions to work around a
1503 // perceived problem where the rounding modes are applied differently
1504 // depending on the instruction and the slot they are in.
1506 // https://bugs.freedesktop.org/show_bug.cgi?id=50232
1507 // Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c
1509 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
1510 // which do not need to be truncated since the fp values are 0.0f or 1.0f.
1511 // We should look into handling these cases separately.
1512 def : Pat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>;
1514 def : Pat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>;
1517 def : SHA256MaPattern <BFI_INT_eg, XOR_INT>;
1519 def EG_ExportSwz : ExportSwzInst {
1520 let Word1{19-16} = 0; // BURST_COUNT
1521 let Word1{20} = 1; // VALID_PIXEL_MODE
1522 let Word1{21} = eop;
1523 let Word1{29-22} = inst;
1524 let Word1{30} = 0; // MARK
1525 let Word1{31} = 1; // BARRIER
1527 defm : ExportPattern<EG_ExportSwz, 83>;
1529 def EG_ExportBuf : ExportBufInst {
1530 let Word1{19-16} = 0; // BURST_COUNT
1531 let Word1{20} = 1; // VALID_PIXEL_MODE
1532 let Word1{21} = eop;
1533 let Word1{29-22} = inst;
1534 let Word1{30} = 0; // MARK
1535 let Word1{31} = 1; // BARRIER
1537 defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>;
1539 def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT),
1540 "TEX $COUNT @$ADDR"> {
1543 def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT),
1544 "VTX $COUNT @$ADDR"> {
1547 def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR),
1548 "LOOP_START_DX10 @$ADDR"> {
1552 def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1556 def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR),
1557 "LOOP_BREAK @$ADDR"> {
1561 def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR),
1562 "CONTINUE @$ADDR"> {
1566 def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1567 "JUMP @$ADDR POP:$POP_COUNT"> {
1570 def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1571 "ELSE @$ADDR POP:$POP_COUNT"> {
1574 def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> {
1579 def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1580 "POP @$ADDR POP:$POP_COUNT"> {
1583 def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> {
1587 let END_OF_PROGRAM = 1;
1590 } // End Predicates = [isEGorCayman]
1592 //===----------------------------------------------------------------------===//
1593 // Regist loads and stores - for indirect addressing
1594 //===----------------------------------------------------------------------===//
1596 defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>;
1598 //===----------------------------------------------------------------------===//
1599 // Cayman Instructions
1600 //===----------------------------------------------------------------------===//
1602 let Predicates = [isCayman] in {
1604 let isVector = 1 in {
1606 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
1608 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
1609 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
1610 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
1611 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
1612 def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>;
1613 def EXP_IEEE_cm : EXP_IEEE_Common<0x81>;
1614 def LOG_IEEE_cm : LOG_IEEE_Common<0x83>;
1615 def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>;
1616 def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>;
1617 def SIN_cm : SIN_Common<0x8D>;
1618 def COS_cm : COS_Common<0x8E>;
1619 } // End isVector = 1
1621 def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL>;
1622 def : SIN_PAT <SIN_cm>;
1623 def : COS_PAT <COS_cm>;
1625 defm DIV_cm : DIV_Common<RECIP_IEEE_cm>;
1627 // RECIP_UINT emulation for Cayman
1628 // The multiplication scales from [0,1] to the unsigned integer range
1630 (AMDGPUurecip i32:$src0),
1631 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)),
1632 (MOV_IMM_I32 CONST.FP_UINT_MAX_PLUS_1)))
1635 def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> {
1641 def : Pat<(fsqrt f32:$src), (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm $src))>;
1644 def RAT_STORE_DWORD_cm : EG_CF_RAT <
1645 0x57, 0x14, 0x1, (outs),
1646 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr),
1647 "EXPORT_RAT_INST_STORE_DWORD $rw_gpr, $index_gpr",
1648 [(global_store i32:$rw_gpr, i32:$index_gpr)]
1650 let eop = 0; // This bit is not used on Cayman.
1653 class VTX_READ_cm <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
1654 : VTX_WORD0_cm, VTX_READ<name, buffer_id, outs, pattern> {
1659 let FETCH_WHOLE_QUAD = 0;
1660 let BUFFER_ID = buffer_id;
1662 // XXX: We can infer this field based on the SRC_GPR. This would allow us
1663 // to store vertex addresses in any channel, not just X.
1666 let STRUCTURED_READ = 0;
1668 let COALESCED_READ = 0;
1670 let Inst{31-0} = Word0;
1673 class VTX_READ_8_cm <bits<8> buffer_id, list<dag> pattern>
1674 : VTX_READ_cm <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id,
1675 (outs R600_TReg32_X:$dst_gpr), pattern> {
1678 let DST_SEL_Y = 7; // Masked
1679 let DST_SEL_Z = 7; // Masked
1680 let DST_SEL_W = 7; // Masked
1681 let DATA_FORMAT = 1; // FMT_8
1684 class VTX_READ_16_cm <bits<8> buffer_id, list<dag> pattern>
1685 : VTX_READ_cm <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id,
1686 (outs R600_TReg32_X:$dst_gpr), pattern> {
1688 let DST_SEL_Y = 7; // Masked
1689 let DST_SEL_Z = 7; // Masked
1690 let DST_SEL_W = 7; // Masked
1691 let DATA_FORMAT = 5; // FMT_16
1695 class VTX_READ_32_cm <bits<8> buffer_id, list<dag> pattern>
1696 : VTX_READ_cm <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id,
1697 (outs R600_TReg32_X:$dst_gpr), pattern> {
1700 let DST_SEL_Y = 7; // Masked
1701 let DST_SEL_Z = 7; // Masked
1702 let DST_SEL_W = 7; // Masked
1703 let DATA_FORMAT = 0xD; // COLOR_32
1705 // This is not really necessary, but there were some GPU hangs that appeared
1706 // to be caused by ALU instructions in the next instruction group that wrote
1707 // to the $src_gpr registers of the VTX_READ.
1709 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
1710 // %T2_X<def> = MOV %ZERO
1711 //Adding this constraint prevents this from happening.
1712 let Constraints = "$src_gpr.ptr = $dst_gpr";
1715 class VTX_READ_128_cm <bits<8> buffer_id, list<dag> pattern>
1716 : VTX_READ_cm <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id,
1717 (outs R600_Reg128:$dst_gpr), pattern> {
1723 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
1725 // XXX: Need to force VTX_READ_128 instructions to write to the same register
1726 // that holds its buffer address to avoid potential hangs. We can't use
1727 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst
1728 // registers are different sizes.
1731 //===----------------------------------------------------------------------===//
1732 // VTX Read from parameter memory space
1733 //===----------------------------------------------------------------------===//
1734 def VTX_READ_PARAM_8_cm : VTX_READ_8_cm <0,
1735 [(set i32:$dst_gpr, (load_param_zexti8 ADDRVTX_READ:$src_gpr))]
1738 def VTX_READ_PARAM_16_cm : VTX_READ_16_cm <0,
1739 [(set i32:$dst_gpr, (load_param_zexti16 ADDRVTX_READ:$src_gpr))]
1742 def VTX_READ_PARAM_32_cm : VTX_READ_32_cm <0,
1743 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1746 def VTX_READ_PARAM_128_cm : VTX_READ_128_cm <0,
1747 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1750 //===----------------------------------------------------------------------===//
1751 // VTX Read from global memory space
1752 //===----------------------------------------------------------------------===//
1755 def VTX_READ_GLOBAL_8_cm : VTX_READ_8_cm <1,
1756 [(set i32:$dst_gpr, (zextloadi8_global ADDRVTX_READ:$src_gpr))]
1760 def VTX_READ_GLOBAL_32_cm : VTX_READ_32_cm <1,
1761 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
1765 def VTX_READ_GLOBAL_128_cm : VTX_READ_128_cm <1,
1766 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
1769 //===----------------------------------------------------------------------===//
1771 // XXX: We are currently storing all constants in the global address space.
1772 //===----------------------------------------------------------------------===//
1774 def CONSTANT_LOAD_cm : VTX_READ_32_cm <1,
1775 [(set i32:$dst_gpr, (constant_load ADDRVTX_READ:$src_gpr))]
1780 //===----------------------------------------------------------------------===//
1781 // Branch Instructions
1782 //===----------------------------------------------------------------------===//
1785 def IF_PREDICATE_SET : ILFormat<(outs), (ins GPRI32:$src),
1786 "IF_PREDICATE_SET $src", []>;
1788 def PREDICATED_BREAK : ILFormat<(outs), (ins GPRI32:$src),
1789 "PREDICATED_BREAK $src", []>;
1791 //===----------------------------------------------------------------------===//
1792 // Pseudo instructions
1793 //===----------------------------------------------------------------------===//
1795 let isPseudo = 1 in {
1797 def PRED_X : InstR600 <
1798 (outs R600_Predicate_Bit:$dst),
1799 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
1801 let FlagOperandIdx = 3;
1804 let isTerminator = 1, isBranch = 1 in {
1805 def JUMP_COND : InstR600 <
1807 (ins brtarget:$target, R600_Predicate_Bit:$p),
1808 "JUMP $target ($p)",
1812 def JUMP : InstR600 <
1814 (ins brtarget:$target),
1819 let isPredicable = 1;
1823 } // End isTerminator = 1, isBranch = 1
1825 let usesCustomInserter = 1 in {
1827 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
1829 def MASK_WRITE : AMDGPUShaderInst <
1831 (ins R600_Reg32:$src),
1836 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 1
1840 (outs R600_Reg128:$dst),
1841 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
1842 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
1843 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
1844 [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2,
1845 imm:$resourceId, imm:$samplerId, imm:$textureTarget))],
1850 def TXD_SHADOW: InstR600 <
1851 (outs R600_Reg128:$dst),
1852 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
1853 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
1854 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
1855 [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2,
1856 imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))],
1861 } // End isPseudo = 1
1862 } // End usesCustomInserter = 1
1864 def CLAMP_R600 : CLAMP <R600_Reg32>;
1865 def FABS_R600 : FABS<R600_Reg32>;
1866 def FNEG_R600 : FNEG<R600_Reg32>;
1868 //===---------------------------------------------------------------------===//
1869 // Return instruction
1870 //===---------------------------------------------------------------------===//
1871 let isTerminator = 1, isReturn = 1, hasCtrlDep = 1,
1872 usesCustomInserter = 1 in {
1873 def RETURN : ILFormat<(outs), (ins variable_ops),
1874 "RETURN", [(IL_retflag)]>;
1878 //===----------------------------------------------------------------------===//
1879 // Constant Buffer Addressing Support
1880 //===----------------------------------------------------------------------===//
1882 let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
1883 def CONST_COPY : Instruction {
1884 let OutOperandList = (outs R600_Reg32:$dst);
1885 let InOperandList = (ins i32imm:$src);
1887 [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];
1888 let AsmString = "CONST_COPY";
1889 let neverHasSideEffects = 1;
1890 let isAsCheapAsAMove = 1;
1891 let Itinerary = NullALU;
1893 } // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
1895 def TEX_VTX_CONSTBUF :
1896 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "VTX_READ_eg $dst, $ptr",
1897 [(set v4i32:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$BUFFER_ID)))]>,
1898 VTX_WORD1_GPR, VTX_WORD0_eg {
1902 let FETCH_WHOLE_QUAD = 0;
1906 let USE_CONST_FIELDS = 0;
1907 let NUM_FORMAT_ALL = 2;
1908 let FORMAT_COMP_ALL = 1;
1909 let SRF_MODE_ALL = 1;
1910 let MEGA_FETCH_COUNT = 16;
1915 let DATA_FORMAT = 35;
1917 let Inst{31-0} = Word0;
1918 let Inst{63-32} = Word1;
1920 // LLVM can only encode 64-bit instructions, so these fields are manually
1921 // encoded in R600CodeEmitter
1924 // bits<2> ENDIAN_SWAP = 0;
1925 // bits<1> CONST_BUF_NO_STRIDE = 0;
1926 // bits<1> MEGA_FETCH = 0;
1927 // bits<1> ALT_CONST = 0;
1928 // bits<2> BUFFER_INDEX_MODE = 0;
1932 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1933 // is done in R600CodeEmitter
1935 // Inst{79-64} = OFFSET;
1936 // Inst{81-80} = ENDIAN_SWAP;
1937 // Inst{82} = CONST_BUF_NO_STRIDE;
1938 // Inst{83} = MEGA_FETCH;
1939 // Inst{84} = ALT_CONST;
1940 // Inst{86-85} = BUFFER_INDEX_MODE;
1941 // Inst{95-86} = 0; Reserved
1943 // VTX_WORD3 (Padding)
1945 // Inst{127-96} = 0;
1950 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr",
1951 [(set v4f32:$dst, (int_R600_load_texbuf ADDRGA_VAR_OFFSET:$ptr, imm:$BUFFER_ID))]>,
1952 VTX_WORD1_GPR, VTX_WORD0_eg {
1956 let FETCH_WHOLE_QUAD = 0;
1960 let USE_CONST_FIELDS = 1;
1961 let NUM_FORMAT_ALL = 0;
1962 let FORMAT_COMP_ALL = 0;
1963 let SRF_MODE_ALL = 1;
1964 let MEGA_FETCH_COUNT = 16;
1969 let DATA_FORMAT = 0;
1971 let Inst{31-0} = Word0;
1972 let Inst{63-32} = Word1;
1974 // LLVM can only encode 64-bit instructions, so these fields are manually
1975 // encoded in R600CodeEmitter
1978 // bits<2> ENDIAN_SWAP = 0;
1979 // bits<1> CONST_BUF_NO_STRIDE = 0;
1980 // bits<1> MEGA_FETCH = 0;
1981 // bits<1> ALT_CONST = 0;
1982 // bits<2> BUFFER_INDEX_MODE = 0;
1986 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1987 // is done in R600CodeEmitter
1989 // Inst{79-64} = OFFSET;
1990 // Inst{81-80} = ENDIAN_SWAP;
1991 // Inst{82} = CONST_BUF_NO_STRIDE;
1992 // Inst{83} = MEGA_FETCH;
1993 // Inst{84} = ALT_CONST;
1994 // Inst{86-85} = BUFFER_INDEX_MODE;
1995 // Inst{95-86} = 0; Reserved
1997 // VTX_WORD3 (Padding)
1999 // Inst{127-96} = 0;
2005 //===--------------------------------------------------------------------===//
2006 // Instructions support
2007 //===--------------------------------------------------------------------===//
2008 //===---------------------------------------------------------------------===//
2009 // Custom Inserter for Branches and returns, this eventually will be a
2011 //===---------------------------------------------------------------------===//
2012 let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in {
2013 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
2014 "; Pseudo unconditional branch instruction",
2016 defm BRANCH_COND : BranchConditional<IL_brcond>;
2019 //===---------------------------------------------------------------------===//
2020 // Flow and Program control Instructions
2021 //===---------------------------------------------------------------------===//
2022 let isTerminator=1 in {
2023 def SWITCH : ILFormat< (outs), (ins GPRI32:$src),
2024 !strconcat("SWITCH", " $src"), []>;
2025 def CASE : ILFormat< (outs), (ins GPRI32:$src),
2026 !strconcat("CASE", " $src"), []>;
2027 def BREAK : ILFormat< (outs), (ins),
2029 def CONTINUE : ILFormat< (outs), (ins),
2031 def DEFAULT : ILFormat< (outs), (ins),
2033 def ELSE : ILFormat< (outs), (ins),
2035 def ENDSWITCH : ILFormat< (outs), (ins),
2037 def ENDMAIN : ILFormat< (outs), (ins),
2039 def END : ILFormat< (outs), (ins),
2041 def ENDFUNC : ILFormat< (outs), (ins),
2043 def ENDIF : ILFormat< (outs), (ins),
2045 def WHILELOOP : ILFormat< (outs), (ins),
2047 def ENDLOOP : ILFormat< (outs), (ins),
2049 def FUNC : ILFormat< (outs), (ins),
2051 def RETDYN : ILFormat< (outs), (ins),
2053 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2054 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">;
2055 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2056 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">;
2057 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2058 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">;
2059 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2060 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">;
2061 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2062 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">;
2063 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2064 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">;
2065 defm IFC : BranchInstr2<"IFC">;
2066 defm BREAKC : BranchInstr2<"BREAKC">;
2067 defm CONTINUEC : BranchInstr2<"CONTINUEC">;
2070 //===----------------------------------------------------------------------===//
2072 //===----------------------------------------------------------------------===//
2074 // CND*_INT Pattterns for f32 True / False values
2076 class CND_INT_f32 <InstR600 cnd, CondCode cc> : Pat <
2077 (selectcc i32:$src0, 0, f32:$src1, f32:$src2, cc),
2078 (cnd $src0, $src1, $src2)
2081 def : CND_INT_f32 <CNDE_INT, SETEQ>;
2082 def : CND_INT_f32 <CNDGT_INT, SETGT>;
2083 def : CND_INT_f32 <CNDGE_INT, SETGE>;
2085 //CNDGE_INT extra pattern
2087 (selectcc i32:$src0, -1, i32:$src1, i32:$src2, COND_GT),
2088 (CNDGE_INT $src0, $src1, $src2)
2094 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
2098 (int_AMDGPU_kill f32:$src0),
2099 (MASK_WRITE (KILLGT (f32 ZERO), $src0))
2104 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_LT),
2110 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_LE),
2114 // SETGT_DX10 reverse args
2116 (selectcc f32:$src0, f32:$src1, -1, 0, COND_LT),
2117 (SETGT_DX10 $src1, $src0)
2120 // SETGE_DX10 reverse args
2122 (selectcc f32:$src0, f32:$src1, -1, 0, COND_LE),
2123 (SETGE_DX10 $src1, $src0)
2126 // SETGT_INT reverse args
2128 (selectcc i32:$src0, i32:$src1, -1, 0, SETLT),
2129 (SETGT_INT $src1, $src0)
2132 // SETGE_INT reverse args
2134 (selectcc i32:$src0, i32:$src1, -1, 0, SETLE),
2135 (SETGE_INT $src1, $src0)
2138 // SETGT_UINT reverse args
2140 (selectcc i32:$src0, i32:$src1, -1, 0, SETULT),
2141 (SETGT_UINT $src1, $src0)
2144 // SETGE_UINT reverse args
2146 (selectcc i32:$src0, i32:$src1, -1, 0, SETULE),
2147 (SETGE_UINT $src1, $src0)
2150 // The next two patterns are special cases for handling 'true if ordered' and
2151 // 'true if unordered' conditionals. The assumption here is that the behavior of
2152 // SETE and SNE conforms to the Direct3D 10 rules for floating point values
2154 // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit
2155 // We assume that SETE returns false when one of the operands is NAN and
2156 // SNE returns true when on of the operands is NAN
2158 //SETE - 'true if ordered'
2160 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, SETO),
2164 //SETE_DX10 - 'true if ordered'
2166 (selectcc f32:$src0, f32:$src1, -1, 0, SETO),
2167 (SETE_DX10 $src0, $src1)
2170 //SNE - 'true if unordered'
2172 (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, SETUO),
2176 //SETNE_DX10 - 'true if ordered'
2178 (selectcc f32:$src0, f32:$src1, -1, 0, SETUO),
2179 (SETNE_DX10 $src0, $src1)
2182 def : Extract_Element <f32, v4f32, 0, sub0>;
2183 def : Extract_Element <f32, v4f32, 1, sub1>;
2184 def : Extract_Element <f32, v4f32, 2, sub2>;
2185 def : Extract_Element <f32, v4f32, 3, sub3>;
2187 def : Insert_Element <f32, v4f32, 0, sub0>;
2188 def : Insert_Element <f32, v4f32, 1, sub1>;
2189 def : Insert_Element <f32, v4f32, 2, sub2>;
2190 def : Insert_Element <f32, v4f32, 3, sub3>;
2192 def : Extract_Element <i32, v4i32, 0, sub0>;
2193 def : Extract_Element <i32, v4i32, 1, sub1>;
2194 def : Extract_Element <i32, v4i32, 2, sub2>;
2195 def : Extract_Element <i32, v4i32, 3, sub3>;
2197 def : Insert_Element <i32, v4i32, 0, sub0>;
2198 def : Insert_Element <i32, v4i32, 1, sub1>;
2199 def : Insert_Element <i32, v4i32, 2, sub2>;
2200 def : Insert_Element <i32, v4i32, 3, sub3>;
2202 def : Vector4_Build <v4f32, f32>;
2203 def : Vector4_Build <v4i32, i32>;
2205 // bitconvert patterns
2207 def : BitConvert <i32, f32, R600_Reg32>;
2208 def : BitConvert <f32, i32, R600_Reg32>;
2209 def : BitConvert <v4f32, v4i32, R600_Reg128>;
2210 def : BitConvert <v4i32, v4f32, R600_Reg128>;
2212 // DWORDADDR pattern
2213 def : DwordAddrPat <i32, R600_Reg32>;
2215 } // End isR600toCayman Predicate