1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // R600 Tablegen instruction definitions
12 //===----------------------------------------------------------------------===//
14 include "R600Intrinsics.td"
15 include "R600InstrFormats.td"
17 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
18 InstR600 <outs, ins, asm, pattern, NullALU> {
20 let Namespace = "AMDGPU";
23 def MEMxi : Operand<iPTR> {
24 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
25 let PrintMethod = "printMemOperand";
28 def MEMrr : Operand<iPTR> {
29 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
32 // Operands for non-registers
34 class InstFlag<string PM = "printOperand", int Default = 0>
35 : OperandWithDefaultOps <i32, (ops (i32 Default))> {
39 // src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers
40 def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> {
41 let PrintMethod = "printSel";
43 def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> {
44 let PrintMethod = "printBankSwizzle";
47 def LITERAL : InstFlag<"printLiteral">;
49 def WRITE : InstFlag <"printWrite", 1>;
50 def OMOD : InstFlag <"printOMOD">;
51 def REL : InstFlag <"printRel">;
52 def CLAMP : InstFlag <"printClamp">;
53 def NEG : InstFlag <"printNeg">;
54 def ABS : InstFlag <"printAbs">;
55 def UEM : InstFlag <"printUpdateExecMask">;
56 def UP : InstFlag <"printUpdatePred">;
58 // XXX: The r600g finalizer in Mesa expects last to be one in most cases.
59 // Once we start using the packetizer in this backend we should have this
61 def LAST : InstFlag<"printLast", 1>;
62 def RSel : Operand<i32> {
63 let PrintMethod = "printRSel";
65 def CT: Operand<i32> {
66 let PrintMethod = "printCT";
69 def FRAMEri : Operand<iPTR> {
70 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index);
73 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
74 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
75 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
76 def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>;
77 def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>;
80 def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
84 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
86 // Class for instructions with only one source register.
87 // If you add new ins to this instruction, make sure they are listed before
88 // $literal, because the backend currently assumes that the last operand is
89 // a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in
90 // R600Defines.h, R600InstrInfo::buildDefaultInstruction(),
91 // and R600InstrInfo::getOperandIdx().
92 class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
93 InstrItinClass itin = AnyALU> :
94 InstR600 <(outs R600_Reg32:$dst),
95 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
96 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
97 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
98 BANK_SWIZZLE:$bank_swizzle),
99 !strconcat(" ", opName,
100 "$clamp $last $dst$write$dst_rel$omod, "
101 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
102 "$pred_sel $bank_swizzle"),
106 R600ALU_Word1_OP2 <inst> {
112 let update_exec_mask = 0;
114 let HasNativeOperands = 1;
117 let DisableEncoding = "$literal";
118 let UseNamedOperandTable = 1;
120 let Inst{31-0} = Word0;
121 let Inst{63-32} = Word1;
124 class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
125 InstrItinClass itin = AnyALU> :
126 R600_1OP <inst, opName,
127 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))]
130 // If you add or change the operands for R600_2OP instructions, you must
131 // also update the R600Op2OperandIndex::ROI enum in R600Defines.h,
132 // R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx().
133 class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
134 InstrItinClass itin = AnyALU> :
135 InstR600 <(outs R600_Reg32:$dst),
136 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
137 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
138 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
139 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
140 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
141 BANK_SWIZZLE:$bank_swizzle),
142 !strconcat(" ", opName,
143 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
144 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
145 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
146 "$pred_sel $bank_swizzle"),
150 R600ALU_Word1_OP2 <inst> {
152 let HasNativeOperands = 1;
155 let DisableEncoding = "$literal";
156 let UseNamedOperandTable = 1;
158 let Inst{31-0} = Word0;
159 let Inst{63-32} = Word1;
162 class R600_2OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
163 InstrItinClass itim = AnyALU> :
164 R600_2OP <inst, opName,
165 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
169 // If you add our change the operands for R600_3OP instructions, you must
170 // also update the R600Op3OperandIndex::ROI enum in R600Defines.h,
171 // R600InstrInfo::buildDefaultInstruction(), and
172 // R600InstrInfo::getOperandIdx().
173 class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
174 InstrItinClass itin = AnyALU> :
175 InstR600 <(outs R600_Reg32:$dst),
176 (ins REL:$dst_rel, CLAMP:$clamp,
177 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
178 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
179 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,
180 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
181 BANK_SWIZZLE:$bank_swizzle),
182 !strconcat(" ", opName, "$clamp $last $dst$dst_rel, "
183 "$src0_neg$src0$src0_rel, "
184 "$src1_neg$src1$src1_rel, "
185 "$src2_neg$src2$src2_rel, "
191 R600ALU_Word1_OP3<inst>{
193 let HasNativeOperands = 1;
194 let DisableEncoding = "$literal";
196 let UseNamedOperandTable = 1;
199 let Inst{31-0} = Word0;
200 let Inst{63-32} = Word1;
203 class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern,
204 InstrItinClass itin = VecALU> :
205 InstR600 <(outs R600_Reg32:$dst),
213 } // End mayLoad = 1, mayStore = 0, hasSideEffects = 0
215 def TEX_SHADOW : PatLeaf<
217 [{uint32_t TType = (uint32_t)N->getZExtValue();
218 return (TType >= 6 && TType <= 8) || (TType >= 11 && TType <= 13);
222 def TEX_RECT : PatLeaf<
224 [{uint32_t TType = (uint32_t)N->getZExtValue();
229 def TEX_ARRAY : PatLeaf<
231 [{uint32_t TType = (uint32_t)N->getZExtValue();
232 return TType == 9 || TType == 10 || TType == 16;
236 def TEX_SHADOW_ARRAY : PatLeaf<
238 [{uint32_t TType = (uint32_t)N->getZExtValue();
239 return TType == 11 || TType == 12 || TType == 17;
243 def TEX_MSAA : PatLeaf<
245 [{uint32_t TType = (uint32_t)N->getZExtValue();
250 def TEX_ARRAY_MSAA : PatLeaf<
252 [{uint32_t TType = (uint32_t)N->getZExtValue();
257 class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> ratid, bits<4> mask,
258 dag outs, dag ins, string asm, list<dag> pattern> :
259 InstR600ISA <outs, ins, asm, pattern>,
260 CF_ALLOC_EXPORT_WORD0_RAT, CF_ALLOC_EXPORT_WORD1_BUF {
263 let rat_inst = ratinst;
265 // XXX: Have a separate instruction for non-indexed writes.
271 let comp_mask = mask;
274 let cf_inst = cfinst;
278 let Inst{31-0} = Word0;
279 let Inst{63-32} = Word1;
284 class VTX_READ <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
285 : InstR600ISA <outs, (ins MEMxi:$src_gpr), name, pattern>,
290 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,
291 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,
292 // however, based on my testing if USE_CONST_FIELDS is set, then all
293 // these fields need to be set to 0.
294 let USE_CONST_FIELDS = 0;
295 let NUM_FORMAT_ALL = 1;
296 let FORMAT_COMP_ALL = 0;
297 let SRF_MODE_ALL = 0;
299 let Inst{63-32} = Word1;
300 // LLVM can only encode 64-bit instructions, so these fields are manually
301 // encoded in R600CodeEmitter
304 // bits<2> ENDIAN_SWAP = 0;
305 // bits<1> CONST_BUF_NO_STRIDE = 0;
306 // bits<1> MEGA_FETCH = 0;
307 // bits<1> ALT_CONST = 0;
308 // bits<2> BUFFER_INDEX_MODE = 0;
310 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
311 // is done in R600CodeEmitter
313 // Inst{79-64} = OFFSET;
314 // Inst{81-80} = ENDIAN_SWAP;
315 // Inst{82} = CONST_BUF_NO_STRIDE;
316 // Inst{83} = MEGA_FETCH;
317 // Inst{84} = ALT_CONST;
318 // Inst{86-85} = BUFFER_INDEX_MODE;
319 // Inst{95-86} = 0; Reserved
321 // VTX_WORD3 (Padding)
328 class LoadParamFrag <PatFrag load_type> : PatFrag <
329 (ops node:$ptr), (load_type node:$ptr),
330 [{ return isConstantLoad(dyn_cast<LoadSDNode>(N), 0); }]
333 def load_param : LoadParamFrag<load>;
334 def load_param_exti8 : LoadParamFrag<az_extloadi8>;
335 def load_param_exti16 : LoadParamFrag<az_extloadi16>;
337 def isR600 : Predicate<"Subtarget.getGeneration() <= AMDGPUSubtarget::R700">;
338 def isR700 : Predicate<"Subtarget.getGeneration() == AMDGPUSubtarget::R700">;
339 def isEG : Predicate<
340 "Subtarget.getGeneration() >= AMDGPUSubtarget::EVERGREEN && "
341 "Subtarget.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && "
342 "!Subtarget.hasCaymanISA()">;
344 def isCayman : Predicate<"Subtarget.hasCaymanISA()">;
345 def isEGorCayman : Predicate<"Subtarget.getGeneration() == "
346 "AMDGPUSubtarget::EVERGREEN"
347 "|| Subtarget.getGeneration() =="
348 "AMDGPUSubtarget::NORTHERN_ISLANDS">;
350 def isR600toCayman : Predicate<
351 "Subtarget.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS">;
353 //===----------------------------------------------------------------------===//
355 //===----------------------------------------------------------------------===//
357 def INTERP_PAIR_XY : AMDGPUShaderInst <
358 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1),
359 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
360 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
363 def INTERP_PAIR_ZW : AMDGPUShaderInst <
364 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1),
365 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
366 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",
369 def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS",
370 SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>,
374 def DOT4 : SDNode<"AMDGPUISD::DOT4",
375 SDTypeProfile<1, 8, [SDTCisFP<0>, SDTCisVT<1, f32>, SDTCisVT<2, f32>,
376 SDTCisVT<3, f32>, SDTCisVT<4, f32>, SDTCisVT<5, f32>,
377 SDTCisVT<6, f32>, SDTCisVT<7, f32>, SDTCisVT<8, f32>]>,
381 def COS_HW : SDNode<"AMDGPUISD::COS_HW",
382 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>
385 def SIN_HW : SDNode<"AMDGPUISD::SIN_HW",
386 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>
389 def TEXTURE_FETCH_Type : SDTypeProfile<1, 19, [SDTCisFP<0>]>;
391 def TEXTURE_FETCH: SDNode<"AMDGPUISD::TEXTURE_FETCH", TEXTURE_FETCH_Type, []>;
393 multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> {
394 def : Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR,
395 (i32 imm:$srcx), (i32 imm:$srcy), (i32 imm:$srcz), (i32 imm:$srcw),
396 (i32 imm:$offsetx), (i32 imm:$offsety), (i32 imm:$offsetz),
397 (i32 imm:$DST_SEL_X), (i32 imm:$DST_SEL_Y), (i32 imm:$DST_SEL_Z),
398 (i32 imm:$DST_SEL_W),
399 (i32 imm:$RESOURCE_ID), (i32 imm:$SAMPLER_ID),
400 (i32 imm:$COORD_TYPE_X), (i32 imm:$COORD_TYPE_Y), (i32 imm:$COORD_TYPE_Z),
401 (i32 imm:$COORD_TYPE_W)),
402 (inst R600_Reg128:$SRC_GPR,
403 imm:$srcx, imm:$srcy, imm:$srcz, imm:$srcw,
404 imm:$offsetx, imm:$offsety, imm:$offsetz,
405 imm:$DST_SEL_X, imm:$DST_SEL_Y, imm:$DST_SEL_Z,
407 imm:$RESOURCE_ID, imm:$SAMPLER_ID,
408 imm:$COORD_TYPE_X, imm:$COORD_TYPE_Y, imm:$COORD_TYPE_Z,
412 //===----------------------------------------------------------------------===//
413 // Interpolation Instructions
414 //===----------------------------------------------------------------------===//
416 def INTERP_VEC_LOAD : AMDGPUShaderInst <
417 (outs R600_Reg128:$dst),
419 "INTERP_LOAD $src0 : $dst",
420 [(set R600_Reg128:$dst, (int_R600_interp_const imm:$src0))]>;
422 def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> {
423 let bank_swizzle = 5;
426 def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> {
427 let bank_swizzle = 5;
430 def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>;
432 //===----------------------------------------------------------------------===//
433 // Export Instructions
434 //===----------------------------------------------------------------------===//
436 def ExportType : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
438 def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType,
439 [SDNPHasChain, SDNPSideEffect]>;
442 field bits<32> Word0;
449 let Word0{12-0} = arraybase;
450 let Word0{14-13} = type;
451 let Word0{21-15} = gpr;
452 let Word0{22} = 0; // RW_REL
453 let Word0{29-23} = 0; // INDEX_GPR
454 let Word0{31-30} = elem_size;
457 class ExportSwzWord1 {
458 field bits<32> Word1;
467 let Word1{2-0} = sw_x;
468 let Word1{5-3} = sw_y;
469 let Word1{8-6} = sw_z;
470 let Word1{11-9} = sw_w;
473 class ExportBufWord1 {
474 field bits<32> Word1;
481 let Word1{11-0} = arraySize;
482 let Word1{15-12} = compMask;
485 multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
486 def : Pat<(int_R600_store_pixel_depth R600_Reg32:$reg),
488 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
489 0, 61, 0, 7, 7, 7, cf_inst, 0)
492 def : Pat<(int_R600_store_pixel_stencil R600_Reg32:$reg),
494 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
495 0, 61, 7, 0, 7, 7, cf_inst, 0)
498 def : Pat<(int_R600_store_dummy (i32 imm:$type)),
500 (v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0)
503 def : Pat<(int_R600_store_dummy 1),
505 (v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0)
508 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
509 (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)),
510 (ExportInst R600_Reg128:$src, imm:$type, imm:$base,
511 imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0)
516 multiclass SteamOutputExportPattern<Instruction ExportInst,
517 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> {
519 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
520 (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)),
521 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
522 4095, imm:$mask, buf0inst, 0)>;
524 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
525 (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)),
526 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
527 4095, imm:$mask, buf1inst, 0)>;
529 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
530 (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)),
531 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
532 4095, imm:$mask, buf2inst, 0)>;
534 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
535 (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)),
536 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
537 4095, imm:$mask, buf3inst, 0)>;
540 // Export Instructions should not be duplicated by TailDuplication pass
541 // (which assumes that duplicable instruction are affected by exec mask)
542 let usesCustomInserter = 1, isNotDuplicable = 1 in {
544 class ExportSwzInst : InstR600ISA<(
546 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
547 RSel:$sw_x, RSel:$sw_y, RSel:$sw_z, RSel:$sw_w, i32imm:$inst,
549 !strconcat("EXPORT", " $gpr.$sw_x$sw_y$sw_z$sw_w"),
550 []>, ExportWord0, ExportSwzWord1 {
552 let Inst{31-0} = Word0;
553 let Inst{63-32} = Word1;
557 } // End usesCustomInserter = 1
559 class ExportBufInst : InstR600ISA<(
561 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
562 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop),
563 !strconcat("EXPORT", " $gpr"),
564 []>, ExportWord0, ExportBufWord1 {
566 let Inst{31-0} = Word0;
567 let Inst{63-32} = Word1;
571 //===----------------------------------------------------------------------===//
572 // Control Flow Instructions
573 //===----------------------------------------------------------------------===//
576 def KCACHE : InstFlag<"printKCache">;
578 class ALU_CLAUSE<bits<4> inst, string OpName> : AMDGPUInst <(outs),
579 (ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1,
580 KCACHE:$KCACHE_MODE0, KCACHE:$KCACHE_MODE1,
581 i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1,
582 i32imm:$COUNT, i32imm:$Enabled),
583 !strconcat(OpName, " $COUNT, @$ADDR, "
584 "KC0[$KCACHE_MODE0], KC1[$KCACHE_MODE1]"),
585 [] >, CF_ALU_WORD0, CF_ALU_WORD1 {
590 let WHOLE_QUAD_MODE = 0;
592 let UseNamedOperandTable = 1;
594 let Inst{31-0} = Word0;
595 let Inst{63-32} = Word1;
598 class CF_WORD0_R600 {
599 field bits<32> Word0;
606 class CF_CLAUSE_R600 <bits<7> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
607 ins, AsmPrint, [] >, CF_WORD0_R600, CF_WORD1_R600 {
614 let VALID_PIXEL_MODE = 0;
616 let COUNT = CNT{2-0};
618 let COUNT_3 = CNT{3};
619 let END_OF_PROGRAM = 0;
620 let WHOLE_QUAD_MODE = 0;
622 let Inst{31-0} = Word0;
623 let Inst{63-32} = Word1;
626 class CF_CLAUSE_EG <bits<8> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
627 ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG {
632 let JUMPTABLE_SEL = 0;
634 let VALID_PIXEL_MODE = 0;
636 let END_OF_PROGRAM = 0;
638 let Inst{31-0} = Word0;
639 let Inst{63-32} = Word1;
642 def CF_ALU : ALU_CLAUSE<8, "ALU">;
643 def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">;
644 def CF_ALU_POP_AFTER : ALU_CLAUSE<10, "ALU_POP_AFTER">;
645 def CF_ALU_CONTINUE : ALU_CLAUSE<13, "ALU_CONTINUE">;
646 def CF_ALU_BREAK : ALU_CLAUSE<14, "ALU_BREAK">;
647 def CF_ALU_ELSE_AFTER : ALU_CLAUSE<15, "ALU_ELSE_AFTER">;
649 def FETCH_CLAUSE : AMDGPUInst <(outs),
650 (ins i32imm:$addr), "Fetch clause starting at $addr:", [] > {
656 def ALU_CLAUSE : AMDGPUInst <(outs),
657 (ins i32imm:$addr), "ALU clause starting at $addr:", [] > {
663 def LITERALS : AMDGPUInst <(outs),
664 (ins LITERAL:$literal1, LITERAL:$literal2), "$literal1, $literal2", [] > {
669 let Inst{31-0} = literal1;
670 let Inst{63-32} = literal2;
673 def PAD : AMDGPUInst <(outs), (ins), "PAD", [] > {
677 let Predicates = [isR600toCayman] in {
679 //===----------------------------------------------------------------------===//
680 // Common Instructions R600, R700, Evergreen, Cayman
681 //===----------------------------------------------------------------------===//
683 def ADD : R600_2OP_Helper <0x0, "ADD", fadd>;
684 // Non-IEEE MUL: 0 * anything = 0
685 def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE", int_AMDGPU_mul>;
686 def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>;
687 def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax>;
688 def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin>;
690 // For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
691 // so some of the instruction names don't match the asm string.
692 // XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
693 def SETE : R600_2OP <
695 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OEQ))]
700 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGT))]
705 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGE))]
710 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_UNE))]
713 def SETE_DX10 : R600_2OP <
715 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OEQ))]
718 def SETGT_DX10 : R600_2OP <
720 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGT))]
723 def SETGE_DX10 : R600_2OP <
725 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGE))]
728 def SETNE_DX10 : R600_2OP <
730 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_UNE))]
733 def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>;
734 def TRUNC : R600_1OP_Helper <0x11, "TRUNC", int_AMDGPU_trunc>;
735 def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;
736 def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>;
737 def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>;
739 // Add also ftrunc intrinsic pattern
740 def : Pat<(ftrunc f32:$src0), (TRUNC $src0)>;
742 def MOV : R600_1OP <0x19, "MOV", []>;
744 let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in {
746 class MOV_IMM <ValueType vt, Operand immType> : AMDGPUInst <
747 (outs R600_Reg32:$dst),
753 } // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1
755 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
758 (MOV_IMM_I32 imm:$val)
761 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
764 (MOV_IMM_F32 fpimm:$val)
767 def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>;
768 def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>;
769 def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>;
770 def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>;
772 let hasSideEffects = 1 in {
774 def KILLGT : R600_2OP <0x2D, "KILLGT", []>;
776 } // end hasSideEffects
778 def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>;
779 def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>;
780 def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>;
781 def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>;
782 def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>;
783 def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>;
784 def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", AMDGPUsmax>;
785 def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", AMDGPUsmin>;
786 def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", AMDGPUumax>;
787 def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", AMDGPUumin>;
789 def SETE_INT : R600_2OP <
791 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETEQ))]
794 def SETGT_INT : R600_2OP <
796 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGT))]
799 def SETGE_INT : R600_2OP <
801 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))]
804 def SETNE_INT : R600_2OP <
806 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETNE))]
809 def SETGT_UINT : R600_2OP <
811 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGT))]
814 def SETGE_UINT : R600_2OP <
816 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGE))]
819 def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>;
820 def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>;
821 def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>;
822 def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>;
824 def CNDE_INT : R600_3OP <
826 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_EQ))]
829 def CNDGE_INT : R600_3OP <
831 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGE))]
834 def CNDGT_INT : R600_3OP <
836 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGT))]
839 //===----------------------------------------------------------------------===//
840 // Texture instructions
841 //===----------------------------------------------------------------------===//
843 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
845 class R600_TEX <bits<11> inst, string opName> :
846 InstR600 <(outs R600_Reg128:$DST_GPR),
847 (ins R600_Reg128:$SRC_GPR,
848 RSel:$srcx, RSel:$srcy, RSel:$srcz, RSel:$srcw,
849 i32imm:$offsetx, i32imm:$offsety, i32imm:$offsetz,
850 RSel:$DST_SEL_X, RSel:$DST_SEL_Y, RSel:$DST_SEL_Z, RSel:$DST_SEL_W,
851 i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID,
852 CT:$COORD_TYPE_X, CT:$COORD_TYPE_Y, CT:$COORD_TYPE_Z,
855 " $DST_GPR.$DST_SEL_X$DST_SEL_Y$DST_SEL_Z$DST_SEL_W, "
856 "$SRC_GPR.$srcx$srcy$srcz$srcw "
857 "RID:$RESOURCE_ID SID:$SAMPLER_ID "
858 "CT:$COORD_TYPE_X$COORD_TYPE_Y$COORD_TYPE_Z$COORD_TYPE_W"),
860 NullALU>, TEX_WORD0, TEX_WORD1, TEX_WORD2 {
861 let Inst{31-0} = Word0;
862 let Inst{63-32} = Word1;
864 let TEX_INST = inst{4-0};
870 let FETCH_WHOLE_QUAD = 0;
872 let SAMPLER_INDEX_MODE = 0;
873 let RESOURCE_INDEX_MODE = 0;
878 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
882 def TEX_SAMPLE : R600_TEX <0x10, "TEX_SAMPLE">;
883 def TEX_SAMPLE_C : R600_TEX <0x18, "TEX_SAMPLE_C">;
884 def TEX_SAMPLE_L : R600_TEX <0x11, "TEX_SAMPLE_L">;
885 def TEX_SAMPLE_C_L : R600_TEX <0x19, "TEX_SAMPLE_C_L">;
886 def TEX_SAMPLE_LB : R600_TEX <0x12, "TEX_SAMPLE_LB">;
887 def TEX_SAMPLE_C_LB : R600_TEX <0x1A, "TEX_SAMPLE_C_LB">;
888 def TEX_LD : R600_TEX <0x03, "TEX_LD">;
889 def TEX_LDPTR : R600_TEX <0x03, "TEX_LDPTR"> {
892 def TEX_GET_TEXTURE_RESINFO : R600_TEX <0x04, "TEX_GET_TEXTURE_RESINFO">;
893 def TEX_GET_GRADIENTS_H : R600_TEX <0x07, "TEX_GET_GRADIENTS_H">;
894 def TEX_GET_GRADIENTS_V : R600_TEX <0x08, "TEX_GET_GRADIENTS_V">;
895 def TEX_SET_GRADIENTS_H : R600_TEX <0x0B, "TEX_SET_GRADIENTS_H">;
896 def TEX_SET_GRADIENTS_V : R600_TEX <0x0C, "TEX_SET_GRADIENTS_V">;
897 def TEX_SAMPLE_G : R600_TEX <0x14, "TEX_SAMPLE_G">;
898 def TEX_SAMPLE_C_G : R600_TEX <0x1C, "TEX_SAMPLE_C_G">;
900 defm : TexPattern<0, TEX_SAMPLE>;
901 defm : TexPattern<1, TEX_SAMPLE_C>;
902 defm : TexPattern<2, TEX_SAMPLE_L>;
903 defm : TexPattern<3, TEX_SAMPLE_C_L>;
904 defm : TexPattern<4, TEX_SAMPLE_LB>;
905 defm : TexPattern<5, TEX_SAMPLE_C_LB>;
906 defm : TexPattern<6, TEX_LD, v4i32>;
907 defm : TexPattern<7, TEX_GET_TEXTURE_RESINFO, v4i32>;
908 defm : TexPattern<8, TEX_GET_GRADIENTS_H>;
909 defm : TexPattern<9, TEX_GET_GRADIENTS_V>;
910 defm : TexPattern<10, TEX_LDPTR, v4i32>;
912 //===----------------------------------------------------------------------===//
913 // Helper classes for common instructions
914 //===----------------------------------------------------------------------===//
916 class MUL_LIT_Common <bits<5> inst> : R600_3OP <
921 class MULADD_Common <bits<5> inst> : R600_3OP <
926 class MULADD_IEEE_Common <bits<5> inst> : R600_3OP <
928 [(set f32:$dst, (fadd (fmul f32:$src0, f32:$src1), f32:$src2))]
931 class CNDE_Common <bits<5> inst> : R600_3OP <
933 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OEQ))]
936 class CNDGT_Common <bits<5> inst> : R600_3OP <
938 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGT))]
940 let Itinerary = VecALU;
943 class CNDGE_Common <bits<5> inst> : R600_3OP <
945 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGE))]
947 let Itinerary = VecALU;
951 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
952 class R600_VEC2OP<list<dag> pattern> : InstR600 <(outs R600_Reg32:$dst), (ins
954 UEM:$update_exec_mask_X, UP:$update_pred_X, WRITE:$write_X,
955 OMOD:$omod_X, REL:$dst_rel_X, CLAMP:$clamp_X,
956 R600_TReg32_X:$src0_X, NEG:$src0_neg_X, REL:$src0_rel_X, ABS:$src0_abs_X, SEL:$src0_sel_X,
957 R600_TReg32_X:$src1_X, NEG:$src1_neg_X, REL:$src1_rel_X, ABS:$src1_abs_X, SEL:$src1_sel_X,
958 R600_Pred:$pred_sel_X,
960 UEM:$update_exec_mask_Y, UP:$update_pred_Y, WRITE:$write_Y,
961 OMOD:$omod_Y, REL:$dst_rel_Y, CLAMP:$clamp_Y,
962 R600_TReg32_Y:$src0_Y, NEG:$src0_neg_Y, REL:$src0_rel_Y, ABS:$src0_abs_Y, SEL:$src0_sel_Y,
963 R600_TReg32_Y:$src1_Y, NEG:$src1_neg_Y, REL:$src1_rel_Y, ABS:$src1_abs_Y, SEL:$src1_sel_Y,
964 R600_Pred:$pred_sel_Y,
966 UEM:$update_exec_mask_Z, UP:$update_pred_Z, WRITE:$write_Z,
967 OMOD:$omod_Z, REL:$dst_rel_Z, CLAMP:$clamp_Z,
968 R600_TReg32_Z:$src0_Z, NEG:$src0_neg_Z, REL:$src0_rel_Z, ABS:$src0_abs_Z, SEL:$src0_sel_Z,
969 R600_TReg32_Z:$src1_Z, NEG:$src1_neg_Z, REL:$src1_rel_Z, ABS:$src1_abs_Z, SEL:$src1_sel_Z,
970 R600_Pred:$pred_sel_Z,
972 UEM:$update_exec_mask_W, UP:$update_pred_W, WRITE:$write_W,
973 OMOD:$omod_W, REL:$dst_rel_W, CLAMP:$clamp_W,
974 R600_TReg32_W:$src0_W, NEG:$src0_neg_W, REL:$src0_rel_W, ABS:$src0_abs_W, SEL:$src0_sel_W,
975 R600_TReg32_W:$src1_W, NEG:$src1_neg_W, REL:$src1_rel_W, ABS:$src1_abs_W, SEL:$src1_sel_W,
976 R600_Pred:$pred_sel_W,
977 LITERAL:$literal0, LITERAL:$literal1),
982 let UseNamedOperandTable = 1;
987 def DOT_4 : R600_VEC2OP<[(set R600_Reg32:$dst, (DOT4
988 R600_TReg32_X:$src0_X, R600_TReg32_X:$src1_X,
989 R600_TReg32_Y:$src0_Y, R600_TReg32_Y:$src1_Y,
990 R600_TReg32_Z:$src0_Z, R600_TReg32_Z:$src1_Z,
991 R600_TReg32_W:$src0_W, R600_TReg32_W:$src1_W))]>;
994 class DOT4_Common <bits<11> inst> : R600_2OP <inst, "DOT4", []>;
997 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
998 multiclass CUBE_Common <bits<11> inst> {
1000 def _pseudo : InstR600 <
1001 (outs R600_Reg128:$dst),
1002 (ins R600_Reg128:$src0),
1004 [(set v4f32:$dst, (int_AMDGPU_cube v4f32:$src0))],
1008 let UseNamedOperandTable = 1;
1011 def _real : R600_2OP <inst, "CUBE", []>;
1013 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
1015 class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1016 inst, "EXP_IEEE", fexp2
1018 let Itinerary = TransALU;
1021 class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper <
1022 inst, "FLT_TO_INT", fp_to_sint
1024 let Itinerary = TransALU;
1027 class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1028 inst, "INT_TO_FLT", sint_to_fp
1030 let Itinerary = TransALU;
1033 class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1034 inst, "FLT_TO_UINT", fp_to_uint
1036 let Itinerary = TransALU;
1039 class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1040 inst, "UINT_TO_FLT", uint_to_fp
1042 let Itinerary = TransALU;
1045 class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <
1046 inst, "LOG_CLAMPED", []
1049 class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1050 inst, "LOG_IEEE", flog2
1052 let Itinerary = TransALU;
1055 class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>;
1056 class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>;
1057 class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>;
1058 class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper <
1059 inst, "MULHI_INT", mulhs
1061 let Itinerary = TransALU;
1063 class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper <
1064 inst, "MULHI", mulhu
1066 let Itinerary = TransALU;
1068 class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper <
1069 inst, "MULLO_INT", mul
1071 let Itinerary = TransALU;
1073 class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []> {
1074 let Itinerary = TransALU;
1077 class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <
1078 inst, "RECIP_CLAMPED", []
1080 let Itinerary = TransALU;
1083 class RECIP_IEEE_Common <bits<11> inst> : R600_1OP <
1084 inst, "RECIP_IEEE", [(set f32:$dst, (fdiv FP_ONE, f32:$src0))]
1086 let Itinerary = TransALU;
1089 class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1090 inst, "RECIP_UINT", AMDGPUurecip
1092 let Itinerary = TransALU;
1095 class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper <
1096 inst, "RECIPSQRT_CLAMPED", int_AMDGPU_rsq
1098 let Itinerary = TransALU;
1101 class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP <
1102 inst, "RECIPSQRT_IEEE", []
1104 let Itinerary = TransALU;
1107 class SIN_Common <bits<11> inst> : R600_1OP <
1108 inst, "SIN", [(set f32:$dst, (SIN_HW f32:$src0))]>{
1110 let Itinerary = TransALU;
1113 class COS_Common <bits<11> inst> : R600_1OP <
1114 inst, "COS", [(set f32:$dst, (COS_HW f32:$src0))]> {
1116 let Itinerary = TransALU;
1119 def CLAMP_R600 : CLAMP <R600_Reg32>;
1120 def FABS_R600 : FABS<R600_Reg32>;
1121 def FNEG_R600 : FNEG<R600_Reg32>;
1123 //===----------------------------------------------------------------------===//
1124 // Helper patterns for complex intrinsics
1125 //===----------------------------------------------------------------------===//
1127 multiclass DIV_Common <InstR600 recip_ieee> {
1129 (int_AMDGPU_div f32:$src0, f32:$src1),
1130 (MUL_IEEE $src0, (recip_ieee $src1))
1134 (fdiv f32:$src0, f32:$src1),
1135 (MUL_IEEE $src0, (recip_ieee $src1))
1139 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee>
1141 (int_TGSI_lit_z f32:$src_x, f32:$src_y, f32:$src_w),
1142 (exp_ieee (mul_lit (log_clamped (MAX $src_y, (f32 ZERO))), $src_w, $src_x))
1146 class FROUNDPat<Instruction CNDGE> : Pat <
1147 (AMDGPUround f32:$x),
1148 (CNDGE (ADD (FNEG_R600 (f32 HALF)), (FRACT $x)), (CEIL $x), (FLOOR $x))
1152 //===----------------------------------------------------------------------===//
1153 // R600 / R700 Instructions
1154 //===----------------------------------------------------------------------===//
1156 let Predicates = [isR600] in {
1158 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
1159 def MULADD_r600 : MULADD_Common<0x10>;
1160 def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>;
1161 def CNDE_r600 : CNDE_Common<0x18>;
1162 def CNDGT_r600 : CNDGT_Common<0x19>;
1163 def CNDGE_r600 : CNDGE_Common<0x1A>;
1164 def DOT4_r600 : DOT4_Common<0x50>;
1165 defm CUBE_r600 : CUBE_Common<0x52>;
1166 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
1167 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
1168 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
1169 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
1170 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
1171 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
1172 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
1173 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
1174 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
1175 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
1176 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
1177 def SIN_r600 : SIN_Common<0x6E>;
1178 def COS_r600 : COS_Common<0x6F>;
1179 def ASHR_r600 : ASHR_Common<0x70>;
1180 def LSHR_r600 : LSHR_Common<0x71>;
1181 def LSHL_r600 : LSHL_Common<0x72>;
1182 def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
1183 def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
1184 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
1185 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
1186 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
1188 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
1189 def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL>;
1190 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
1192 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>;
1193 def : FROUNDPat <CNDGE_r600>;
1195 def R600_ExportSwz : ExportSwzInst {
1196 let Word1{20-17} = 0; // BURST_COUNT
1197 let Word1{21} = eop;
1198 let Word1{22} = 0; // VALID_PIXEL_MODE
1199 let Word1{30-23} = inst;
1200 let Word1{31} = 1; // BARRIER
1202 defm : ExportPattern<R600_ExportSwz, 39>;
1204 def R600_ExportBuf : ExportBufInst {
1205 let Word1{20-17} = 0; // BURST_COUNT
1206 let Word1{21} = eop;
1207 let Word1{22} = 0; // VALID_PIXEL_MODE
1208 let Word1{30-23} = inst;
1209 let Word1{31} = 1; // BARRIER
1211 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>;
1213 def CF_TC_R600 : CF_CLAUSE_R600<1, (ins i32imm:$ADDR, i32imm:$CNT),
1214 "TEX $CNT @$ADDR"> {
1217 def CF_VC_R600 : CF_CLAUSE_R600<2, (ins i32imm:$ADDR, i32imm:$CNT),
1218 "VTX $CNT @$ADDR"> {
1221 def WHILE_LOOP_R600 : CF_CLAUSE_R600<6, (ins i32imm:$ADDR),
1222 "LOOP_START_DX10 @$ADDR"> {
1226 def END_LOOP_R600 : CF_CLAUSE_R600<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1230 def LOOP_BREAK_R600 : CF_CLAUSE_R600<9, (ins i32imm:$ADDR),
1231 "LOOP_BREAK @$ADDR"> {
1235 def CF_CONTINUE_R600 : CF_CLAUSE_R600<8, (ins i32imm:$ADDR),
1236 "CONTINUE @$ADDR"> {
1240 def CF_JUMP_R600 : CF_CLAUSE_R600<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1241 "JUMP @$ADDR POP:$POP_COUNT"> {
1244 def CF_PUSH_ELSE_R600 : CF_CLAUSE_R600<12, (ins i32imm:$ADDR),
1245 "PUSH_ELSE @$ADDR"> {
1248 def CF_ELSE_R600 : CF_CLAUSE_R600<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1249 "ELSE @$ADDR POP:$POP_COUNT"> {
1252 def CF_CALL_FS_R600 : CF_CLAUSE_R600<19, (ins), "CALL_FS"> {
1257 def POP_R600 : CF_CLAUSE_R600<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1258 "POP @$ADDR POP:$POP_COUNT"> {
1261 def CF_END_R600 : CF_CLAUSE_R600<0, (ins), "CF_END"> {
1265 let END_OF_PROGRAM = 1;
1270 //===----------------------------------------------------------------------===//
1271 // R700 Only instructions
1272 //===----------------------------------------------------------------------===//
1274 let Predicates = [isR700] in {
1275 def SIN_r700 : SIN_Common<0x6E>;
1276 def COS_r700 : COS_Common<0x6F>;
1279 //===----------------------------------------------------------------------===//
1280 // Evergreen / Cayman store instructions
1281 //===----------------------------------------------------------------------===//
1283 let Predicates = [isEGorCayman] in {
1285 class CF_MEM_RAT_CACHELESS <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins,
1286 string name, list<dag> pattern>
1287 : EG_CF_RAT <0x57, rat_inst, rat_id, mask, (outs), ins,
1288 "MEM_RAT_CACHELESS "#name, pattern>;
1290 class CF_MEM_RAT <bits<6> rat_inst, bits<4> rat_id, dag ins, string name,
1292 : EG_CF_RAT <0x56, rat_inst, rat_id, 0xf /* mask */, (outs), ins,
1293 "MEM_RAT "#name, pattern>;
1295 def RAT_MSKOR : CF_MEM_RAT <0x11, 0,
1296 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr),
1297 "MSKOR $rw_gpr.XW, $index_gpr",
1298 [(mskor_global v4i32:$rw_gpr, i32:$index_gpr)]
1303 } // End Predicates = [isEGorCayman]
1306 //===----------------------------------------------------------------------===//
1307 // Evergreen Only instructions
1308 //===----------------------------------------------------------------------===//
1310 let Predicates = [isEG] in {
1312 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
1313 defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
1315 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
1316 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
1317 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
1318 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
1319 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
1320 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
1321 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
1322 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
1323 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
1324 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
1325 def SIN_eg : SIN_Common<0x8D>;
1326 def COS_eg : COS_Common<0x8E>;
1328 def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>;
1329 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>;
1331 //===----------------------------------------------------------------------===//
1332 // Memory read/write instructions
1333 //===----------------------------------------------------------------------===//
1335 let usesCustomInserter = 1 in {
1338 def RAT_WRITE_CACHELESS_32_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x1,
1339 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1340 "STORE_RAW $rw_gpr, $index_gpr, $eop",
1341 [(global_store i32:$rw_gpr, i32:$index_gpr)]
1345 def RAT_WRITE_CACHELESS_64_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x3,
1346 (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1347 "STORE_RAW $rw_gpr.XY, $index_gpr, $eop",
1348 [(global_store v2i32:$rw_gpr, i32:$index_gpr)]
1352 def RAT_WRITE_CACHELESS_128_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0xf,
1353 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1354 "STORE_RAW $rw_gpr.XYZW, $index_gpr, $eop",
1355 [(global_store v4i32:$rw_gpr, i32:$index_gpr)]
1358 } // End usesCustomInserter = 1
1360 class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
1361 : VTX_WORD0_eg, VTX_READ<name, buffer_id, outs, pattern> {
1366 let FETCH_WHOLE_QUAD = 0;
1367 let BUFFER_ID = buffer_id;
1369 // XXX: We can infer this field based on the SRC_GPR. This would allow us
1370 // to store vertex addresses in any channel, not just X.
1373 let Inst{31-0} = Word0;
1376 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
1377 : VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id,
1378 (outs R600_TReg32_X:$dst_gpr), pattern> {
1380 let MEGA_FETCH_COUNT = 1;
1382 let DST_SEL_Y = 7; // Masked
1383 let DST_SEL_Z = 7; // Masked
1384 let DST_SEL_W = 7; // Masked
1385 let DATA_FORMAT = 1; // FMT_8
1388 class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
1389 : VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id,
1390 (outs R600_TReg32_X:$dst_gpr), pattern> {
1391 let MEGA_FETCH_COUNT = 2;
1393 let DST_SEL_Y = 7; // Masked
1394 let DST_SEL_Z = 7; // Masked
1395 let DST_SEL_W = 7; // Masked
1396 let DATA_FORMAT = 5; // FMT_16
1400 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
1401 : VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id,
1402 (outs R600_TReg32_X:$dst_gpr), pattern> {
1404 let MEGA_FETCH_COUNT = 4;
1406 let DST_SEL_Y = 7; // Masked
1407 let DST_SEL_Z = 7; // Masked
1408 let DST_SEL_W = 7; // Masked
1409 let DATA_FORMAT = 0xD; // COLOR_32
1411 // This is not really necessary, but there were some GPU hangs that appeared
1412 // to be caused by ALU instructions in the next instruction group that wrote
1413 // to the $src_gpr registers of the VTX_READ.
1415 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
1416 // %T2_X<def> = MOV %ZERO
1417 //Adding this constraint prevents this from happening.
1418 let Constraints = "$src_gpr.ptr = $dst_gpr";
1421 class VTX_READ_64_eg <bits<8> buffer_id, list<dag> pattern>
1422 : VTX_READ_eg <"VTX_READ_64 $dst_gpr.XY, $src_gpr", buffer_id,
1423 (outs R600_Reg64:$dst_gpr), pattern> {
1425 let MEGA_FETCH_COUNT = 8;
1430 let DATA_FORMAT = 0x1D; // COLOR_32_32
1433 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
1434 : VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id,
1435 (outs R600_Reg128:$dst_gpr), pattern> {
1437 let MEGA_FETCH_COUNT = 16;
1442 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
1444 // XXX: Need to force VTX_READ_128 instructions to write to the same register
1445 // that holds its buffer address to avoid potential hangs. We can't use
1446 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst
1447 // registers are different sizes.
1450 //===----------------------------------------------------------------------===//
1451 // VTX Read from parameter memory space
1452 //===----------------------------------------------------------------------===//
1454 def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <0,
1455 [(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))]
1458 def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <0,
1459 [(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))]
1462 def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0,
1463 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1466 def VTX_READ_PARAM_64_eg : VTX_READ_64_eg <0,
1467 [(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1470 def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <0,
1471 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
1474 //===----------------------------------------------------------------------===//
1475 // VTX Read from global memory space
1476 //===----------------------------------------------------------------------===//
1479 def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1,
1480 [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))]
1483 def VTX_READ_GLOBAL_16_eg : VTX_READ_16_eg <1,
1484 [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))]
1488 def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1,
1489 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
1493 def VTX_READ_GLOBAL_64_eg : VTX_READ_64_eg <1,
1494 [(set v2i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
1498 def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
1499 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
1502 } // End Predicates = [isEG]
1504 //===----------------------------------------------------------------------===//
1505 // Evergreen / Cayman Instructions
1506 //===----------------------------------------------------------------------===//
1508 let Predicates = [isEGorCayman] in {
1510 // BFE_UINT - bit_extract, an optimization for mask and shift
1515 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
1520 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0
1521 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
1522 // (16,8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
1523 // (24,8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
1524 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
1525 [(set i32:$dst, (int_AMDIL_bit_extract_u32 i32:$src0, i32:$src1,
1529 // XXX: This pattern is broken, disabling for now. See comment in
1530 // AMDGPUInstructions.td for more info.
1531 // def : BFEPattern <BFE_UINT_eg>;
1533 def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", [], VecALU>;
1534 defm : BFIPatterns <BFI_INT_eg>;
1536 def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24",
1537 [(set i32:$dst, (add (mul U24:$src0, U24:$src1), i32:$src2))], VecALU
1539 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>;
1540 def : ROTRPattern <BIT_ALIGN_INT_eg>;
1542 def MULADD_eg : MULADD_Common<0x14>;
1543 def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>;
1544 def ASHR_eg : ASHR_Common<0x15>;
1545 def LSHR_eg : LSHR_Common<0x16>;
1546 def LSHL_eg : LSHL_Common<0x17>;
1547 def CNDE_eg : CNDE_Common<0x19>;
1548 def CNDGT_eg : CNDGT_Common<0x1A>;
1549 def CNDGE_eg : CNDGE_Common<0x1B>;
1550 def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
1551 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
1552 def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24",
1553 [(set i32:$dst, (mul U24:$src0, U24:$src1))], VecALU
1555 def DOT4_eg : DOT4_Common<0xBE>;
1556 defm CUBE_eg : CUBE_Common<0xC0>;
1558 let hasSideEffects = 1 in {
1559 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", [], VecALU>;
1562 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
1564 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
1566 let Itinerary = AnyALU;
1569 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
1571 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
1575 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
1577 def GROUP_BARRIER : InstR600 <
1578 (outs), (ins), " GROUP_BARRIER", [(int_AMDGPU_barrier_local)], AnyALU>,
1580 R600ALU_Word1_OP2 <0x54> {
1596 let bank_swizzle = 0;
1598 let update_exec_mask = 0;
1599 let update_pred = 0;
1601 let Inst{31-0} = Word0;
1602 let Inst{63-32} = Word1;
1607 //===----------------------------------------------------------------------===//
1609 //===----------------------------------------------------------------------===//
1610 class R600_LDS <bits<6> op, dag outs, dag ins, string asm,
1611 list<dag> pattern = []> :
1613 InstR600 <outs, ins, asm, pattern, XALU>,
1620 let Word1{27} = offset{0};
1621 let Word1{12} = offset{1};
1622 let Word1{28} = offset{2};
1623 let Word1{31} = offset{3};
1624 let Word0{12} = offset{4};
1625 let Word0{25} = offset{5};
1628 let Inst{31-0} = Word0;
1629 let Inst{63-32} = Word1;
1632 let HasNativeOperands = 1;
1633 let UseNamedOperandTable = 1;
1636 class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS <
1638 (outs R600_Reg32:$dst),
1639 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
1640 LAST:$last, R600_Pred:$pred_sel,
1641 BANK_SWIZZLE:$bank_swizzle),
1642 " "#name#" $last OQAP, $src0$src0_rel $pred_sel",
1652 let usesCustomInserter = 1;
1654 let DisableEncoding = "$dst";
1657 class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern,
1661 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
1662 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
1663 LAST:$last, R600_Pred:$pred_sel,
1664 BANK_SWIZZLE:$bank_swizzle),
1665 " "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel",
1669 field string BaseOp;
1676 class R600_LDS_1A1D_NORET <bits<6> lds_op, string name, list<dag> pattern> :
1677 R600_LDS_1A1D <lds_op, (outs), name, pattern> {
1681 class R600_LDS_1A1D_RET <bits<6> lds_op, string name, list<dag> pattern> :
1682 R600_LDS_1A1D <lds_op, (outs R600_Reg32:$dst), name##"_RET", pattern, "OQAP, "> {
1685 let usesCustomInserter = 1;
1686 let DisableEncoding = "$dst";
1690 class R600_LDS_1A2D <bits<6> lds_op, string name, list<dag> pattern> :
1694 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
1695 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
1696 R600_Reg32:$src2, REL:$src2_rel, SEL:$src2_sel,
1697 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle),
1698 " "#name# "$last $src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel",
1703 def LDS_ADD : R600_LDS_1A1D_NORET <0x0, "LDS_ADD", [] >;
1704 def LDS_SUB : R600_LDS_1A1D_NORET <0x1, "LDS_SUB", [] >;
1705 def LDS_WRITE : R600_LDS_1A1D_NORET <0xD, "LDS_WRITE",
1706 [(local_store (i32 R600_Reg32:$src1), R600_Reg32:$src0)]
1708 def LDS_BYTE_WRITE : R600_LDS_1A1D_NORET<0x12, "LDS_BYTE_WRITE",
1709 [(truncstorei8_local i32:$src1, i32:$src0)]
1711 def LDS_SHORT_WRITE : R600_LDS_1A1D_NORET<0x13, "LDS_SHORT_WRITE",
1712 [(truncstorei16_local i32:$src1, i32:$src0)]
1714 def LDS_ADD_RET : R600_LDS_1A1D_RET <0x20, "LDS_ADD",
1715 [(set i32:$dst, (atomic_load_add_local i32:$src0, i32:$src1))]
1717 def LDS_SUB_RET : R600_LDS_1A1D_RET <0x21, "LDS_SUB",
1718 [(set i32:$dst, (atomic_load_sub_local i32:$src0, i32:$src1))]
1720 def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET",
1721 [(set (i32 R600_Reg32:$dst), (local_load R600_Reg32:$src0))]
1723 def LDS_BYTE_READ_RET : R600_LDS_1A <0x36, "LDS_BYTE_READ_RET",
1724 [(set i32:$dst, (sextloadi8_local i32:$src0))]
1726 def LDS_UBYTE_READ_RET : R600_LDS_1A <0x37, "LDS_UBYTE_READ_RET",
1727 [(set i32:$dst, (az_extloadi8_local i32:$src0))]
1729 def LDS_SHORT_READ_RET : R600_LDS_1A <0x38, "LDS_SHORT_READ_RET",
1730 [(set i32:$dst, (sextloadi16_local i32:$src0))]
1732 def LDS_USHORT_READ_RET : R600_LDS_1A <0x39, "LDS_USHORT_READ_RET",
1733 [(set i32:$dst, (az_extloadi16_local i32:$src0))]
1736 // TRUNC is used for the FLT_TO_INT instructions to work around a
1737 // perceived problem where the rounding modes are applied differently
1738 // depending on the instruction and the slot they are in.
1740 // https://bugs.freedesktop.org/show_bug.cgi?id=50232
1741 // Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c
1743 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
1744 // which do not need to be truncated since the fp values are 0.0f or 1.0f.
1745 // We should look into handling these cases separately.
1746 def : Pat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>;
1748 def : Pat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>;
1751 def : SHA256MaPattern <BFI_INT_eg, XOR_INT>;
1753 def : FROUNDPat <CNDGE_eg>;
1755 def EG_ExportSwz : ExportSwzInst {
1756 let Word1{19-16} = 0; // BURST_COUNT
1757 let Word1{20} = 0; // VALID_PIXEL_MODE
1758 let Word1{21} = eop;
1759 let Word1{29-22} = inst;
1760 let Word1{30} = 0; // MARK
1761 let Word1{31} = 1; // BARRIER
1763 defm : ExportPattern<EG_ExportSwz, 83>;
1765 def EG_ExportBuf : ExportBufInst {
1766 let Word1{19-16} = 0; // BURST_COUNT
1767 let Word1{20} = 0; // VALID_PIXEL_MODE
1768 let Word1{21} = eop;
1769 let Word1{29-22} = inst;
1770 let Word1{30} = 0; // MARK
1771 let Word1{31} = 1; // BARRIER
1773 defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>;
1775 def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT),
1776 "TEX $COUNT @$ADDR"> {
1779 def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT),
1780 "VTX $COUNT @$ADDR"> {
1783 def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR),
1784 "LOOP_START_DX10 @$ADDR"> {
1788 def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1792 def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR),
1793 "LOOP_BREAK @$ADDR"> {
1797 def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR),
1798 "CONTINUE @$ADDR"> {
1802 def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1803 "JUMP @$ADDR POP:$POP_COUNT"> {
1806 def CF_PUSH_EG : CF_CLAUSE_EG<11, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1807 "PUSH @$ADDR POP:$POP_COUNT"> {
1810 def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1811 "ELSE @$ADDR POP:$POP_COUNT"> {
1814 def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> {
1819 def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1820 "POP @$ADDR POP:$POP_COUNT"> {
1823 def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> {
1827 let END_OF_PROGRAM = 1;
1830 } // End Predicates = [isEGorCayman]
1832 //===----------------------------------------------------------------------===//
1833 // Regist loads and stores - for indirect addressing
1834 //===----------------------------------------------------------------------===//
1836 defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>;
1838 //===----------------------------------------------------------------------===//
1839 // Cayman Instructions
1840 //===----------------------------------------------------------------------===//
1842 let Predicates = [isCayman] in {
1844 def MULADD_INT24_cm : R600_3OP <0x08, "MULADD_INT24",
1845 [(set i32:$dst, (add (mul I24:$src0, I24:$src1), i32:$src2))], VecALU
1847 def MUL_INT24_cm : R600_2OP <0x5B, "MUL_INT24",
1848 [(set i32:$dst, (mul I24:$src0, I24:$src1))], VecALU
1851 let isVector = 1 in {
1853 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
1855 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
1856 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
1857 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
1858 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
1859 def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>;
1860 def EXP_IEEE_cm : EXP_IEEE_Common<0x81>;
1861 def LOG_IEEE_cm : LOG_IEEE_Common<0x83>;
1862 def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>;
1863 def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>;
1864 def SIN_cm : SIN_Common<0x8D>;
1865 def COS_cm : COS_Common<0x8E>;
1866 } // End isVector = 1
1868 def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL>;
1870 defm DIV_cm : DIV_Common<RECIP_IEEE_cm>;
1872 // RECIP_UINT emulation for Cayman
1873 // The multiplication scales from [0,1] to the unsigned integer range
1875 (AMDGPUurecip i32:$src0),
1876 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)),
1877 (MOV_IMM_I32 CONST.FP_UINT_MAX_PLUS_1)))
1880 def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> {
1887 def : Pat<(fsqrt f32:$src), (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm $src))>;
1889 class RAT_STORE_DWORD <RegisterClass rc, ValueType vt, bits<4> mask> :
1890 CF_MEM_RAT_CACHELESS <0x14, 0, mask,
1891 (ins rc:$rw_gpr, R600_TReg32_X:$index_gpr),
1892 "STORE_DWORD $rw_gpr, $index_gpr",
1893 [(global_store vt:$rw_gpr, i32:$index_gpr)]> {
1894 let eop = 0; // This bit is not used on Cayman.
1897 def RAT_STORE_DWORD32 : RAT_STORE_DWORD <R600_TReg32_X, i32, 0x1>;
1898 def RAT_STORE_DWORD64 : RAT_STORE_DWORD <R600_Reg64, v2i32, 0x3>;
1899 def RAT_STORE_DWORD128 : RAT_STORE_DWORD <R600_Reg128, v4i32, 0xf>;
1901 class VTX_READ_cm <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
1902 : VTX_WORD0_cm, VTX_READ<name, buffer_id, outs, pattern> {
1907 let FETCH_WHOLE_QUAD = 0;
1908 let BUFFER_ID = buffer_id;
1910 // XXX: We can infer this field based on the SRC_GPR. This would allow us
1911 // to store vertex addresses in any channel, not just X.
1914 let STRUCTURED_READ = 0;
1916 let COALESCED_READ = 0;
1918 let Inst{31-0} = Word0;
1921 class VTX_READ_8_cm <bits<8> buffer_id, list<dag> pattern>
1922 : VTX_READ_cm <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id,
1923 (outs R600_TReg32_X:$dst_gpr), pattern> {
1926 let DST_SEL_Y = 7; // Masked
1927 let DST_SEL_Z = 7; // Masked
1928 let DST_SEL_W = 7; // Masked
1929 let DATA_FORMAT = 1; // FMT_8
1932 class VTX_READ_16_cm <bits<8> buffer_id, list<dag> pattern>
1933 : VTX_READ_cm <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id,
1934 (outs R600_TReg32_X:$dst_gpr), pattern> {
1936 let DST_SEL_Y = 7; // Masked
1937 let DST_SEL_Z = 7; // Masked
1938 let DST_SEL_W = 7; // Masked
1939 let DATA_FORMAT = 5; // FMT_16
1943 class VTX_READ_32_cm <bits<8> buffer_id, list<dag> pattern>
1944 : VTX_READ_cm <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id,
1945 (outs R600_TReg32_X:$dst_gpr), pattern> {
1948 let DST_SEL_Y = 7; // Masked
1949 let DST_SEL_Z = 7; // Masked
1950 let DST_SEL_W = 7; // Masked
1951 let DATA_FORMAT = 0xD; // COLOR_32
1953 // This is not really necessary, but there were some GPU hangs that appeared
1954 // to be caused by ALU instructions in the next instruction group that wrote
1955 // to the $src_gpr registers of the VTX_READ.
1957 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
1958 // %T2_X<def> = MOV %ZERO
1959 //Adding this constraint prevents this from happening.
1960 let Constraints = "$src_gpr.ptr = $dst_gpr";
1963 class VTX_READ_64_cm <bits<8> buffer_id, list<dag> pattern>
1964 : VTX_READ_cm <"VTX_READ_64 $dst_gpr, $src_gpr", buffer_id,
1965 (outs R600_Reg64:$dst_gpr), pattern> {
1971 let DATA_FORMAT = 0x1D; // COLOR_32_32
1974 class VTX_READ_128_cm <bits<8> buffer_id, list<dag> pattern>
1975 : VTX_READ_cm <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id,
1976 (outs R600_Reg128:$dst_gpr), pattern> {
1982 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
1984 // XXX: Need to force VTX_READ_128 instructions to write to the same register
1985 // that holds its buffer address to avoid potential hangs. We can't use
1986 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst
1987 // registers are different sizes.
1990 //===----------------------------------------------------------------------===//
1991 // VTX Read from parameter memory space
1992 //===----------------------------------------------------------------------===//
1993 def VTX_READ_PARAM_8_cm : VTX_READ_8_cm <0,
1994 [(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))]
1997 def VTX_READ_PARAM_16_cm : VTX_READ_16_cm <0,
1998 [(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))]
2001 def VTX_READ_PARAM_32_cm : VTX_READ_32_cm <0,
2002 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
2005 def VTX_READ_PARAM_64_cm : VTX_READ_64_cm <0,
2006 [(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
2009 def VTX_READ_PARAM_128_cm : VTX_READ_128_cm <0,
2010 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
2013 //===----------------------------------------------------------------------===//
2014 // VTX Read from global memory space
2015 //===----------------------------------------------------------------------===//
2018 def VTX_READ_GLOBAL_8_cm : VTX_READ_8_cm <1,
2019 [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))]
2022 def VTX_READ_GLOBAL_16_cm : VTX_READ_16_cm <1,
2023 [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))]
2027 def VTX_READ_GLOBAL_32_cm : VTX_READ_32_cm <1,
2028 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
2032 def VTX_READ_GLOBAL_64_cm : VTX_READ_64_cm <1,
2033 [(set v2i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
2037 def VTX_READ_GLOBAL_128_cm : VTX_READ_128_cm <1,
2038 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
2043 //===----------------------------------------------------------------------===//
2044 // Branch Instructions
2045 //===----------------------------------------------------------------------===//
2048 def IF_PREDICATE_SET : ILFormat<(outs), (ins GPRI32:$src),
2049 "IF_PREDICATE_SET $src", []>;
2051 //===----------------------------------------------------------------------===//
2052 // Pseudo instructions
2053 //===----------------------------------------------------------------------===//
2055 let isPseudo = 1 in {
2057 def PRED_X : InstR600 <
2058 (outs R600_Predicate_Bit:$dst),
2059 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
2061 let FlagOperandIdx = 3;
2064 let isTerminator = 1, isBranch = 1 in {
2065 def JUMP_COND : InstR600 <
2067 (ins brtarget:$target, R600_Predicate_Bit:$p),
2068 "JUMP $target ($p)",
2072 def JUMP : InstR600 <
2074 (ins brtarget:$target),
2079 let isPredicable = 1;
2083 } // End isTerminator = 1, isBranch = 1
2085 let usesCustomInserter = 1 in {
2087 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
2089 def MASK_WRITE : AMDGPUShaderInst <
2091 (ins R600_Reg32:$src),
2096 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 1
2100 (outs R600_Reg128:$dst),
2101 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
2102 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
2103 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
2104 [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2,
2105 imm:$resourceId, imm:$samplerId, imm:$textureTarget))],
2110 def TXD_SHADOW: InstR600 <
2111 (outs R600_Reg128:$dst),
2112 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
2113 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
2114 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
2115 [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2,
2116 imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))],
2121 } // End isPseudo = 1
2122 } // End usesCustomInserter = 1
2124 //===---------------------------------------------------------------------===//
2125 // Return instruction
2126 //===---------------------------------------------------------------------===//
2127 let isTerminator = 1, isReturn = 1, hasCtrlDep = 1,
2128 usesCustomInserter = 1 in {
2129 def RETURN : ILFormat<(outs), (ins variable_ops),
2130 "RETURN", [(IL_retflag)]>;
2134 //===----------------------------------------------------------------------===//
2135 // Constant Buffer Addressing Support
2136 //===----------------------------------------------------------------------===//
2138 let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
2139 def CONST_COPY : Instruction {
2140 let OutOperandList = (outs R600_Reg32:$dst);
2141 let InOperandList = (ins i32imm:$src);
2143 [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];
2144 let AsmString = "CONST_COPY";
2145 let neverHasSideEffects = 1;
2146 let isAsCheapAsAMove = 1;
2147 let Itinerary = NullALU;
2149 } // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
2151 def TEX_VTX_CONSTBUF :
2152 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "VTX_READ_eg $dst, $ptr",
2153 [(set v4i32:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$BUFFER_ID)))]>,
2154 VTX_WORD1_GPR, VTX_WORD0_eg {
2158 let FETCH_WHOLE_QUAD = 0;
2162 let USE_CONST_FIELDS = 0;
2163 let NUM_FORMAT_ALL = 2;
2164 let FORMAT_COMP_ALL = 1;
2165 let SRF_MODE_ALL = 1;
2166 let MEGA_FETCH_COUNT = 16;
2171 let DATA_FORMAT = 35;
2173 let Inst{31-0} = Word0;
2174 let Inst{63-32} = Word1;
2176 // LLVM can only encode 64-bit instructions, so these fields are manually
2177 // encoded in R600CodeEmitter
2180 // bits<2> ENDIAN_SWAP = 0;
2181 // bits<1> CONST_BUF_NO_STRIDE = 0;
2182 // bits<1> MEGA_FETCH = 0;
2183 // bits<1> ALT_CONST = 0;
2184 // bits<2> BUFFER_INDEX_MODE = 0;
2188 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
2189 // is done in R600CodeEmitter
2191 // Inst{79-64} = OFFSET;
2192 // Inst{81-80} = ENDIAN_SWAP;
2193 // Inst{82} = CONST_BUF_NO_STRIDE;
2194 // Inst{83} = MEGA_FETCH;
2195 // Inst{84} = ALT_CONST;
2196 // Inst{86-85} = BUFFER_INDEX_MODE;
2197 // Inst{95-86} = 0; Reserved
2199 // VTX_WORD3 (Padding)
2201 // Inst{127-96} = 0;
2206 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr",
2207 [(set v4f32:$dst, (int_R600_load_texbuf ADDRGA_VAR_OFFSET:$ptr, imm:$BUFFER_ID))]>,
2208 VTX_WORD1_GPR, VTX_WORD0_eg {
2212 let FETCH_WHOLE_QUAD = 0;
2216 let USE_CONST_FIELDS = 1;
2217 let NUM_FORMAT_ALL = 0;
2218 let FORMAT_COMP_ALL = 0;
2219 let SRF_MODE_ALL = 1;
2220 let MEGA_FETCH_COUNT = 16;
2225 let DATA_FORMAT = 0;
2227 let Inst{31-0} = Word0;
2228 let Inst{63-32} = Word1;
2230 // LLVM can only encode 64-bit instructions, so these fields are manually
2231 // encoded in R600CodeEmitter
2234 // bits<2> ENDIAN_SWAP = 0;
2235 // bits<1> CONST_BUF_NO_STRIDE = 0;
2236 // bits<1> MEGA_FETCH = 0;
2237 // bits<1> ALT_CONST = 0;
2238 // bits<2> BUFFER_INDEX_MODE = 0;
2242 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
2243 // is done in R600CodeEmitter
2245 // Inst{79-64} = OFFSET;
2246 // Inst{81-80} = ENDIAN_SWAP;
2247 // Inst{82} = CONST_BUF_NO_STRIDE;
2248 // Inst{83} = MEGA_FETCH;
2249 // Inst{84} = ALT_CONST;
2250 // Inst{86-85} = BUFFER_INDEX_MODE;
2251 // Inst{95-86} = 0; Reserved
2253 // VTX_WORD3 (Padding)
2255 // Inst{127-96} = 0;
2261 //===--------------------------------------------------------------------===//
2262 // Instructions support
2263 //===--------------------------------------------------------------------===//
2264 //===---------------------------------------------------------------------===//
2265 // Custom Inserter for Branches and returns, this eventually will be a
2267 //===---------------------------------------------------------------------===//
2268 let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in {
2269 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
2270 "; Pseudo unconditional branch instruction",
2272 defm BRANCH_COND : BranchConditional<IL_brcond, R600_Reg32, R600_Reg32>;
2275 //===---------------------------------------------------------------------===//
2276 // Flow and Program control Instructions
2277 //===---------------------------------------------------------------------===//
2278 let isTerminator=1 in {
2279 def SWITCH : ILFormat< (outs), (ins GPRI32:$src),
2280 !strconcat("SWITCH", " $src"), []>;
2281 def CASE : ILFormat< (outs), (ins GPRI32:$src),
2282 !strconcat("CASE", " $src"), []>;
2283 def BREAK : ILFormat< (outs), (ins),
2285 def CONTINUE : ILFormat< (outs), (ins),
2287 def DEFAULT : ILFormat< (outs), (ins),
2289 def ELSE : ILFormat< (outs), (ins),
2291 def ENDSWITCH : ILFormat< (outs), (ins),
2293 def ENDMAIN : ILFormat< (outs), (ins),
2295 def END : ILFormat< (outs), (ins),
2297 def ENDFUNC : ILFormat< (outs), (ins),
2299 def ENDIF : ILFormat< (outs), (ins),
2301 def WHILELOOP : ILFormat< (outs), (ins),
2303 def ENDLOOP : ILFormat< (outs), (ins),
2305 def FUNC : ILFormat< (outs), (ins),
2307 def RETDYN : ILFormat< (outs), (ins),
2309 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2310 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">;
2311 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2312 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">;
2313 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2314 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">;
2315 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2316 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">;
2317 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2318 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">;
2319 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2320 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">;
2321 defm IFC : BranchInstr2<"IFC">;
2322 defm BREAKC : BranchInstr2<"BREAKC">;
2323 defm CONTINUEC : BranchInstr2<"CONTINUEC">;
2326 //===----------------------------------------------------------------------===//
2328 //===----------------------------------------------------------------------===//
2330 // CND*_INT Pattterns for f32 True / False values
2332 class CND_INT_f32 <InstR600 cnd, CondCode cc> : Pat <
2333 (selectcc i32:$src0, 0, f32:$src1, f32:$src2, cc),
2334 (cnd $src0, $src1, $src2)
2337 def : CND_INT_f32 <CNDE_INT, SETEQ>;
2338 def : CND_INT_f32 <CNDGT_INT, SETGT>;
2339 def : CND_INT_f32 <CNDGE_INT, SETGE>;
2341 //CNDGE_INT extra pattern
2343 (selectcc i32:$src0, -1, i32:$src1, i32:$src2, COND_SGT),
2344 (CNDGE_INT $src0, $src1, $src2)
2350 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
2354 (int_AMDGPU_kill f32:$src0),
2355 (MASK_WRITE (KILLGT (f32 ZERO), $src0))
2358 def : Extract_Element <f32, v4f32, 0, sub0>;
2359 def : Extract_Element <f32, v4f32, 1, sub1>;
2360 def : Extract_Element <f32, v4f32, 2, sub2>;
2361 def : Extract_Element <f32, v4f32, 3, sub3>;
2363 def : Insert_Element <f32, v4f32, 0, sub0>;
2364 def : Insert_Element <f32, v4f32, 1, sub1>;
2365 def : Insert_Element <f32, v4f32, 2, sub2>;
2366 def : Insert_Element <f32, v4f32, 3, sub3>;
2368 def : Extract_Element <i32, v4i32, 0, sub0>;
2369 def : Extract_Element <i32, v4i32, 1, sub1>;
2370 def : Extract_Element <i32, v4i32, 2, sub2>;
2371 def : Extract_Element <i32, v4i32, 3, sub3>;
2373 def : Insert_Element <i32, v4i32, 0, sub0>;
2374 def : Insert_Element <i32, v4i32, 1, sub1>;
2375 def : Insert_Element <i32, v4i32, 2, sub2>;
2376 def : Insert_Element <i32, v4i32, 3, sub3>;
2378 def : Extract_Element <f32, v2f32, 0, sub0>;
2379 def : Extract_Element <f32, v2f32, 1, sub1>;
2381 def : Insert_Element <f32, v2f32, 0, sub0>;
2382 def : Insert_Element <f32, v2f32, 1, sub1>;
2384 def : Extract_Element <i32, v2i32, 0, sub0>;
2385 def : Extract_Element <i32, v2i32, 1, sub1>;
2387 def : Insert_Element <i32, v2i32, 0, sub0>;
2388 def : Insert_Element <i32, v2i32, 1, sub1>;
2390 // bitconvert patterns
2392 def : BitConvert <i32, f32, R600_Reg32>;
2393 def : BitConvert <f32, i32, R600_Reg32>;
2394 def : BitConvert <v2f32, v2i32, R600_Reg64>;
2395 def : BitConvert <v2i32, v2f32, R600_Reg64>;
2396 def : BitConvert <v4f32, v4i32, R600_Reg128>;
2397 def : BitConvert <v4i32, v4f32, R600_Reg128>;
2399 // DWORDADDR pattern
2400 def : DwordAddrPat <i32, R600_Reg32>;
2402 } // End isR600toCayman Predicate
2404 def getLDSNoRetOp : InstrMapping {
2405 let FilterClass = "R600_LDS_1A1D";
2406 let RowFields = ["BaseOp"];
2407 let ColFields = ["DisableEncoding"];
2408 let KeyCol = ["$dst"];
2409 let ValueCols = [[""""]];