1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // R600 Tablegen instruction definitions
12 //===----------------------------------------------------------------------===//
14 include "R600Intrinsics.td"
16 class InstR600 <bits<11> inst, dag outs, dag ins, string asm, list<dag> pattern,
18 : AMDGPUInst <outs, ins, asm, pattern> {
24 bits<2> FlagOperandIdx = 0;
27 bit HasNativeOperands = 0;
29 bits<11> op_code = inst;
31 let Namespace = "AMDGPU";
32 let OutOperandList = outs;
33 let InOperandList = ins;
35 let Pattern = pattern;
38 let TSFlags{4} = Trig;
41 // Vector instructions are instructions that must fill all slots in an
43 let TSFlags{6} = isVector;
44 let TSFlags{8-7} = FlagOperandIdx;
45 let TSFlags{9} = HasNativeOperands;
46 let TSFlags{10} = Op1;
47 let TSFlags{11} = Op2;
50 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
51 AMDGPUInst <outs, ins, asm, pattern> {
54 let Namespace = "AMDGPU";
57 def MEMxi : Operand<iPTR> {
58 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
59 let PrintMethod = "printMemOperand";
62 def MEMrr : Operand<iPTR> {
63 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
66 // Operands for non-registers
68 class InstFlag<string PM = "printOperand", int Default = 0>
69 : OperandWithDefaultOps <i32, (ops (i32 Default))> {
73 // src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers
74 def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> {
75 let PrintMethod = "printSel";
78 def LITERAL : InstFlag<"printLiteral">;
80 def WRITE : InstFlag <"printWrite", 1>;
81 def OMOD : InstFlag <"printOMOD">;
82 def REL : InstFlag <"printRel">;
83 def CLAMP : InstFlag <"printClamp">;
84 def NEG : InstFlag <"printNeg">;
85 def ABS : InstFlag <"printAbs">;
86 def UEM : InstFlag <"printUpdateExecMask">;
87 def UP : InstFlag <"printUpdatePred">;
89 // XXX: The r600g finalizer in Mesa expects last to be one in most cases.
90 // Once we start using the packetizer in this backend we should have this
92 def LAST : InstFlag<"printLast", 1>;
94 def FRAMEri : Operand<iPTR> {
95 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index);
98 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
99 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
100 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
101 def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>;
102 def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>;
103 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
105 class R600ALU_Word0 {
106 field bits<32> Word0;
114 bits<3> index_mode = 0;
118 bits<9> src0_sel = src0{8-0};
119 bits<2> src0_chan = src0{10-9};
120 bits<9> src1_sel = src1{8-0};
121 bits<2> src1_chan = src1{10-9};
123 let Word0{8-0} = src0_sel;
124 let Word0{9} = src0_rel;
125 let Word0{11-10} = src0_chan;
126 let Word0{12} = src0_neg;
127 let Word0{21-13} = src1_sel;
128 let Word0{22} = src1_rel;
129 let Word0{24-23} = src1_chan;
130 let Word0{25} = src1_neg;
131 let Word0{28-26} = index_mode;
132 let Word0{30-29} = pred_sel;
133 let Word0{31} = last;
136 class R600ALU_Word1 {
137 field bits<32> Word1;
140 bits<3> bank_swizzle = 0;
144 bits<7> dst_sel = dst{6-0};
145 bits<2> dst_chan = dst{10-9};
147 let Word1{20-18} = bank_swizzle;
148 let Word1{27-21} = dst_sel;
149 let Word1{28} = dst_rel;
150 let Word1{30-29} = dst_chan;
151 let Word1{31} = clamp;
154 class R600ALU_Word1_OP2 <bits<11> alu_inst> : R600ALU_Word1{
158 bits<1> update_exec_mask;
163 let Word1{0} = src0_abs;
164 let Word1{1} = src1_abs;
165 let Word1{2} = update_exec_mask;
166 let Word1{3} = update_pred;
167 let Word1{4} = write;
168 let Word1{6-5} = omod;
169 let Word1{17-7} = alu_inst;
172 class R600ALU_Word1_OP3 <bits<5> alu_inst> : R600ALU_Word1{
178 bits<9> src2_sel = src2{8-0};
179 bits<2> src2_chan = src2{10-9};
181 let Word1{8-0} = src2_sel;
182 let Word1{9} = src2_rel;
183 let Word1{11-10} = src2_chan;
184 let Word1{12} = src2_neg;
185 let Word1{17-13} = alu_inst;
189 field bits<32> Word0;
193 bits<1> FETCH_WHOLE_QUAD;
197 bits<6> MEGA_FETCH_COUNT;
199 let Word0{4-0} = VC_INST;
200 let Word0{6-5} = FETCH_TYPE;
201 let Word0{7} = FETCH_WHOLE_QUAD;
202 let Word0{15-8} = BUFFER_ID;
203 let Word0{22-16} = SRC_GPR;
204 let Word0{23} = SRC_REL;
205 let Word0{25-24} = SRC_SEL_X;
206 let Word0{31-26} = MEGA_FETCH_COUNT;
209 class VTX_WORD1_GPR {
210 field bits<32> Word1;
217 bits<1> USE_CONST_FIELDS;
219 bits<2> NUM_FORMAT_ALL;
220 bits<1> FORMAT_COMP_ALL;
221 bits<1> SRF_MODE_ALL;
223 let Word1{6-0} = DST_GPR;
224 let Word1{7} = DST_REL;
225 let Word1{8} = 0; // Reserved
226 let Word1{11-9} = DST_SEL_X;
227 let Word1{14-12} = DST_SEL_Y;
228 let Word1{17-15} = DST_SEL_Z;
229 let Word1{20-18} = DST_SEL_W;
230 let Word1{21} = USE_CONST_FIELDS;
231 let Word1{27-22} = DATA_FORMAT;
232 let Word1{29-28} = NUM_FORMAT_ALL;
233 let Word1{30} = FORMAT_COMP_ALL;
234 let Word1{31} = SRF_MODE_ALL;
238 field bits<32> Word0;
242 bits<1> FETCH_WHOLE_QUAD;
247 bits<2> RESOURCE_INDEX_MODE;
248 bits<2> SAMPLER_INDEX_MODE;
250 let Word0{4-0} = TEX_INST;
251 let Word0{6-5} = INST_MOD;
252 let Word0{7} = FETCH_WHOLE_QUAD;
253 let Word0{15-8} = RESOURCE_ID;
254 let Word0{22-16} = SRC_GPR;
255 let Word0{23} = SRC_REL;
256 let Word0{24} = ALT_CONST;
257 let Word0{26-25} = RESOURCE_INDEX_MODE;
258 let Word0{28-27} = SAMPLER_INDEX_MODE;
262 field bits<32> Word1;
271 bits<1> COORD_TYPE_X;
272 bits<1> COORD_TYPE_Y;
273 bits<1> COORD_TYPE_Z;
274 bits<1> COORD_TYPE_W;
276 let Word1{6-0} = DST_GPR;
277 let Word1{7} = DST_REL;
278 let Word1{11-9} = DST_SEL_X;
279 let Word1{14-12} = DST_SEL_Y;
280 let Word1{17-15} = DST_SEL_Z;
281 let Word1{20-18} = DST_SEL_W;
282 let Word1{27-21} = LOD_BIAS;
283 let Word1{28} = COORD_TYPE_X;
284 let Word1{29} = COORD_TYPE_Y;
285 let Word1{30} = COORD_TYPE_Z;
286 let Word1{31} = COORD_TYPE_W;
290 field bits<32> Word2;
301 let Word2{4-0} = OFFSET_X;
302 let Word2{9-5} = OFFSET_Y;
303 let Word2{14-10} = OFFSET_Z;
304 let Word2{19-15} = SAMPLER_ID;
305 let Word2{22-20} = SRC_SEL_X;
306 let Word2{25-23} = SRC_SEL_Y;
307 let Word2{28-26} = SRC_SEL_Z;
308 let Word2{31-29} = SRC_SEL_W;
312 XXX: R600 subtarget uses a slightly different encoding than the other
313 subtargets. We currently handle this in R600MCCodeEmitter, but we may
314 want to use these instruction classes in the future.
316 class R600ALU_Word1_OP2_r600 : R600ALU_Word1_OP2 {
321 let Inst{37} = fog_merge;
322 let Inst{39-38} = omod;
323 let Inst{49-40} = alu_inst;
326 class R600ALU_Word1_OP2_r700 : R600ALU_Word1_OP2 {
330 let Inst{38-37} = omod;
331 let Inst{49-39} = alu_inst;
335 def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
339 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
341 // Class for instructions with only one source register.
342 // If you add new ins to this instruction, make sure they are listed before
343 // $literal, because the backend currently assumes that the last operand is
344 // a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in
345 // R600Defines.h, R600InstrInfo::buildDefaultInstruction(),
346 // and R600InstrInfo::getOperandIdx().
347 class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
348 InstrItinClass itin = AnyALU> :
350 (outs R600_Reg32:$dst),
351 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
352 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
353 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
354 !strconcat(" ", opName,
355 "$clamp $dst$write$dst_rel$omod, "
356 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
357 "$literal $pred_sel$last"),
361 R600ALU_Word1_OP2 <inst> {
367 let update_exec_mask = 0;
369 let HasNativeOperands = 1;
371 let DisableEncoding = "$literal";
373 let Inst{31-0} = Word0;
374 let Inst{63-32} = Word1;
377 class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
378 InstrItinClass itin = AnyALU> :
379 R600_1OP <inst, opName,
380 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))]
383 // If you add our change the operands for R600_2OP instructions, you must
384 // also update the R600Op2OperandIndex::ROI enum in R600Defines.h,
385 // R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx().
386 class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
387 InstrItinClass itin = AnyALU> :
389 (outs R600_Reg32:$dst),
390 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
391 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
392 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
393 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
394 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
395 !strconcat(" ", opName,
396 "$clamp $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
397 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
398 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
399 "$literal $pred_sel$last"),
403 R600ALU_Word1_OP2 <inst> {
405 let HasNativeOperands = 1;
407 let DisableEncoding = "$literal";
409 let Inst{31-0} = Word0;
410 let Inst{63-32} = Word1;
413 class R600_2OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
414 InstrItinClass itim = AnyALU> :
415 R600_2OP <inst, opName,
416 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
420 // If you add our change the operands for R600_3OP instructions, you must
421 // also update the R600Op3OperandIndex::ROI enum in R600Defines.h,
422 // R600InstrInfo::buildDefaultInstruction(), and
423 // R600InstrInfo::getOperandIdx().
424 class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
425 InstrItinClass itin = AnyALU> :
427 (outs R600_Reg32:$dst),
428 (ins REL:$dst_rel, CLAMP:$clamp,
429 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
430 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
431 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,
432 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
433 !strconcat(" ", opName, "$clamp $dst$dst_rel, "
434 "$src0_neg$src0$src0_rel, "
435 "$src1_neg$src1$src1_rel, "
436 "$src2_neg$src2$src2_rel, "
437 "$literal $pred_sel$last"),
441 R600ALU_Word1_OP3<inst>{
443 let HasNativeOperands = 1;
444 let DisableEncoding = "$literal";
447 let Inst{31-0} = Word0;
448 let Inst{63-32} = Word1;
451 class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern,
452 InstrItinClass itin = VecALU> :
454 (outs R600_Reg32:$dst),
460 class R600_TEX <bits<11> inst, string opName, list<dag> pattern,
461 InstrItinClass itin = AnyALU> :
463 (outs R600_Reg128:$DST_GPR),
464 (ins R600_Reg128:$SRC_GPR, i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID, i32imm:$textureTarget),
465 !strconcat(opName, "$DST_GPR, $SRC_GPR, $RESOURCE_ID, $SAMPLER_ID, $textureTarget"),
467 itin>, TEX_WORD0, TEX_WORD1, TEX_WORD2 {
468 let Inst{31-0} = Word0;
469 let Inst{63-32} = Word1;
471 let TEX_INST = inst{4-0};
481 let FETCH_WHOLE_QUAD = 0;
483 let SAMPLER_INDEX_MODE = 0;
485 let COORD_TYPE_X = 0;
486 let COORD_TYPE_Y = 0;
487 let COORD_TYPE_Z = 0;
488 let COORD_TYPE_W = 0;
491 } // End mayLoad = 1, mayStore = 0, hasSideEffects = 0
493 def TEX_SHADOW : PatLeaf<
495 [{uint32_t TType = (uint32_t)N->getZExtValue();
496 return (TType >= 6 && TType <= 8) || (TType >= 11 && TType <= 13);
500 def TEX_RECT : PatLeaf<
502 [{uint32_t TType = (uint32_t)N->getZExtValue();
507 def TEX_ARRAY : PatLeaf<
509 [{uint32_t TType = (uint32_t)N->getZExtValue();
510 return TType == 9 || TType == 10 || TType == 15 || TType == 16;
514 def TEX_SHADOW_ARRAY : PatLeaf<
516 [{uint32_t TType = (uint32_t)N->getZExtValue();
517 return TType == 11 || TType == 12 || TType == 17;
521 class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
522 dag ins, string asm, list<dag> pattern> :
523 InstR600ISA <outs, ins, asm, pattern> {
540 // CF_ALLOC_EXPORT_WORD0_RAT
541 let Inst{3-0} = rat_id;
542 let Inst{9-4} = rat_inst;
543 let Inst{10} = 0; // Reserved
544 let Inst{12-11} = RIM;
545 let Inst{14-13} = TYPE;
546 let Inst{21-15} = RW_GPR;
547 let Inst{22} = RW_REL;
548 let Inst{29-23} = INDEX_GPR;
549 let Inst{31-30} = ELEM_SIZE;
551 // CF_ALLOC_EXPORT_WORD1_BUF
552 let Inst{43-32} = ARRAY_SIZE;
553 let Inst{47-44} = COMP_MASK;
554 let Inst{51-48} = BURST_COUNT;
557 let Inst{61-54} = cf_inst;
559 let Inst{63} = BARRIER;
562 class LoadParamFrag <PatFrag load_type> : PatFrag <
563 (ops node:$ptr), (load_type node:$ptr),
564 [{ return isParamLoad(dyn_cast<LoadSDNode>(N)); }]
567 def load_param : LoadParamFrag<load>;
568 def load_param_zexti8 : LoadParamFrag<zextloadi8>;
569 def load_param_zexti16 : LoadParamFrag<zextloadi16>;
571 def isR600 : Predicate<"Subtarget.device()"
572 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX">;
573 def isR700 : Predicate<"Subtarget.device()"
574 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX &&"
575 "Subtarget.device()->getDeviceFlag()"
576 ">= OCL_DEVICE_RV710">;
577 def isEG : Predicate<
578 "Subtarget.device()->getGeneration() >= AMDGPUDeviceInfo::HD5XXX && "
579 "Subtarget.device()->getGeneration() < AMDGPUDeviceInfo::HD7XXX && "
580 "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">;
582 def isCayman : Predicate<"Subtarget.device()"
583 "->getDeviceFlag() == OCL_DEVICE_CAYMAN">;
584 def isEGorCayman : Predicate<"Subtarget.device()"
585 "->getGeneration() == AMDGPUDeviceInfo::HD5XXX"
586 "|| Subtarget.device()->getGeneration() =="
587 "AMDGPUDeviceInfo::HD6XXX">;
589 def isR600toCayman : Predicate<
590 "Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX">;
592 //===----------------------------------------------------------------------===//
594 //===----------------------------------------------------------------------===//
596 def INTERP_PAIR_XY : AMDGPUShaderInst <
597 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1),
598 (ins i32imm:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
599 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
602 def INTERP_PAIR_ZW : AMDGPUShaderInst <
603 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1),
604 (ins i32imm:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
605 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",
608 def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS",
609 SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>,
613 //===----------------------------------------------------------------------===//
614 // Interpolation Instructions
615 //===----------------------------------------------------------------------===//
617 def INTERP_VEC_LOAD : AMDGPUShaderInst <
618 (outs R600_Reg128:$dst),
620 "INTERP_LOAD $src0 : $dst",
623 def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> {
624 let bank_swizzle = 5;
627 def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> {
628 let bank_swizzle = 5;
631 def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>;
633 //===----------------------------------------------------------------------===//
634 // Export Instructions
635 //===----------------------------------------------------------------------===//
637 def ExportType : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
639 def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType,
640 [SDNPHasChain, SDNPSideEffect]>;
643 field bits<32> Word0;
650 let Word0{12-0} = arraybase;
651 let Word0{14-13} = type;
652 let Word0{21-15} = gpr;
653 let Word0{22} = 0; // RW_REL
654 let Word0{29-23} = 0; // INDEX_GPR
655 let Word0{31-30} = elem_size;
658 class ExportSwzWord1 {
659 field bits<32> Word1;
668 let Word1{2-0} = sw_x;
669 let Word1{5-3} = sw_y;
670 let Word1{8-6} = sw_z;
671 let Word1{11-9} = sw_w;
674 class ExportBufWord1 {
675 field bits<32> Word1;
682 let Word1{11-0} = arraySize;
683 let Word1{15-12} = compMask;
686 multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
687 def : Pat<(int_R600_store_pixel_depth R600_Reg32:$reg),
689 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
690 0, 61, 0, 7, 7, 7, cf_inst, 0)
693 def : Pat<(int_R600_store_pixel_stencil R600_Reg32:$reg),
695 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
696 0, 61, 7, 0, 7, 7, cf_inst, 0)
699 def : Pat<(int_R600_store_dummy (i32 imm:$type)),
701 (v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0)
704 def : Pat<(int_R600_store_dummy 1),
706 (v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0)
709 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
710 (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)),
711 (ExportInst R600_Reg128:$src, imm:$type, imm:$base,
712 imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0)
717 multiclass SteamOutputExportPattern<Instruction ExportInst,
718 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> {
720 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
721 (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)),
722 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
723 4095, imm:$mask, buf0inst, 0)>;
725 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
726 (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)),
727 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
728 4095, imm:$mask, buf1inst, 0)>;
730 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
731 (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)),
732 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
733 4095, imm:$mask, buf2inst, 0)>;
735 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
736 (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)),
737 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
738 4095, imm:$mask, buf3inst, 0)>;
741 // Export Instructions should not be duplicated by TailDuplication pass
742 // (which assumes that duplicable instruction are affected by exec mask)
743 let usesCustomInserter = 1, isNotDuplicable = 1 in {
745 class ExportSwzInst : InstR600ISA<(
747 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
748 i32imm:$sw_x, i32imm:$sw_y, i32imm:$sw_z, i32imm:$sw_w, i32imm:$inst,
750 !strconcat("EXPORT", " $gpr"),
751 []>, ExportWord0, ExportSwzWord1 {
753 let Inst{31-0} = Word0;
754 let Inst{63-32} = Word1;
757 } // End usesCustomInserter = 1
759 class ExportBufInst : InstR600ISA<(
761 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
762 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop),
763 !strconcat("EXPORT", " $gpr"),
764 []>, ExportWord0, ExportBufWord1 {
766 let Inst{31-0} = Word0;
767 let Inst{63-32} = Word1;
770 //===----------------------------------------------------------------------===//
771 // Control Flow Instructions
772 //===----------------------------------------------------------------------===//
775 field bits<32> Word0;
778 bits<4> KCACHE_BANK0;
779 bits<4> KCACHE_BANK1;
780 bits<2> KCACHE_MODE0;
782 let Word0{21-0} = ADDR;
783 let Word0{25-22} = KCACHE_BANK0;
784 let Word0{29-26} = KCACHE_BANK1;
785 let Word0{31-30} = KCACHE_MODE0;
789 field bits<32> Word1;
791 bits<2> KCACHE_MODE1;
792 bits<8> KCACHE_ADDR0;
793 bits<8> KCACHE_ADDR1;
797 bits<1> WHOLE_QUAD_MODE;
800 let Word1{1-0} = KCACHE_MODE1;
801 let Word1{9-2} = KCACHE_ADDR0;
802 let Word1{17-10} = KCACHE_ADDR1;
803 let Word1{24-18} = COUNT;
804 let Word1{25} = ALT_CONST;
805 let Word1{29-26} = CF_INST;
806 let Word1{30} = WHOLE_QUAD_MODE;
807 let Word1{31} = BARRIER;
810 class ALU_CLAUSE<bits<4> inst, string OpName> : AMDGPUInst <(outs),
811 (ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1, i32imm:$KCACHE_MODE0, i32imm:$KCACHE_MODE1,
812 i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1, i32imm:$COUNT),
813 !strconcat(OpName, " $COUNT, @$ADDR, "
814 "KC0[CB$KCACHE_BANK0:$KCACHE_ADDR0-$KCACHE_ADDR0+32]"
815 ", KC1[CB$KCACHE_BANK1:$KCACHE_ADDR1-$KCACHE_ADDR1+32]"),
816 [] >, CF_ALU_WORD0, CF_ALU_WORD1 {
821 let WHOLE_QUAD_MODE = 0;
824 let Inst{31-0} = Word0;
825 let Inst{63-32} = Word1;
828 class CF_WORD0_R600 {
829 field bits<32> Word0;
836 class CF_WORD1_R600 {
837 field bits<32> Word1;
845 bits<1> END_OF_PROGRAM;
846 bits<1> VALID_PIXEL_MODE;
848 bits<1> WHOLE_QUAD_MODE;
851 let Word1{2-0} = POP_COUNT;
852 let Word1{7-3} = CF_CONST;
853 let Word1{9-8} = COND;
854 let Word1{12-10} = COUNT;
855 let Word1{18-13} = CALL_COUNT;
856 let Word1{19} = COUNT_3;
857 let Word1{21} = END_OF_PROGRAM;
858 let Word1{22} = VALID_PIXEL_MODE;
859 let Word1{29-23} = CF_INST;
860 let Word1{30} = WHOLE_QUAD_MODE;
861 let Word1{31} = BARRIER;
864 class CF_CLAUSE_R600 <bits<7> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
865 ins, AsmPrint, [] >, CF_WORD0_R600, CF_WORD1_R600 {
871 let VALID_PIXEL_MODE = 0;
875 let END_OF_PROGRAM = 0;
876 let WHOLE_QUAD_MODE = 0;
878 let Inst{31-0} = Word0;
879 let Inst{63-32} = Word1;
883 field bits<32> Word0;
886 bits<3> JUMPTABLE_SEL;
888 let Word0{23-0} = ADDR;
889 let Word0{26-24} = JUMPTABLE_SEL;
893 field bits<32> Word1;
899 bits<1> VALID_PIXEL_MODE;
900 bits<1> END_OF_PROGRAM;
904 let Word1{2-0} = POP_COUNT;
905 let Word1{7-3} = CF_CONST;
906 let Word1{9-8} = COND;
907 let Word1{15-10} = COUNT;
908 let Word1{20} = VALID_PIXEL_MODE;
909 let Word1{29-22} = CF_INST;
910 let Word1{31} = BARRIER;
913 class CF_CLAUSE_EG <bits<8> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
914 ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG {
919 let JUMPTABLE_SEL = 0;
921 let VALID_PIXEL_MODE = 0;
923 let END_OF_PROGRAM = 0;
925 let Inst{31-0} = Word0;
926 let Inst{63-32} = Word1;
929 def CF_ALU : ALU_CLAUSE<8, "ALU">;
930 def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">;
932 def PAD : AMDGPUInst <(outs), (ins), "PAD", [] > {
936 let Predicates = [isR600toCayman] in {
938 //===----------------------------------------------------------------------===//
939 // Common Instructions R600, R700, Evergreen, Cayman
940 //===----------------------------------------------------------------------===//
942 def ADD : R600_2OP_Helper <0x0, "ADD", fadd>;
943 // Non-IEEE MUL: 0 * anything = 0
944 def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE", int_AMDGPU_mul>;
945 def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>;
946 def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax>;
947 def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin>;
949 // For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
950 // so some of the instruction names don't match the asm string.
951 // XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
952 def SETE : R600_2OP <
954 [(set R600_Reg32:$dst,
955 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
961 [(set R600_Reg32:$dst,
962 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
968 [(set R600_Reg32:$dst,
969 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
975 [(set R600_Reg32:$dst,
976 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
980 def SETE_DX10 : R600_2OP <
982 [(set R600_Reg32:$dst,
983 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
987 def SETGT_DX10 : R600_2OP <
989 [(set R600_Reg32:$dst,
990 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
994 def SETGE_DX10 : R600_2OP <
996 [(set R600_Reg32:$dst,
997 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
1001 def SETNE_DX10 : R600_2OP <
1003 [(set R600_Reg32:$dst,
1004 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
1008 def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>;
1009 def TRUNC : R600_1OP_Helper <0x11, "TRUNC", int_AMDGPU_trunc>;
1010 def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;
1011 def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>;
1012 def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>;
1014 def MOV : R600_1OP <0x19, "MOV", []>;
1016 let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in {
1018 class MOV_IMM <ValueType vt, Operand immType> : AMDGPUInst <
1019 (outs R600_Reg32:$dst),
1025 } // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1
1027 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
1030 (MOV_IMM_I32 imm:$val)
1033 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
1036 (MOV_IMM_F32 fpimm:$val)
1039 def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>;
1040 def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>;
1041 def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>;
1042 def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>;
1044 let hasSideEffects = 1 in {
1046 def KILLGT : R600_2OP <0x2D, "KILLGT", []>;
1048 } // end hasSideEffects
1050 def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>;
1051 def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>;
1052 def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>;
1053 def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>;
1054 def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>;
1055 def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>;
1056 def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", AMDGPUsmax>;
1057 def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", AMDGPUsmin>;
1058 def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", AMDGPUumax>;
1059 def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", AMDGPUumin>;
1061 def SETE_INT : R600_2OP <
1063 [(set (i32 R600_Reg32:$dst),
1064 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))]
1067 def SETGT_INT : R600_2OP <
1069 [(set (i32 R600_Reg32:$dst),
1070 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))]
1073 def SETGE_INT : R600_2OP <
1075 [(set (i32 R600_Reg32:$dst),
1076 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
1079 def SETNE_INT : R600_2OP <
1081 [(set (i32 R600_Reg32:$dst),
1082 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
1085 def SETGT_UINT : R600_2OP <
1087 [(set (i32 R600_Reg32:$dst),
1088 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))]
1091 def SETGE_UINT : R600_2OP <
1093 [(set (i32 R600_Reg32:$dst),
1094 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
1097 def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>;
1098 def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>;
1099 def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>;
1100 def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>;
1102 def CNDE_INT : R600_3OP <
1104 [(set (i32 R600_Reg32:$dst),
1105 (selectcc (i32 R600_Reg32:$src0), 0,
1106 (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
1110 def CNDGE_INT : R600_3OP <
1112 [(set (i32 R600_Reg32:$dst),
1113 (selectcc (i32 R600_Reg32:$src0), 0,
1114 (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
1118 def CNDGT_INT : R600_3OP <
1120 [(set (i32 R600_Reg32:$dst),
1121 (selectcc (i32 R600_Reg32:$src0), 0,
1122 (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
1126 //===----------------------------------------------------------------------===//
1127 // Texture instructions
1128 //===----------------------------------------------------------------------===//
1130 def TEX_LD : R600_TEX <
1132 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txf R600_Reg128:$SRC_GPR,
1133 imm:$OFFSET_X, imm:$OFFSET_Y, imm:$OFFSET_Z, imm:$RESOURCE_ID,
1134 imm:$SAMPLER_ID, imm:$textureTarget))]
1136 let AsmString = "TEX_LD $DST_GPR, $SRC_GPR, $OFFSET_X, $OFFSET_Y, $OFFSET_Z,"
1137 "$RESOURCE_ID, $SAMPLER_ID, $textureTarget";
1138 let InOperandList = (ins R600_Reg128:$SRC_GPR, i32imm:$OFFSET_X,
1139 i32imm:$OFFSET_Y, i32imm:$OFFSET_Z, i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID,
1140 i32imm:$textureTarget);
1143 def TEX_GET_TEXTURE_RESINFO : R600_TEX <
1144 0x04, "TEX_GET_TEXTURE_RESINFO",
1145 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txq R600_Reg128:$SRC_GPR,
1146 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1149 def TEX_GET_GRADIENTS_H : R600_TEX <
1150 0x07, "TEX_GET_GRADIENTS_H",
1151 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_ddx R600_Reg128:$SRC_GPR,
1152 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1155 def TEX_GET_GRADIENTS_V : R600_TEX <
1156 0x08, "TEX_GET_GRADIENTS_V",
1157 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_ddy R600_Reg128:$SRC_GPR,
1158 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1161 def TEX_SET_GRADIENTS_H : R600_TEX <
1162 0x0B, "TEX_SET_GRADIENTS_H",
1166 def TEX_SET_GRADIENTS_V : R600_TEX <
1167 0x0C, "TEX_SET_GRADIENTS_V",
1171 def TEX_SAMPLE : R600_TEX <
1173 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_tex R600_Reg128:$SRC_GPR,
1174 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1177 def TEX_SAMPLE_C : R600_TEX <
1178 0x18, "TEX_SAMPLE_C",
1179 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_tex R600_Reg128:$SRC_GPR,
1180 imm:$RESOURCE_ID, imm:$SAMPLER_ID, TEX_SHADOW:$textureTarget))]
1183 def TEX_SAMPLE_L : R600_TEX <
1184 0x11, "TEX_SAMPLE_L",
1185 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txl R600_Reg128:$SRC_GPR,
1186 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1189 def TEX_SAMPLE_C_L : R600_TEX <
1190 0x19, "TEX_SAMPLE_C_L",
1191 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txl R600_Reg128:$SRC_GPR,
1192 imm:$RESOURCE_ID, imm:$SAMPLER_ID, TEX_SHADOW:$textureTarget))]
1195 def TEX_SAMPLE_LB : R600_TEX <
1196 0x12, "TEX_SAMPLE_LB",
1197 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txb R600_Reg128:$SRC_GPR,
1198 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1201 def TEX_SAMPLE_C_LB : R600_TEX <
1202 0x1A, "TEX_SAMPLE_C_LB",
1203 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txb R600_Reg128:$SRC_GPR,
1204 imm:$RESOURCE_ID, imm:$SAMPLER_ID, TEX_SHADOW:$textureTarget))]
1207 def TEX_SAMPLE_G : R600_TEX <
1208 0x14, "TEX_SAMPLE_G",
1212 def TEX_SAMPLE_C_G : R600_TEX <
1213 0x1C, "TEX_SAMPLE_C_G",
1217 //===----------------------------------------------------------------------===//
1218 // Helper classes for common instructions
1219 //===----------------------------------------------------------------------===//
1221 class MUL_LIT_Common <bits<5> inst> : R600_3OP <
1226 class MULADD_Common <bits<5> inst> : R600_3OP <
1231 class MULADD_IEEE_Common <bits<5> inst> : R600_3OP <
1232 inst, "MULADD_IEEE",
1233 [(set (f32 R600_Reg32:$dst),
1234 (fadd (fmul R600_Reg32:$src0, R600_Reg32:$src1), R600_Reg32:$src2))]
1237 class CNDE_Common <bits<5> inst> : R600_3OP <
1239 [(set R600_Reg32:$dst,
1240 (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
1241 (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
1245 class CNDGT_Common <bits<5> inst> : R600_3OP <
1247 [(set R600_Reg32:$dst,
1248 (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
1249 (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
1253 class CNDGE_Common <bits<5> inst> : R600_3OP <
1255 [(set R600_Reg32:$dst,
1256 (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
1257 (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
1261 multiclass DOT4_Common <bits<11> inst> {
1263 def _pseudo : R600_REDUCTION <inst,
1264 (ins R600_Reg128:$src0, R600_Reg128:$src1),
1265 "DOT4 $dst $src0, $src1",
1266 [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))]
1269 def _real : R600_2OP <inst, "DOT4", []>;
1272 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
1273 multiclass CUBE_Common <bits<11> inst> {
1275 def _pseudo : InstR600 <
1277 (outs R600_Reg128:$dst),
1278 (ins R600_Reg128:$src),
1280 [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))],
1286 def _real : R600_2OP <inst, "CUBE", []>;
1288 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
1290 class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1291 inst, "EXP_IEEE", fexp2
1294 class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper <
1295 inst, "FLT_TO_INT", fp_to_sint
1298 class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1299 inst, "INT_TO_FLT", sint_to_fp
1302 class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1303 inst, "FLT_TO_UINT", fp_to_uint
1306 class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1307 inst, "UINT_TO_FLT", uint_to_fp
1310 class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <
1311 inst, "LOG_CLAMPED", []
1314 class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1315 inst, "LOG_IEEE", flog2
1318 class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>;
1319 class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>;
1320 class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>;
1321 class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper <
1322 inst, "MULHI_INT", mulhs
1324 class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper <
1325 inst, "MULHI", mulhu
1327 class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper <
1328 inst, "MULLO_INT", mul
1330 class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []>;
1332 class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <
1333 inst, "RECIP_CLAMPED", []
1336 class RECIP_IEEE_Common <bits<11> inst> : R600_1OP <
1337 inst, "RECIP_IEEE", [(set R600_Reg32:$dst, (fdiv FP_ONE, R600_Reg32:$src0))]
1340 class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1341 inst, "RECIP_UINT", AMDGPUurecip
1344 class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper <
1345 inst, "RECIPSQRT_CLAMPED", int_AMDGPU_rsq
1348 class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP <
1349 inst, "RECIPSQRT_IEEE", []
1352 class SIN_Common <bits<11> inst> : R600_1OP <
1357 class COS_Common <bits<11> inst> : R600_1OP <
1362 //===----------------------------------------------------------------------===//
1363 // Helper patterns for complex intrinsics
1364 //===----------------------------------------------------------------------===//
1366 multiclass DIV_Common <InstR600 recip_ieee> {
1368 (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
1369 (MUL_IEEE R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
1373 (fdiv R600_Reg32:$src0, R600_Reg32:$src1),
1374 (MUL_IEEE R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
1378 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat <
1379 (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w),
1380 (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x))
1383 //===----------------------------------------------------------------------===//
1384 // R600 / R700 Instructions
1385 //===----------------------------------------------------------------------===//
1387 let Predicates = [isR600] in {
1389 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
1390 def MULADD_r600 : MULADD_Common<0x10>;
1391 def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>;
1392 def CNDE_r600 : CNDE_Common<0x18>;
1393 def CNDGT_r600 : CNDGT_Common<0x19>;
1394 def CNDGE_r600 : CNDGE_Common<0x1A>;
1395 defm DOT4_r600 : DOT4_Common<0x50>;
1396 defm CUBE_r600 : CUBE_Common<0x52>;
1397 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
1398 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
1399 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
1400 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
1401 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
1402 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
1403 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
1404 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
1405 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
1406 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
1407 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
1408 def SIN_r600 : SIN_Common<0x6E>;
1409 def COS_r600 : COS_Common<0x6F>;
1410 def ASHR_r600 : ASHR_Common<0x70>;
1411 def LSHR_r600 : LSHR_Common<0x71>;
1412 def LSHL_r600 : LSHL_Common<0x72>;
1413 def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
1414 def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
1415 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
1416 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
1417 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
1419 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
1420 def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL, R600_Reg32>;
1421 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
1423 def : Pat<(fsqrt R600_Reg32:$src),
1424 (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_r600 R600_Reg32:$src))>;
1426 def R600_ExportSwz : ExportSwzInst {
1427 let Word1{20-17} = 0; // BURST_COUNT
1428 let Word1{21} = eop;
1429 let Word1{22} = 1; // VALID_PIXEL_MODE
1430 let Word1{30-23} = inst;
1431 let Word1{31} = 1; // BARRIER
1433 defm : ExportPattern<R600_ExportSwz, 39>;
1435 def R600_ExportBuf : ExportBufInst {
1436 let Word1{20-17} = 0; // BURST_COUNT
1437 let Word1{21} = eop;
1438 let Word1{22} = 1; // VALID_PIXEL_MODE
1439 let Word1{30-23} = inst;
1440 let Word1{31} = 1; // BARRIER
1442 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>;
1444 def CF_TC_R600 : CF_CLAUSE_R600<1, (ins i32imm:$ADDR, i32imm:$COUNT),
1445 "TEX $COUNT @$ADDR"> {
1448 def CF_VC_R600 : CF_CLAUSE_R600<2, (ins i32imm:$ADDR, i32imm:$COUNT),
1449 "VTX $COUNT @$ADDR"> {
1452 def WHILE_LOOP_R600 : CF_CLAUSE_R600<6, (ins i32imm:$ADDR),
1453 "LOOP_START_DX10 @$ADDR"> {
1457 def END_LOOP_R600 : CF_CLAUSE_R600<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1461 def LOOP_BREAK_R600 : CF_CLAUSE_R600<9, (ins i32imm:$ADDR),
1462 "LOOP_BREAK @$ADDR"> {
1466 def CF_CONTINUE_R600 : CF_CLAUSE_R600<8, (ins i32imm:$ADDR),
1467 "CONTINUE @$ADDR"> {
1471 def CF_JUMP_R600 : CF_CLAUSE_R600<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1472 "JUMP @$ADDR POP:$POP_COUNT"> {
1475 def CF_ELSE_R600 : CF_CLAUSE_R600<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1476 "ELSE @$ADDR POP:$POP_COUNT"> {
1479 def CF_CALL_FS_R600 : CF_CLAUSE_R600<19, (ins), "CALL_FS"> {
1484 def POP_R600 : CF_CLAUSE_R600<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1485 "POP @$ADDR POP:$POP_COUNT"> {
1488 def CF_END_R600 : CF_CLAUSE_R600<0, (ins), "CF_END"> {
1492 let END_OF_PROGRAM = 1;
1497 // Helper pattern for normalizing inputs to triginomic instructions for R700+
1499 class COS_PAT <InstR600 trig> : Pat<
1500 (fcos R600_Reg32:$src),
1501 (trig (MUL_IEEE (MOV_IMM_I32 CONST.TWO_PI_INV), R600_Reg32:$src))
1504 class SIN_PAT <InstR600 trig> : Pat<
1505 (fsin R600_Reg32:$src),
1506 (trig (MUL_IEEE (MOV_IMM_I32 CONST.TWO_PI_INV), R600_Reg32:$src))
1509 //===----------------------------------------------------------------------===//
1510 // R700 Only instructions
1511 //===----------------------------------------------------------------------===//
1513 let Predicates = [isR700] in {
1514 def SIN_r700 : SIN_Common<0x6E>;
1515 def COS_r700 : COS_Common<0x6F>;
1517 // R700 normalizes inputs to SIN/COS the same as EG
1518 def : SIN_PAT <SIN_r700>;
1519 def : COS_PAT <COS_r700>;
1522 //===----------------------------------------------------------------------===//
1523 // Evergreen Only instructions
1524 //===----------------------------------------------------------------------===//
1526 let Predicates = [isEG] in {
1528 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
1529 defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
1531 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
1532 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
1533 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
1534 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
1535 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
1536 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
1537 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
1538 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
1539 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
1540 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
1541 def SIN_eg : SIN_Common<0x8D>;
1542 def COS_eg : COS_Common<0x8E>;
1544 def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL, R600_Reg32>;
1545 def : SIN_PAT <SIN_eg>;
1546 def : COS_PAT <COS_eg>;
1547 def : Pat<(fsqrt R600_Reg32:$src),
1548 (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_eg R600_Reg32:$src))>;
1549 } // End Predicates = [isEG]
1551 //===----------------------------------------------------------------------===//
1552 // Evergreen / Cayman Instructions
1553 //===----------------------------------------------------------------------===//
1555 let Predicates = [isEGorCayman] in {
1557 // BFE_UINT - bit_extract, an optimization for mask and shift
1562 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
1567 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0
1568 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
1569 // (16,8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
1570 // (24,8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
1571 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
1572 [(set R600_Reg32:$dst, (int_AMDIL_bit_extract_u32 R600_Reg32:$src0,
1574 R600_Reg32:$src2))],
1578 def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", []>;
1579 defm : BFIPatterns <BFI_INT_eg>;
1581 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT",
1582 [(set R600_Reg32:$dst, (AMDGPUbitalign R600_Reg32:$src0, R600_Reg32:$src1,
1583 R600_Reg32:$src2))],
1587 def MULADD_eg : MULADD_Common<0x14>;
1588 def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>;
1589 def ASHR_eg : ASHR_Common<0x15>;
1590 def LSHR_eg : LSHR_Common<0x16>;
1591 def LSHL_eg : LSHL_Common<0x17>;
1592 def CNDE_eg : CNDE_Common<0x19>;
1593 def CNDGT_eg : CNDGT_Common<0x1A>;
1594 def CNDGE_eg : CNDGE_Common<0x1B>;
1595 def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
1596 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
1597 defm DOT4_eg : DOT4_Common<0xBE>;
1598 defm CUBE_eg : CUBE_Common<0xC0>;
1600 let hasSideEffects = 1 in {
1601 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", []>;
1604 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
1606 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
1610 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
1612 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
1616 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
1618 // TRUNC is used for the FLT_TO_INT instructions to work around a
1619 // perceived problem where the rounding modes are applied differently
1620 // depending on the instruction and the slot they are in.
1622 // https://bugs.freedesktop.org/show_bug.cgi?id=50232
1623 // Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c
1625 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
1626 // which do not need to be truncated since the fp values are 0.0f or 1.0f.
1627 // We should look into handling these cases separately.
1628 def : Pat<(fp_to_sint R600_Reg32:$src0),
1629 (FLT_TO_INT_eg (TRUNC R600_Reg32:$src0))>;
1631 def : Pat<(fp_to_uint R600_Reg32:$src0),
1632 (FLT_TO_UINT_eg (TRUNC R600_Reg32:$src0))>;
1634 def EG_ExportSwz : ExportSwzInst {
1635 let Word1{19-16} = 0; // BURST_COUNT
1636 let Word1{20} = 1; // VALID_PIXEL_MODE
1637 let Word1{21} = eop;
1638 let Word1{29-22} = inst;
1639 let Word1{30} = 0; // MARK
1640 let Word1{31} = 1; // BARRIER
1642 defm : ExportPattern<EG_ExportSwz, 83>;
1644 def EG_ExportBuf : ExportBufInst {
1645 let Word1{19-16} = 0; // BURST_COUNT
1646 let Word1{20} = 1; // VALID_PIXEL_MODE
1647 let Word1{21} = eop;
1648 let Word1{29-22} = inst;
1649 let Word1{30} = 0; // MARK
1650 let Word1{31} = 1; // BARRIER
1652 defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>;
1654 def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT),
1655 "TEX $COUNT @$ADDR"> {
1658 def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT),
1659 "VTX $COUNT @$ADDR"> {
1662 def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR),
1663 "LOOP_START_DX10 @$ADDR"> {
1667 def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1671 def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR),
1672 "LOOP_BREAK @$ADDR"> {
1676 def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR),
1677 "CONTINUE @$ADDR"> {
1681 def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1682 "JUMP @$ADDR POP:$POP_COUNT"> {
1685 def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1686 "ELSE @$ADDR POP:$POP_COUNT"> {
1689 def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> {
1694 def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1695 "POP @$ADDR POP:$POP_COUNT"> {
1698 def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> {
1702 let END_OF_PROGRAM = 1;
1705 //===----------------------------------------------------------------------===//
1706 // Memory read/write instructions
1707 //===----------------------------------------------------------------------===//
1708 let usesCustomInserter = 1 in {
1710 class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> comp_mask, string name,
1712 : EG_CF_RAT <0x57, 0x2, 0, (outs), ins,
1713 !strconcat(name, " $rw_gpr, $index_gpr, $eop"), pattern> {
1715 // XXX: Have a separate instruction for non-indexed writes.
1721 let COMP_MASK = comp_mask;
1722 let BURST_COUNT = 0;
1728 } // End usesCustomInserter = 1
1731 def RAT_WRITE_CACHELESS_32_eg : RAT_WRITE_CACHELESS_eg <
1732 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1733 0x1, "RAT_WRITE_CACHELESS_32_eg",
1734 [(global_store (i32 R600_TReg32_X:$rw_gpr), R600_TReg32_X:$index_gpr)]
1738 def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg <
1739 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1740 0xf, "RAT_WRITE_CACHELESS_128",
1741 [(global_store (v4i32 R600_Reg128:$rw_gpr), R600_TReg32_X:$index_gpr)]
1744 class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
1745 : InstR600ISA <outs, (ins MEMxi:$ptr), name#" $dst, $ptr", pattern>,
1746 VTX_WORD1_GPR, VTX_WORD0 {
1751 let FETCH_WHOLE_QUAD = 0;
1752 let BUFFER_ID = buffer_id;
1754 // XXX: We can infer this field based on the SRC_GPR. This would allow us
1755 // to store vertex addresses in any channel, not just X.
1758 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,
1759 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,
1760 // however, based on my testing if USE_CONST_FIELDS is set, then all
1761 // these fields need to be set to 0.
1762 let USE_CONST_FIELDS = 0;
1763 let NUM_FORMAT_ALL = 1;
1764 let FORMAT_COMP_ALL = 0;
1765 let SRF_MODE_ALL = 0;
1767 let Inst{31-0} = Word0;
1768 let Inst{63-32} = Word1;
1769 // LLVM can only encode 64-bit instructions, so these fields are manually
1770 // encoded in R600CodeEmitter
1773 // bits<2> ENDIAN_SWAP = 0;
1774 // bits<1> CONST_BUF_NO_STRIDE = 0;
1775 // bits<1> MEGA_FETCH = 0;
1776 // bits<1> ALT_CONST = 0;
1777 // bits<2> BUFFER_INDEX_MODE = 0;
1781 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1782 // is done in R600CodeEmitter
1784 // Inst{79-64} = OFFSET;
1785 // Inst{81-80} = ENDIAN_SWAP;
1786 // Inst{82} = CONST_BUF_NO_STRIDE;
1787 // Inst{83} = MEGA_FETCH;
1788 // Inst{84} = ALT_CONST;
1789 // Inst{86-85} = BUFFER_INDEX_MODE;
1790 // Inst{95-86} = 0; Reserved
1792 // VTX_WORD3 (Padding)
1794 // Inst{127-96} = 0;
1797 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
1798 : VTX_READ_eg <"VTX_READ_8", buffer_id, (outs R600_TReg32_X:$dst),
1801 let MEGA_FETCH_COUNT = 1;
1803 let DST_SEL_Y = 7; // Masked
1804 let DST_SEL_Z = 7; // Masked
1805 let DST_SEL_W = 7; // Masked
1806 let DATA_FORMAT = 1; // FMT_8
1809 class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
1810 : VTX_READ_eg <"VTX_READ_16", buffer_id, (outs R600_TReg32_X:$dst),
1812 let MEGA_FETCH_COUNT = 2;
1814 let DST_SEL_Y = 7; // Masked
1815 let DST_SEL_Z = 7; // Masked
1816 let DST_SEL_W = 7; // Masked
1817 let DATA_FORMAT = 5; // FMT_16
1821 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
1822 : VTX_READ_eg <"VTX_READ_32", buffer_id, (outs R600_TReg32_X:$dst),
1825 let MEGA_FETCH_COUNT = 4;
1827 let DST_SEL_Y = 7; // Masked
1828 let DST_SEL_Z = 7; // Masked
1829 let DST_SEL_W = 7; // Masked
1830 let DATA_FORMAT = 0xD; // COLOR_32
1832 // This is not really necessary, but there were some GPU hangs that appeared
1833 // to be caused by ALU instructions in the next instruction group that wrote
1834 // to the $ptr registers of the VTX_READ.
1836 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
1837 // %T2_X<def> = MOV %ZERO
1838 //Adding this constraint prevents this from happening.
1839 let Constraints = "$ptr.ptr = $dst";
1842 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
1843 : VTX_READ_eg <"VTX_READ_128", buffer_id, (outs R600_Reg128:$dst),
1846 let MEGA_FETCH_COUNT = 16;
1851 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
1853 // XXX: Need to force VTX_READ_128 instructions to write to the same register
1854 // that holds its buffer address to avoid potential hangs. We can't use
1855 // the same constraint as VTX_READ_32_eg, because the $ptr.ptr and $dst
1856 // registers are different sizes.
1859 //===----------------------------------------------------------------------===//
1860 // VTX Read from parameter memory space
1861 //===----------------------------------------------------------------------===//
1863 def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <0,
1864 [(set (i32 R600_TReg32_X:$dst), (load_param_zexti8 ADDRVTX_READ:$ptr))]
1867 def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <0,
1868 [(set (i32 R600_TReg32_X:$dst), (load_param_zexti16 ADDRVTX_READ:$ptr))]
1871 def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0,
1872 [(set (i32 R600_TReg32_X:$dst), (load_param ADDRVTX_READ:$ptr))]
1875 def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <0,
1876 [(set (v4i32 R600_Reg128:$dst), (load_param ADDRVTX_READ:$ptr))]
1879 //===----------------------------------------------------------------------===//
1880 // VTX Read from global memory space
1881 //===----------------------------------------------------------------------===//
1884 def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1,
1885 [(set (i32 R600_TReg32_X:$dst), (zextloadi8_global ADDRVTX_READ:$ptr))]
1889 def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1,
1890 [(set (i32 R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))]
1894 def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
1895 [(set (v4i32 R600_Reg128:$dst), (global_load ADDRVTX_READ:$ptr))]
1898 //===----------------------------------------------------------------------===//
1900 // XXX: We are currently storing all constants in the global address space.
1901 //===----------------------------------------------------------------------===//
1903 def CONSTANT_LOAD_eg : VTX_READ_32_eg <1,
1904 [(set (i32 R600_TReg32_X:$dst), (constant_load ADDRVTX_READ:$ptr))]
1909 //===----------------------------------------------------------------------===//
1910 // Regist loads and stores - for indirect addressing
1911 //===----------------------------------------------------------------------===//
1913 defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>;
1915 let Predicates = [isCayman] in {
1917 let isVector = 1 in {
1919 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
1921 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
1922 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
1923 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
1924 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
1925 def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>;
1926 def EXP_IEEE_cm : EXP_IEEE_Common<0x81>;
1927 def LOG_IEEE_cm : LOG_IEEE_Common<0x83>;
1928 def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>;
1929 def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>;
1930 def SIN_cm : SIN_Common<0x8D>;
1931 def COS_cm : COS_Common<0x8E>;
1932 } // End isVector = 1
1934 def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL, R600_Reg32>;
1935 def : SIN_PAT <SIN_cm>;
1936 def : COS_PAT <COS_cm>;
1938 defm DIV_cm : DIV_Common<RECIP_IEEE_cm>;
1940 // RECIP_UINT emulation for Cayman
1941 // The multiplication scales from [0,1] to the unsigned integer range
1943 (AMDGPUurecip R600_Reg32:$src0),
1944 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg R600_Reg32:$src0)),
1945 (MOV_IMM_I32 CONST.FP_UINT_MAX_PLUS_1)))
1948 def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> {
1954 def : Pat<(fsqrt R600_Reg32:$src),
1955 (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm R600_Reg32:$src))>;
1959 //===----------------------------------------------------------------------===//
1960 // Branch Instructions
1961 //===----------------------------------------------------------------------===//
1964 def IF_PREDICATE_SET : ILFormat<(outs), (ins GPRI32:$src),
1965 "IF_PREDICATE_SET $src", []>;
1967 def PREDICATED_BREAK : ILFormat<(outs), (ins GPRI32:$src),
1968 "PREDICATED_BREAK $src", []>;
1970 //===----------------------------------------------------------------------===//
1971 // Pseudo instructions
1972 //===----------------------------------------------------------------------===//
1974 let isPseudo = 1 in {
1976 def PRED_X : InstR600 <
1977 0, (outs R600_Predicate_Bit:$dst),
1978 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
1980 let FlagOperandIdx = 3;
1983 let isTerminator = 1, isBranch = 1 in {
1984 def JUMP_COND : InstR600 <0x10,
1986 (ins brtarget:$target, R600_Predicate_Bit:$p),
1987 "JUMP $target ($p)",
1991 def JUMP : InstR600 <0x10,
1993 (ins brtarget:$target),
1998 let isPredicable = 1;
2002 } // End isTerminator = 1, isBranch = 1
2004 let usesCustomInserter = 1 in {
2006 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
2008 def MASK_WRITE : AMDGPUShaderInst <
2010 (ins R600_Reg32:$src),
2015 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 1
2018 def TXD: AMDGPUShaderInst <
2019 (outs R600_Reg128:$dst),
2020 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
2021 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
2022 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
2025 def TXD_SHADOW: AMDGPUShaderInst <
2026 (outs R600_Reg128:$dst),
2027 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
2028 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
2029 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))]
2032 } // End isPseudo = 1
2033 } // End usesCustomInserter = 1
2035 def CLAMP_R600 : CLAMP <R600_Reg32>;
2036 def FABS_R600 : FABS<R600_Reg32>;
2037 def FNEG_R600 : FNEG<R600_Reg32>;
2039 //===---------------------------------------------------------------------===//
2040 // Return instruction
2041 //===---------------------------------------------------------------------===//
2042 let isTerminator = 1, isReturn = 1, hasCtrlDep = 1,
2043 usesCustomInserter = 1 in {
2044 def RETURN : ILFormat<(outs), (ins variable_ops),
2045 "RETURN", [(IL_retflag)]>;
2049 //===----------------------------------------------------------------------===//
2050 // Constant Buffer Addressing Support
2051 //===----------------------------------------------------------------------===//
2053 let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
2054 def CONST_COPY : Instruction {
2055 let OutOperandList = (outs R600_Reg32:$dst);
2056 let InOperandList = (ins i32imm:$src);
2058 [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];
2059 let AsmString = "CONST_COPY";
2060 let neverHasSideEffects = 1;
2061 let isAsCheapAsAMove = 1;
2062 let Itinerary = NullALU;
2064 } // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
2066 def TEX_VTX_CONSTBUF :
2067 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "VTX_READ_eg $dst, $ptr",
2068 [(set R600_Reg128:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$BUFFER_ID)))]>,
2069 VTX_WORD1_GPR, VTX_WORD0 {
2073 let FETCH_WHOLE_QUAD = 0;
2077 let USE_CONST_FIELDS = 0;
2078 let NUM_FORMAT_ALL = 2;
2079 let FORMAT_COMP_ALL = 1;
2080 let SRF_MODE_ALL = 1;
2081 let MEGA_FETCH_COUNT = 16;
2086 let DATA_FORMAT = 35;
2088 let Inst{31-0} = Word0;
2089 let Inst{63-32} = Word1;
2091 // LLVM can only encode 64-bit instructions, so these fields are manually
2092 // encoded in R600CodeEmitter
2095 // bits<2> ENDIAN_SWAP = 0;
2096 // bits<1> CONST_BUF_NO_STRIDE = 0;
2097 // bits<1> MEGA_FETCH = 0;
2098 // bits<1> ALT_CONST = 0;
2099 // bits<2> BUFFER_INDEX_MODE = 0;
2103 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
2104 // is done in R600CodeEmitter
2106 // Inst{79-64} = OFFSET;
2107 // Inst{81-80} = ENDIAN_SWAP;
2108 // Inst{82} = CONST_BUF_NO_STRIDE;
2109 // Inst{83} = MEGA_FETCH;
2110 // Inst{84} = ALT_CONST;
2111 // Inst{86-85} = BUFFER_INDEX_MODE;
2112 // Inst{95-86} = 0; Reserved
2114 // VTX_WORD3 (Padding)
2116 // Inst{127-96} = 0;
2120 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr",
2121 [(set R600_Reg128:$dst, (int_R600_load_texbuf ADDRGA_VAR_OFFSET:$ptr, imm:$BUFFER_ID))]>,
2122 VTX_WORD1_GPR, VTX_WORD0 {
2126 let FETCH_WHOLE_QUAD = 0;
2130 let USE_CONST_FIELDS = 1;
2131 let NUM_FORMAT_ALL = 0;
2132 let FORMAT_COMP_ALL = 0;
2133 let SRF_MODE_ALL = 1;
2134 let MEGA_FETCH_COUNT = 16;
2139 let DATA_FORMAT = 0;
2141 let Inst{31-0} = Word0;
2142 let Inst{63-32} = Word1;
2144 // LLVM can only encode 64-bit instructions, so these fields are manually
2145 // encoded in R600CodeEmitter
2148 // bits<2> ENDIAN_SWAP = 0;
2149 // bits<1> CONST_BUF_NO_STRIDE = 0;
2150 // bits<1> MEGA_FETCH = 0;
2151 // bits<1> ALT_CONST = 0;
2152 // bits<2> BUFFER_INDEX_MODE = 0;
2156 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
2157 // is done in R600CodeEmitter
2159 // Inst{79-64} = OFFSET;
2160 // Inst{81-80} = ENDIAN_SWAP;
2161 // Inst{82} = CONST_BUF_NO_STRIDE;
2162 // Inst{83} = MEGA_FETCH;
2163 // Inst{84} = ALT_CONST;
2164 // Inst{86-85} = BUFFER_INDEX_MODE;
2165 // Inst{95-86} = 0; Reserved
2167 // VTX_WORD3 (Padding)
2169 // Inst{127-96} = 0;
2174 //===--------------------------------------------------------------------===//
2175 // Instructions support
2176 //===--------------------------------------------------------------------===//
2177 //===---------------------------------------------------------------------===//
2178 // Custom Inserter for Branches and returns, this eventually will be a
2180 //===---------------------------------------------------------------------===//
2181 let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in {
2182 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
2183 "; Pseudo unconditional branch instruction",
2185 defm BRANCH_COND : BranchConditional<IL_brcond>;
2188 //===---------------------------------------------------------------------===//
2189 // Flow and Program control Instructions
2190 //===---------------------------------------------------------------------===//
2191 let isTerminator=1 in {
2192 def SWITCH : ILFormat< (outs), (ins GPRI32:$src),
2193 !strconcat("SWITCH", " $src"), []>;
2194 def CASE : ILFormat< (outs), (ins GPRI32:$src),
2195 !strconcat("CASE", " $src"), []>;
2196 def BREAK : ILFormat< (outs), (ins),
2198 def CONTINUE : ILFormat< (outs), (ins),
2200 def DEFAULT : ILFormat< (outs), (ins),
2202 def ELSE : ILFormat< (outs), (ins),
2204 def ENDSWITCH : ILFormat< (outs), (ins),
2206 def ENDMAIN : ILFormat< (outs), (ins),
2208 def END : ILFormat< (outs), (ins),
2210 def ENDFUNC : ILFormat< (outs), (ins),
2212 def ENDIF : ILFormat< (outs), (ins),
2214 def WHILELOOP : ILFormat< (outs), (ins),
2216 def ENDLOOP : ILFormat< (outs), (ins),
2218 def FUNC : ILFormat< (outs), (ins),
2220 def RETDYN : ILFormat< (outs), (ins),
2222 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2223 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">;
2224 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2225 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">;
2226 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2227 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">;
2228 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2229 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">;
2230 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2231 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">;
2232 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2233 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">;
2234 defm IFC : BranchInstr2<"IFC">;
2235 defm BREAKC : BranchInstr2<"BREAKC">;
2236 defm CONTINUEC : BranchInstr2<"CONTINUEC">;
2239 //===----------------------------------------------------------------------===//
2241 //===----------------------------------------------------------------------===//
2243 // CND*_INT Pattterns for f32 True / False values
2245 class CND_INT_f32 <InstR600 cnd, CondCode cc> : Pat <
2246 (selectcc (i32 R600_Reg32:$src0), 0, (f32 R600_Reg32:$src1),
2247 R600_Reg32:$src2, cc),
2248 (cnd R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2)
2251 def : CND_INT_f32 <CNDE_INT, SETEQ>;
2252 def : CND_INT_f32 <CNDGT_INT, SETGT>;
2253 def : CND_INT_f32 <CNDGE_INT, SETGE>;
2255 //CNDGE_INT extra pattern
2257 (selectcc (i32 R600_Reg32:$src0), -1, (i32 R600_Reg32:$src1),
2258 (i32 R600_Reg32:$src2), COND_GT),
2259 (CNDGE_INT R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2)
2265 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
2269 (int_AMDGPU_kill R600_Reg32:$src0),
2270 (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
2275 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT),
2276 (SGT R600_Reg32:$src1, R600_Reg32:$src0)
2281 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LE),
2282 (SGE R600_Reg32:$src1, R600_Reg32:$src0)
2285 // SETGT_DX10 reverse args
2287 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, COND_LT),
2288 (SETGT_DX10 R600_Reg32:$src1, R600_Reg32:$src0)
2291 // SETGE_DX10 reverse args
2293 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, COND_LE),
2294 (SETGE_DX10 R600_Reg32:$src1, R600_Reg32:$src0)
2297 // SETGT_INT reverse args
2299 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT),
2300 (SETGT_INT R600_Reg32:$src1, R600_Reg32:$src0)
2303 // SETGE_INT reverse args
2305 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLE),
2306 (SETGE_INT R600_Reg32:$src1, R600_Reg32:$src0)
2309 // SETGT_UINT reverse args
2311 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT),
2312 (SETGT_UINT R600_Reg32:$src1, R600_Reg32:$src0)
2315 // SETGE_UINT reverse args
2317 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULE),
2318 (SETGE_UINT R600_Reg32:$src1, R600_Reg32:$src0)
2321 // The next two patterns are special cases for handling 'true if ordered' and
2322 // 'true if unordered' conditionals. The assumption here is that the behavior of
2323 // SETE and SNE conforms to the Direct3D 10 rules for floating point values
2325 // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit
2326 // We assume that SETE returns false when one of the operands is NAN and
2327 // SNE returns true when on of the operands is NAN
2329 //SETE - 'true if ordered'
2331 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO),
2332 (SETE R600_Reg32:$src0, R600_Reg32:$src1)
2335 //SETE_DX10 - 'true if ordered'
2337 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETO),
2338 (SETE_DX10 R600_Reg32:$src0, R600_Reg32:$src1)
2341 //SNE - 'true if unordered'
2343 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETUO),
2344 (SNE R600_Reg32:$src0, R600_Reg32:$src1)
2347 //SETNE_DX10 - 'true if ordered'
2349 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUO),
2350 (SETNE_DX10 R600_Reg32:$src0, R600_Reg32:$src1)
2353 def : Extract_Element <f32, v4f32, R600_Reg128, 0, sub0>;
2354 def : Extract_Element <f32, v4f32, R600_Reg128, 1, sub1>;
2355 def : Extract_Element <f32, v4f32, R600_Reg128, 2, sub2>;
2356 def : Extract_Element <f32, v4f32, R600_Reg128, 3, sub3>;
2358 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 0, sub0>;
2359 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 1, sub1>;
2360 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 2, sub2>;
2361 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 3, sub3>;
2363 def : Extract_Element <i32, v4i32, R600_Reg128, 0, sub0>;
2364 def : Extract_Element <i32, v4i32, R600_Reg128, 1, sub1>;
2365 def : Extract_Element <i32, v4i32, R600_Reg128, 2, sub2>;
2366 def : Extract_Element <i32, v4i32, R600_Reg128, 3, sub3>;
2368 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 0, sub0>;
2369 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 1, sub1>;
2370 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 2, sub2>;
2371 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 3, sub3>;
2373 def : Vector4_Build <v4f32, R600_Reg128, f32, R600_Reg32>;
2374 def : Vector4_Build <v4i32, R600_Reg128, i32, R600_Reg32>;
2376 // bitconvert patterns
2378 def : BitConvert <i32, f32, R600_Reg32>;
2379 def : BitConvert <f32, i32, R600_Reg32>;
2380 def : BitConvert <v4f32, v4i32, R600_Reg128>;
2381 def : BitConvert <v4i32, v4f32, R600_Reg128>;
2383 // DWORDADDR pattern
2384 def : DwordAddrPat <i32, R600_Reg32>;
2386 } // End isR600toCayman Predicate